JPS55135448A - Extracting system for manchester code clock - Google Patents

Extracting system for manchester code clock

Info

Publication number
JPS55135448A
JPS55135448A JP4253079A JP4253079A JPS55135448A JP S55135448 A JPS55135448 A JP S55135448A JP 4253079 A JP4253079 A JP 4253079A JP 4253079 A JP4253079 A JP 4253079A JP S55135448 A JPS55135448 A JP S55135448A
Authority
JP
Japan
Prior art keywords
signal
clock
circuit
extracting
manchester
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4253079A
Other languages
Japanese (ja)
Inventor
Tatsuo Chono
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP4253079A priority Critical patent/JPS55135448A/en
Publication of JPS55135448A publication Critical patent/JPS55135448A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To secure extracting of the clock signal which is synchronized with the reception Manchester signal with the reduced phase error, by resetting the divider dividing the clock of the integer-fold frequency via the normal code changing point signal and then extracting the division output in the form of the clock. CONSTITUTION:Differential pulse (c) is obtained in accordance with the rise and fall of Manchester code signal (a) in order to take in the count value of the integer n-fold clock (b) immediately before resetting counter 2 along with the scale decided by decision circuit 4. Then AND gate control 9 is given the pulse (c) via delay circuit 5 and decision output (d) in order to obtain code changing point signal (e). Divider circuit 6 is then reset with signal (e), and then circuit 6 is started again to obtain extracting clock (i). In case signal (e) is delivered mistakenly, the phase shift is reduced as much as possible through queuing circuit 7.
JP4253079A 1979-04-10 1979-04-10 Extracting system for manchester code clock Pending JPS55135448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4253079A JPS55135448A (en) 1979-04-10 1979-04-10 Extracting system for manchester code clock

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4253079A JPS55135448A (en) 1979-04-10 1979-04-10 Extracting system for manchester code clock

Publications (1)

Publication Number Publication Date
JPS55135448A true JPS55135448A (en) 1980-10-22

Family

ID=12638626

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4253079A Pending JPS55135448A (en) 1979-04-10 1979-04-10 Extracting system for manchester code clock

Country Status (1)

Country Link
JP (1) JPS55135448A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60256247A (en) * 1984-06-01 1985-12-17 Toshiba Corp Information transmission system
JP2006157221A (en) * 2004-11-26 2006-06-15 Pioneer Electronic Corp Signal decoding apparatus and signal decoding method
JP2015050741A (en) * 2013-09-04 2015-03-16 株式会社東芝 Radio communication device and radio communication method

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60256247A (en) * 1984-06-01 1985-12-17 Toshiba Corp Information transmission system
JPH0550901B2 (en) * 1984-06-01 1993-07-30 Tokyo Shibaura Electric Co
JP2006157221A (en) * 2004-11-26 2006-06-15 Pioneer Electronic Corp Signal decoding apparatus and signal decoding method
JP4486871B2 (en) * 2004-11-26 2010-06-23 パイオニア株式会社 Signal decoding apparatus and signal decoding method
JP2015050741A (en) * 2013-09-04 2015-03-16 株式会社東芝 Radio communication device and radio communication method

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