JPS5513549A - Timing phase synchronizing system - Google Patents

Timing phase synchronizing system

Info

Publication number
JPS5513549A
JPS5513549A JP8584278A JP8584278A JPS5513549A JP S5513549 A JPS5513549 A JP S5513549A JP 8584278 A JP8584278 A JP 8584278A JP 8584278 A JP8584278 A JP 8584278A JP S5513549 A JPS5513549 A JP S5513549A
Authority
JP
Japan
Prior art keywords
phase
zero
sampling
cross point
output signals
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP8584278A
Other languages
Japanese (ja)
Other versions
JPS6013624B2 (en
Inventor
Kazuo Murano
Tatsuki Hayashi
Shigeyuki Umigami
Fumio Amano
Yasukazu Ito
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP53085842A priority Critical patent/JPS6013624B2/en
Priority to SE7905913A priority patent/SE440015B/en
Priority to GB7923953A priority patent/GB2026796B/en
Priority to CA331,561A priority patent/CA1108246A/en
Priority to US06/056,641 priority patent/US4312075A/en
Priority to ES482447A priority patent/ES482447A1/en
Priority to AU48890/79A priority patent/AU525576B2/en
Priority to FR7918289A priority patent/FR2431228B1/en
Priority to DE19792928446 priority patent/DE2928446A1/en
Priority to NLAANVRAGE7905478,A priority patent/NL180063C/en
Publication of JPS5513549A publication Critical patent/JPS5513549A/en
Publication of JPS6013624B2 publication Critical patent/JPS6013624B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0334—Processing of samples having at least three levels, e.g. soft decisions
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
    • H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
    • H04L7/0331—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)

Abstract

PURPOSE:To make it possible to detect a zero-cross point in a high speed by outputting sampling pulses obtained by dividing a reference frequency when it is decided that the phase of output signals is at the zero-cross point of timing signal components or near it. CONSTITUTION:Frequency divider circuits 5, 6, and 8 divide a reference frequency to generate sampling pulses, and sampling circuit 9 samples timing signal components by these sampling pulses and supplies output signals to zero-cross point detector circuit 10. In this case, when it is decided by circuit 10 that the phase of output signals is a sampling phase other than the phase at the zero-cross point of timing signal components or near it, circuits 5, 6, and 8 insert or remove pulses on the way of frequency division and change the phase of sampling pulses; and when it is decided that the phase of output signals is the sampling phase at the zero-cross point or near it, circuits 5, 6, and 8 output sampling pulses obtained by dividing the reference frequency, so that the zero-cross can be detected in a high speed.
JP53085842A 1978-07-14 1978-07-14 Timing phase synchronization method Expired JPS6013624B2 (en)

Priority Applications (10)

Application Number Priority Date Filing Date Title
JP53085842A JPS6013624B2 (en) 1978-07-14 1978-07-14 Timing phase synchronization method
SE7905913A SE440015B (en) 1978-07-14 1979-07-06 Time phase recovery circuit for receivers in a carrier wave modulated data communication system
GB7923953A GB2026796B (en) 1978-07-14 1979-07-10 Clock synchronization circuit
CA331,561A CA1108246A (en) 1978-07-14 1979-07-11 Timing-phase recovery circuit
US06/056,641 US4312075A (en) 1978-07-14 1979-07-11 Timing-phase recovery circuit
ES482447A ES482447A1 (en) 1978-07-14 1979-07-12 Timing-phase recovery circuit
AU48890/79A AU525576B2 (en) 1978-07-14 1979-07-12 Timing-phase recovery circuit
FR7918289A FR2431228B1 (en) 1978-07-14 1979-07-13 CLOCK PHASE RECOVERY CIRCUIT
DE19792928446 DE2928446A1 (en) 1978-07-14 1979-07-13 TIMING PHASE RECOVERY CIRCUIT
NLAANVRAGE7905478,A NL180063C (en) 1978-07-14 1979-07-13 SYNCHRONIZATION CIRCUIT.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP53085842A JPS6013624B2 (en) 1978-07-14 1978-07-14 Timing phase synchronization method

Publications (2)

Publication Number Publication Date
JPS5513549A true JPS5513549A (en) 1980-01-30
JPS6013624B2 JPS6013624B2 (en) 1985-04-08

Family

ID=13870110

Family Applications (1)

Application Number Title Priority Date Filing Date
JP53085842A Expired JPS6013624B2 (en) 1978-07-14 1978-07-14 Timing phase synchronization method

Country Status (1)

Country Link
JP (1) JPS6013624B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346080A (en) * 1976-10-08 1978-04-25 Nippon Steel Corp Method and apparatus for automatic harddenability test

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012270A (en) * 1973-06-05 1975-02-07

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5012270A (en) * 1973-06-05 1975-02-07

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5346080A (en) * 1976-10-08 1978-04-25 Nippon Steel Corp Method and apparatus for automatic harddenability test

Also Published As

Publication number Publication date
JPS6013624B2 (en) 1985-04-08

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