JPS6013624B2 - Timing phase synchronization method - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a timing phase synchronization method for extracting a timing signal component from a received modulated signal and achieving timing phase synchronization by digital processing in a data modem or the like.

In order to receive modulated signals such as polyphase PSK modulation or quadrature amplitude modulation and reproduce data, it is necessary to achieve timing and phase synchronization.

The follower extracts analog timing signal components from the received modulated signal, for example as shown in FIG.
、．・・・．・・・． It was common to achieve timing phase synchronization by detecting back cross points as shown in .... With recent advances in digital processing circuits, methods have been proposed in which timing and phase synchronization is achieved through digital processing.

In that case, the received modulated signal is sampled and digitized, and the timing signal component is extracted using a digital filter or the like. When this timing signal component is converted into an analog form and shown, it becomes the dotted line waveform in Figure 2. If the average frequency of this timing signal component is ft, sampling is performed at a sampling frequency of $ of fs by Nh (N22), and the timing when the sampling output is zero to zero cross points a, b, c, d. …
.... However, when sampling is performed at the timing shown by the solid line arrow in Figure 2, since lfs - Nftl <<1, the sampling phase gradually shifts as shown by the dotted line arrow, for example, and the sampling point is reversed. It will take a considerable amount of time to shift to the cross point or its vicinity.

In other words, the timing is determined by detecting the supporting cross point. It will take a long time to achieve phase synchronization. The present invention has been made to improve the above-mentioned drawbacks, and an object of the present invention is to perform timing phase synchronization pull-in at high speed.

Examples will be described in detail below. FIG. 3 is a block diagram of an embodiment of the present invention, in which 1 is a conversion circuit that converts a received modulated signal into a digital signal, 2 is a timing signal component extraction circuit, and 3 is a circuit that detects a cross point and extracts a timing signal. The generating timing synchronization circuit 4 is a digital processing circuit that demodulates data using a timing signal.

In the timing synchronization circuit 4, when the sampling point is largely deviated from the zero cross point, the timing phase synchronization pull-in at the time of synchronization pull-in is made more distant by greatly changing the sampling frequency $.
FIG. 4 is a block diagram of the main parts of the timing signal component extraction circuit 2 and the timing synchronization circuit 3, in which the reference frequency is divided into 1/N and 1/M by frequency dividing circuits 5 and 6, respectively. , , etc.

In that case, M=kN, where k2 is selected. The pulse control circuit 7 outputs the pulse with the frequency f, as it is, or the pulse with the frequency f,
1 (or f, 10 f2) is added to the frequency divider circuit 8 and divided by 1/L to obtain the sampling frequency $ at the time of synchronization pull-in. The timing signal component of the frequency day is applied to the sampling circuit 9, sampled at the frequency $, and applied to the timing signal component extraction circuit 10. The timing signal component extracting circuit 10 is composed of, for example, a narrow band digital filter circuit. Furthermore, if the input signal to the sampling circuit 9 is a pure timing signal, the timing signal component extraction circuit 10 can be omitted. As explained with reference to FIG. 2, the zero cross point detection circuit 11 determines that the sample value is zero or a value close to zero when synchronization pull-in is performed, and the sample time at this time is determined to be the zero cross point. , and applies the zero cross point detection signal to the pulse control circuit 7.

The pulse control circuit 7 outputs f, - when the koto cross point detection signal is not input, that is, when synchronization is not performed.
A pulse with a frequency of f2=f3 or f, and f2=f3 is applied to the frequency divider circuit 8, and when the cross point detection signal is input, that is, when synchronization is engaged, f2 is set as a steady state.
, = are applied to the frequency dividing circuit 8. That is, the sampling phase when synchronous pull-in is not performed is greatly changed by removing or inserting a pulse during frequency division, and then the same number of pull-in is performed. Thereby, timing phase synchronization pull-in can be performed at high speed. Further, the zero cross points a and b have a phase difference of 1800 degrees, for example, and there are cases where it is desired to achieve phase synchronization with only one of the zero cross points.

For example, Mino cross points b, d. When synchronizing the phase at the zero cross point when reversing from positive polarity to negative polarity, as in ・・・・・・・・・, remember the sacrifice of the sample value one or several sample points before. When the sample value has a nascent slope such that the sacrifice of the sample value is reversed from positive to negative, and the sample value is a fog or a value close to zero, it is determined to be an Akira cross point. Also, the absolute values of the sample values before and after the zero cross points, for example b, d, . . . , are compared, and if the previous sample value is large, the pulse control circuit 7 is Insertion of pulses, that is, L + f2 =
If a pulse with a frequency of f3 is output, and the subsequent sample value is large, the pulse is removed, that is, a pulse with a frequency of f, -2 = f3 is output, and the drop crossing point detection method can be performed even faster. Synchronous pull-in is possible. Here, an example of a circuit for comparing the absolute values of sample values is shown in FIG.

In this figure, SIGNBIT is a sign bit, $ is a sampling signal, 25 is an inverter, and 26 and 27 are AND circuits.

That is, a timing signal represented by a two's complement code of J bits is input, and the sign bit is first latched into the latch circuit 21 as an absolute value by taking the exclusive OR of other bits at the input point. Furthermore, a second latch circuit 22 is provided to store the sample value of one sample before.
The outputs A and B of these two latch circuits are input to the amplitude comparator 23 and compared, and the result of the comparison is that the sign bit is "1" in the previous sample (that is, a negative sample) and "1" in the current sample.
0" (that is, a positive sample), that is, when the condition A>B, which indicates that the zero cross point is between the sample points on the upper right side, is satisfied, the flip-flop 24 is latched, and even if the result is "1". If it is "0", the pulse is inserted, and if it is "0", the pulse is removed. Figure 5 is a block diagram of the main part of the band crossing point detection circuit. This is for the case where the S cross point is detected by

A signal TS of J bits, for example, 9 bits, including the sign bit of the timing signal component sampled at the frequency SI by the sampling circuit is latched into the latch circuit 12,
The sign bit is applied to the D terminal of flip-flop 13 and to NAND circuit 15 and NOR circuit 18. Further, the upper three bits excluding the sign bit are applied to a NAND circuit 14 and a NOR circuit 17. Also, 16 is a NAND circuit, 19 is an inverter,
20 is an AND circuit, and the flip-flop 13 is 1
A NAND circuit 14 is configured to store a bit indicating the polarity of the sampling output before sampling, that is, a sign bit.
The NOR circuit 17 constitutes a pattern detection circuit that detects a characteristic pattern of the upper bits, for example, the upper three bits, of the current sampling output. Also, NAND circuits 15, 16,
A detection signal generation circuit that outputs a high cross point detection signal using a NOR circuit 18, an inverter 19, and a NAND circuit 20.
It consists of The flip-flop 13 stores the polarity of the previous sample, and is set when the polarity of the previous sample is negative, and the Q state output becomes "1". 3 bits are “1”
11'', the output of the NAND circuit 14 is ``0'', the output of the NOR circuit 17 is ``0'', and therefore the output of the NAND circuit 16 is ``1'', so the zero cross point of the output of the AND circuit 20 is detected. Signal ZS becomes "1".

Also, if the sample value is positive and the upper 3 bits excluding the sign bit are "000", the output of the NAND circuit 14 is "1".
, the output of the NOR circuit 17 becomes "1", and therefore the output of the NAND circuit 16 becomes "1", so the multi-cross point detection signal ZS output from the AND circuit 20 becomes "1". Then, the zero cross point detection signal false becomes "0".
'As mentioned above, the cross point detection circuit shown in FIG. 5 is capable of detecting zero cross points that change from negative polarity to positive polarity, such as the drop cross points a, c, e, etc. in FIG. In that case, detection near the zero cross point will be performed using the upper three bits excluding the sign bit, but it is sufficient for timing phase synchronization even if complete multi-cross point detection is not required.

As explained above, the present invention provides frequency dividing circuits 5, 6,
8, etc.; a sampling circuit 9; and a koto cross point detection circuit 11. If a pulse is inserted or removed using the pulse control circuit 7 or the like during frequency division, and it is determined that the sampling phase is at or near the Hiroshi cross point, the sampling pulse obtained by dividing the reference frequency signal is This is what is output.

Therefore, by performing frequency division by inserting or removing pulses during division, the sampling phase can be changed at high speed, and detection of the Hiro-cross point or its vicinity can be performed. The zero cross point detection circuit 11 also includes a memory including a flip-flop 13 for storing bits indicating the polarity of the sampling output of the previous sample, and upper bits of the current sampling output, such as the upper three bits "111",
A pattern detection circuit consisting of a NAND circuit 14 and/or circuit 17 for detecting a specific pattern such as "00", and a NAND circuit 15, 16 for outputting a spring cross point detection signal.
, a detection signal generation circuit including a NOR circuit 18, an inverter 19, a NAND circuit 20, and the like.

In the above-mentioned zero cross point detection circuit 11, since the sampling output magnetism of the previous sample is stored in the memory, the polarity of the sampling output of the previous sample and the current sample can be determined by comparing it with the sampling output polarity of the current sample. It can be determined that there is a zero cross point between .

Therefore, when phase synchronization is to be performed at a droplet cross point where the polarity reverses from negative polarity to positive polarity, it can be distinguished from the opposite drop cross point where the polarity reverses from positive polarity to negative polarity. Further, by detecting the specific/gutter of the upper bit by the pattern detection circuit, it is possible to determine that the value of the sampling output is sufficiently small and that the sampling phase is at or near the drop crossing point.

In this case, it is possible to detect a complete zero-crossing point using all bits of the sampling output, but the large number of bits makes the circuit configuration complicated. However, by adopting a configuration in which a specific pattern of high-order bits is detected as in the present invention, there is an advantage that the number of processing bits is reduced and the circuit configuration is simplified.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional analog timing signal component drop-crossing point, FIG. 2 is an explanatory diagram of zero-crossing point detection by sampling a timing signal component, and FIG. 3 is a block diagram of an embodiment of the present invention. , Fig. 4 is a block diagram of the main parts of the timing signal component extraction circuit and the timing synchronization circuit, Fig. 5 is a block diagram of the main parts of the koto cross point detection circuit, and Fig. 6 is the absolute value comparison circuit of sample values. . 1 is a sampling circuit, 2 is a timing signal component extraction circuit, 3 is a timing synchronization circuit, 4 is a digital processing circuit, 5, 6, 8 are frequency dividing circuits, 7 is a pulse control circuit, 9 is a sampling circuit, 10 is a timing signal Component extraction circuit
11 is a zero cross point detection circuit. O diagram O 2 diagram O 3 diagram O 4 diagram X 5 diagram 6 diagram

Claims (1)

[Claims] 1. Frequency division means that divides the reference frequency to generate sampling pulses, a sampling circuit that samples timing signal components using the sampling pulses from the frequency division means, and zero-cross point detection that inputs the sampling output of the sampling circuit. When the zero-crossing point detection circuit determines that the sampling phase is not at or near the zero-crossing point of the timing signal component, the frequency dividing means inserts or removes a pulse during frequency division. When it is determined that the sampling phase is at or near the zero crossing point, the frequency dividing means uses a timing phase synchronization method to output a sampling pulse obtained by dividing the reference frequency. The zero cross point detection circuit is configured to include a memory that stores bits indicating the polarity of the sampling output of the previous sample, a pattern detection circuit that detects a specific pattern of the upper bits of the current sampling output, and a memory that stores bits indicating the polarity of the sampling output of the current sampling output. 1. A timing phase synchronization system comprising: a detection signal generation circuit which outputs a zero cross point detection signal when a detection signal is output from the pattern detection circuit;