JPS55130249A - Code synchronous system for reception of spectrum diffusion signal - Google Patents

Code synchronous system for reception of spectrum diffusion signal

Info

Publication number
JPS55130249A
JPS55130249A JP3684179A JP3684179A JPS55130249A JP S55130249 A JPS55130249 A JP S55130249A JP 3684179 A JP3684179 A JP 3684179A JP 3684179 A JP3684179 A JP 3684179A JP S55130249 A JPS55130249 A JP S55130249A
Authority
JP
Japan
Prior art keywords
output
control
counter
vco6
vco
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3684179A
Other languages
Japanese (ja)
Other versions
JPS6028170B2 (en
Inventor
Yuji Ikeda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sansui Electric Co Ltd
Original Assignee
Sansui Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sansui Electric Co Ltd filed Critical Sansui Electric Co Ltd
Priority to JP54036841A priority Critical patent/JPS6028170B2/en
Publication of JPS55130249A publication Critical patent/JPS55130249A/en
Publication of JPS6028170B2 publication Critical patent/JPS6028170B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H04L7/042—Detectors therefor, e.g. correlators, state machines

Abstract

PURPOSE:To realize the delay synchronous system which features a short lock-in time and also can maintain the steady synchronous state, by providing the integrator and the sample holding circuit in place of the loop filter. CONSTITUTION:The output of correlater units 21 and 22 are compounded at compounding circuit 3 and then supplied to voltage control oscillator (VCO) 6 through integrator 7 and sample holding circuit 8 to give the control to the oscillation frequency of the VCO. The oscillation output of VCO6 is applied to local code generator 11 to give the control to the code signal phase of the output. On the other hand, sampling pulse generator 9 consists of variable divider 91 which divides the output of VCO6, division ratio setting counter 92 of divider 91, and pulse generator 93 which gives the count pulse to counter 92 each. And counter 92 receives the control for the start, stop and reset of its counting action via the start/stop/reset signal given from outside.
JP54036841A 1979-03-30 1979-03-30 Code synchronization method for reception of spread spectrum signals Expired JPS6028170B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54036841A JPS6028170B2 (en) 1979-03-30 1979-03-30 Code synchronization method for reception of spread spectrum signals

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54036841A JPS6028170B2 (en) 1979-03-30 1979-03-30 Code synchronization method for reception of spread spectrum signals

Publications (2)

Publication Number Publication Date
JPS55130249A true JPS55130249A (en) 1980-10-08
JPS6028170B2 JPS6028170B2 (en) 1985-07-03

Family

ID=12480974

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54036841A Expired JPS6028170B2 (en) 1979-03-30 1979-03-30 Code synchronization method for reception of spread spectrum signals

Country Status (1)

Country Link
JP (1) JPS6028170B2 (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141154A (en) * 1981-02-25 1982-09-01 Sony Corp Receiver on spectrum spread communication system
JPS58175332A (en) * 1982-03-10 1983-10-14 ソーン　イーエムアイ　パテンツ　リミテッド Channel communication system
JPS63262932A (en) * 1987-04-20 1988-10-31 Sony Corp Delay lock loop circuit
JPH0423534A (en) * 1990-05-17 1992-01-27 Sekiyu Kodan Transmission system for mwd
JP2010160077A (en) * 2009-01-08 2010-07-22 Building Research Institute Portable pull-out tester

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57141154A (en) * 1981-02-25 1982-09-01 Sony Corp Receiver on spectrum spread communication system
JPH0239139B2 (en) * 1981-02-25 1990-09-04 Sony Corp
JPS58175332A (en) * 1982-03-10 1983-10-14 ソーン　イーエムアイ　パテンツ　リミテッド Channel communication system
JPH0374542B2 (en) * 1982-03-10 1991-11-27
JPS63262932A (en) * 1987-04-20 1988-10-31 Sony Corp Delay lock loop circuit
JPH0423534A (en) * 1990-05-17 1992-01-27 Sekiyu Kodan Transmission system for mwd
JP2010160077A (en) * 2009-01-08 2010-07-22 Building Research Institute Portable pull-out tester

Also Published As

Publication number Publication date
JPS6028170B2 (en) 1985-07-03

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