JPS5676640A - Receiver of frequency synthesizer system - Google Patents

Receiver of frequency synthesizer system

Info

Publication number
JPS5676640A
JPS5676640A JP15392179A JP15392179A JPS5676640A JP S5676640 A JPS5676640 A JP S5676640A JP 15392179 A JP15392179 A JP 15392179A JP 15392179 A JP15392179 A JP 15392179A JP S5676640 A JPS5676640 A JP S5676640A
Authority
JP
Japan
Prior art keywords
frequency
circuit
oscillation
output
local oscillation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15392179A
Other languages
Japanese (ja)
Inventor
Takeshi Sakai
Tsutomu Ogishi
Toru Akiyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP15392179A priority Critical patent/JPS5676640A/en
Publication of JPS5676640A publication Critical patent/JPS5676640A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/16—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop
    • H03L7/18—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop
    • H03L7/183—Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop using a frequency divider or counter in the loop a time difference being used for locking the loop, the counter counting between fixed numbers or the frequency divider dividing by a fixed number
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L2207/00—Indexing scheme relating to automatic control of frequency or phase and to synchronisation
    • H03L2207/10—Indirect frequency synthesis using a frequency multiplier in the phase-locked loop or in the reference signal path

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Superheterodyne Receivers (AREA)
  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

PURPOSE:To reduce the lock-up time PLL, by obtaining the local oscillation frequency of broad range through the use of VCO stable and narrow in the oscillation frequency range, through the use of the oscillation output of a voltage controlled oscillator (VCO) as a local oscillation frequency through multiplication. CONSTITUTION:The oscillation output of a stable reference oscillation circuit 10 is frequency-divided at a frequency dividing circuit 11 and is input to a phase comparison circuit 12 as the reference signal. On the other hand, the oscillation output of a VCO13 is multiplied by M at a multiplier 16 and used as the local oscillation frequency and frequency-divided at a programmable frequency dividing circuit 14 in which the frequency dividing ratio N is varied with the desired local oscillation frequency, as another input of the phase comparison circuit 12. The output of the circuit 12 is fed back to the VCO13 via a low pass filter 15.
JP15392179A 1979-11-27 1979-11-27 Receiver of frequency synthesizer system Pending JPS5676640A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15392179A JPS5676640A (en) 1979-11-27 1979-11-27 Receiver of frequency synthesizer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15392179A JPS5676640A (en) 1979-11-27 1979-11-27 Receiver of frequency synthesizer system

Publications (1)

Publication Number Publication Date
JPS5676640A true JPS5676640A (en) 1981-06-24

Family

ID=15572997

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15392179A Pending JPS5676640A (en) 1979-11-27 1979-11-27 Receiver of frequency synthesizer system

Country Status (1)

Country Link
JP (1) JPS5676640A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021930U (en) * 1988-06-17 1990-01-09
WO1994022224A1 (en) * 1993-03-18 1994-09-29 Kabushiki Kaisha Toshiba Frequency synthesizer

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH021930U (en) * 1988-06-17 1990-01-09
WO1994022224A1 (en) * 1993-03-18 1994-09-29 Kabushiki Kaisha Toshiba Frequency synthesizer
US5568098A (en) * 1993-03-18 1996-10-22 Toshiba Corporation Frequency synthesizer for use in radio transmitter and receiver
CN1047898C (en) * 1993-03-18 1999-12-29 东芝株式会社 Frequency synthesizer

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