JPS54121610A - Pll circuit of radio receiver - Google Patents
Pll circuit of radio receiverInfo
- Publication number
- JPS54121610A JPS54121610A JP2869378A JP2869378A JPS54121610A JP S54121610 A JPS54121610 A JP S54121610A JP 2869378 A JP2869378 A JP 2869378A JP 2869378 A JP2869378 A JP 2869378A JP S54121610 A JPS54121610 A JP S54121610A
- Authority
- JP
- Japan
- Prior art keywords
- divider
- frequency
- pll circuit
- circuit
- division ratio
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/06—Receivers
- H04B1/16—Circuits
- H04B1/26—Circuits for superheterodyne receivers
Abstract
PURPOSE:To secure the optimum and accurate reception regardless of dispersion of the central frequency of the intermediate frequency filter for the PLL circuit of the digital synthesizer receiver by varying the division ratio of the divider which divides the crystal oscillation frequency. CONSTITUTION:Prescaler 6 to divide the oscillation frequency of local oscillator circuit 5 is provided along with programable divider 7, and the output of divider 7 is supplied to phase comparator 8. At the same time, the oscillation frequency of crystal oscillator 9 is divided via divider 11 and then supplied to comparator 8. Switch circuit 15 which can vary part of whole of the division ratio is provided to divider 11, and the output of comparator 8 is fed back to oscillator 5 via LPF12. Thus, a PLL circuit is formed. The solid state filter or the like is used for intermediate frequency filter 2 with no incapability to vary the central frequency, and part or whole of the division ratio of divider 11 is varied through circuit 15. and thus, the frequency of the PLL circuit is varied in accordance with the frequency of divider 11.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2869378A JPS54121610A (en) | 1978-03-15 | 1978-03-15 | Pll circuit of radio receiver |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2869378A JPS54121610A (en) | 1978-03-15 | 1978-03-15 | Pll circuit of radio receiver |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS54121610A true JPS54121610A (en) | 1979-09-20 |
Family
ID=12255551
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2869378A Pending JPS54121610A (en) | 1978-03-15 | 1978-03-15 | Pll circuit of radio receiver |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS54121610A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6221318A (en) * | 1985-07-22 | 1987-01-29 | Victor Co Of Japan Ltd | Channel selection device |
JPH03206731A (en) * | 1990-01-08 | 1991-09-10 | Matsushita Electric Ind Co Ltd | Clock generator for pwm system digital analog converter |
-
1978
- 1978-03-15 JP JP2869378A patent/JPS54121610A/en active Pending
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6221318A (en) * | 1985-07-22 | 1987-01-29 | Victor Co Of Japan Ltd | Channel selection device |
JPH0315367B2 (en) * | 1985-07-22 | 1991-02-28 | Victor Company Of Japan | |
JPH03206731A (en) * | 1990-01-08 | 1991-09-10 | Matsushita Electric Ind Co Ltd | Clock generator for pwm system digital analog converter |
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