JPS63262932A - Delay lock loop circuit - Google Patents

Abstract

PURPOSE:To surely realize phase lock, by constituting a loop filter in a full integration type filter, and limiting the integration range of the loop filter. CONSTITUTION:A code generator 1 which generates the same code as that of a reception signal is provided, and codes outputted from the reception signal and the code generator 1 are phase-compared at phase comparators 3 and 4, and a compared output is supplied to a voltage controlled oscillator 2 via the loop filter 7, then, the output phase of the code generator 1 can be controlled by the output of the voltage controlled oscillator 2. At this time, the loop filter of full integration type and whose integration range is limited is used as the loop filter 7. By limiting the integration range of the loop filter 7, it is possible to dissipate the stationary phase error of the loop filter 7, and to surely perform the phase lock.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a delay lock loop circuit used for receiving spread spectrum signals.

[Summary of the invention]

This invention enables reliable locking in a delay lock loop circuit used to receive spread spectrum signals by limiting the integral range of the loop filter that constitutes the delay lock loop circuit. be.

[Conventional technology]

For example, in a satellite positioning and communication service system that uses artificial satellites to position moving objects such as vehicles, aircraft, and ships, and also performs message communication, a spread spectrum method is used as the transmission method. In the spread spectrum method, when transmitting data, a PN code is superimposed on the data to spread the spectrum.

The spread spectrum method is resistant to interference and has high confidentiality because it requires a PN sequence similar to the signal sent during reception.

In this way, a DLL (delay lock loop) circuit is used to demodulate the spread spectrum signal. The DLL circuit is provided with a PN code generator that generates a PN code that is the same as the PN code of the received signal, and performs a phase comparison between the code from the P and N code generator and the code of the received signal, and uses the comparison output as The phase of the code generated from the PN code generator is controlled. Regarding such a LL circuit, for example,
It is described in Publication No. 8170.

That is, FIG. 5 shows an example of a conventional DLL circuit. In FIG. 5, 51 is a PN code generator.

The PN code generator 51 is composed of, for example, a shift register and a feedback circuit. The PN code generator 51 generates the same PN sequence code as the received signal. The output of a VCO (voltage controlled oscillator) 52 is supplied to the PN code generator 51, and the phase of the code output from the PN code generator 51 is controlled by the output of the VCO 52. The PN code generator 51 generates a PN code S of the same PN sequence as the received signal.
e (FIG. 5A) and a PN code SR<FIG. 5B) delayed by one chip phase from this PN code Se are output. This PN code Ss and the delayed PN code Sl are supplied to phase comparators 53 and 54, respectively.

The phase comparators 53 and 54 are supplied with the received signal from an input terminal 55.
and the code Se from the PN code generator 51, and the phase comparator 54 compares the code Sl of the received signal and the delayed I)N code Sj! from the PN code generator 51. A phase comparison is made with

The comparison output from the phase comparator 53 and the comparison output from the phase comparator 54 are supplied to a combining circuit 56.

The output of the synthesis circuit 56 is passed through the loop filter 57 to the VC
The oscillation of the VCO 52 is controlled by the output from the loop filter 57.

The phase comparators 53 and 54 are multipliers, and when the phases of the codes Se and SR from the PN code generators 53 and 54 match the phase of the received signal Sl, the correlation between the codes increases, and the comparison output becomes As described above, the code Sl supplied to the phase comparator 54 lags the code Se supplied to the phase comparator 53 by one chip.

Therefore, as shown in FIGS. 7A and 7B, the peak value of the comparison output of the phase comparator 54 lags behind the peak value of the comparison output of the phase comparator 53 by 2π.

In FIG. 7, the horizontal axis represents the phase difference, and the vertical axis represents the comparative output voltage. That is, the output of the phase comparator 53 reaches its maximum at a point where the phase of the received signal is advanced by π with respect to the phase at the locked point. On the other hand, the output of the phase comparator 54 reaches its maximum at a point delayed by π with respect to the phase at the point where the phase of the received signal is locked.

The outputs of phase comparators 53 and 54 are combined in a combining circuit 56. At this time, the output of the phase comparator 54 is inverted and combined. As a result, from the combining circuit 56,
An output with the characteristic of a figure-eight curve as shown in the figure is obtained. The output of the synthesis circuit 56 controls the oscillation of the VCO 52 and locks the DLL. That is, the synthesis circuit 56
When the output of PN code generator 51 becomes a positive level, the phase of the received signal is leading (PN
(the phase of the code is delayed with respect to the lock point), so P
When the output of the 0 synthesis circuit 56, which advances the phase of the PN code output from the N code generator 51, becomes a negative level, the phase of the received signal is delayed (PN code generator 5
1), the phase of the PN code output from the PN code generator 51 is ahead of the lock point).
The phase of the N code is delayed.

By performing such control, the phase difference φ becomes (-3π
≦ψ≦3π), it is theoretically possible to perform phase locking.

[Problem that the invention seeks to solve]

However, in the conventional DLL circuit, there is a problem in that even though the phase difference ψ cannot be locked in principle and is within the range of -3π≦ψ≦3π, the phase may not be locked. This is explained as follows.

In the conventional DLL circuit, a completely integral type filter is used as the loop filter 57. This is because, in a completely integral type filter, the stationary phase error is theoretically zero. On the other hand, in a lag lead filter, the steady phase error does not become zero. As shown in FIG. 8, the complete integral type filter includes an operational amplifier 11 and a resistor 62.
63 and a capacitor 64.

A completely integral type filter has infinite DC gain.

Therefore, if a completely integral type filter is used as the loop filter 57, the phase comparator 5
A DC voltage slightly outputted from 3.54 through the synthesis circuit 56 is integrated by the loop filter 57. Therefore, in the initial state, the output of the loop filter 57 reaches Vlim above the positive level or negative level limit voltage determined by the circuit.

For example, as shown in FIG. 9, the limiting voltage JVlil 1
It is assumed that the peak value IVmaxl of the combining circuit 56 is larger than the peak value IVmaxl. As described above, in the initial state, the output voltage vf of the loop filter 57 reaches Vljm above the positive level or negative level limit voltage. As shown in FIG. 9A, the output voltage v of the loop filter 57 in the initial state is
For example, assume that the -Vth point m has been reached. It is also assumed that the phase difference ψ when the synchronization process is started is π.

In this case, if the output voltage of the loop filter 57 is zero in the initial state, the phase difference ψ is π, so the output voltage ■ of the loop filter 57 becomes Vmax, and VC
A voltage of +Vmax is supplied to O52. VCO5
Since the voltage supplied to the PN code generator 51 is at a positive level, the phase of the PN code output from the PN code generator 51 is advanced, and eventually phase lock is achieved.

However, the output voltage V of the loop filter 57 in the initial state is -V lim as described above.

Therefore, the output voltage Vf when the phase difference is ψ is the seventh
As shown in Figure B, (-Vlim + Vmax). Here, if l Vain l > l Vmax l, the output voltage Vl becomes a negative level, as shown in FIG. 7B. If the voltage supplied to the VCO 52 is at a negative level,
The phase of the PN code output from the PN code generator 51 is delayed. Therefore, the phase difference ψ increases, and phase lock becomes impossible.

Therefore, the purpose of this invention is to use the loop filter as a loop filter.
It is an object of the present invention to provide a DLL circuit that can use a DLL circuit in which the steady phase error is zero and can reliably perform phase locking.

[Means for solving problems]

This invention is provided with a code generator that generates the same code as a received signal, compares the phases of the received signal and the code output from the code generator, and sends the comparison output to a voltage controlled oscillator via a loop filter. In a delay lock loop circuit in which the output phase of the code generator is controlled by the output of the voltage controlled oscillator, this loop filter is
This is a delay lock loop circuit which has a completely integral type configuration and whose vF characteristic is that the integration range of the loop filter is limited.

[Effect]

As the loop filter constituting the DLL, a completely integral type loop filter whose integral range is limited to the peak value of the phase comparator is used. In this way, by limiting the integration range of the loop filter, phase locking can be achieved reliably.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

In FIG. 1, 1 is a PN code generator.

The PN code generator 1 includes, for example, a shift register and a feedback circuit. The PN code generator 1 generates the same PN sequence code as the received signal. The output of a VCO (voltage controlled oscillator) 2 is supplied to the PN code generator 1, and the phase of the code output from the PN code generator 1 is
It is controlled by the output of 2. Outside of the PNN code generator,
A PN code of the same PN sequence as the received signal and a PN code delayed by one chip phase from this PN code are output.

This PN code and the delayed PN code are supplied to phase comparators 3 and 4, respectively.

The phase comparators 3 and 4 are supplied with the received signal from the input terminal 5.The phase comparator 3 compares the phase of the received signal with the leading PN code from the PN code generator 1, and calculates the phase. Comparator 4 compares the phase of the code of the received signal and the delayed PN code from PN code generator 1. The comparison output from phase comparator 3 and the comparison output from phase comparator 4 are sent to synthesis circuit 6. The output of the 0 synthesis circuit 6 is supplied to the VCO 2 via the loop filter 7, and the oscillation of C02 is controlled by the output from the loop filter 7.

As the loop filter 7, one having the configuration shown in FIG. 2 is used.

The outputs of the phase comparators 3 and 4 are combined by a combining circuit 6. At this time, the output of the phase comparator 4 is inverted and combined. As a result, the synthesis circuit 6 obtains an output having characteristics of a three-figure curve as shown in FIG. The output of the synthesis circuit 6 controls the oscillation of the VCO 2 and locks the DLL. That is, when the output of the combining circuit 6 becomes a positive level, the phase of the received signal is ahead (the phase of the PN code output from the PN code/sign generator 1 is delayed with respect to the lock point). Therefore, the phase of the PN code output from the PN code generator 1 is advanced. When the output of the synthesis circuit 6 becomes a negative level, the phase of the received signal is delayed (the phase of the PN code output from the PN code generator 1 is ahead of the lock point), so the PN code is The phase of the PN code output from the generator 1 is delayed.

In one embodiment of the present invention, the loop filter 7 having the configuration shown in FIG. 2 is used.

In FIG. 2, the non-inverting input terminal of the operational amplifier 11 is grounded, and the inverting input terminal of the operational amplifier 11 and the input terminal 12 are grounded.
A resistor 13 is connected between the two.

A series connection of a resistor 14 and a capacitor 15 is connected between the inverting input terminal of the operational amplifier 11 and its output terminal, as well as a series connection of Zener diodes 16 and 17. From the output terminal of operational amplifier 11 to output terminal 1
8 is derived.

The filter shown in FIG. 2 is of a completely integral type, and the stationary phase error is theoretically zero. And operational amplifier 11
Since the series connection of Zener diodes 16 and 17 is connected between the inverting input terminal of and its output terminal,
For example, the limit voltage lV1iml
is the peak value IVm of the synthesis circuit 6, as shown in FIG.
It is considered to be below A of axl. By thus limiting the integration range, phase locking is ensured.

Note that the integration range is limited by connecting Zener diodes 16 and 17 between the inverting input terminal of the operational amplifier IT and its output terminal, as shown in FIG. In addition, as shown in FIG.
This can also be achieved by limiting the power supply voltages +V and -■ supplied to the terminals 2 and 2.

A description will be given of how phase locking is ensured by limiting the integration range of the loop filter in this way.

In the initial state, a small amount of DC voltage output from the synthesis circuit 6 is integrated by the loop filter 7, and as shown in FIG. 4A, the output voltage Vf of the loop filter reaches the positive limit voltage V.
If the synchronization process is started with a zero phase difference ψ (ψ - π), which is equal to lim or the negative limit voltage -VJim, the output voltage V of the loop filter is as shown in FIG. 4B: V, =-Vlim +Vt5ax == (1), where the output voltage v of the loop filter.

If is at a positive level, the phase difference ψ will be reduced and phase lock will eventually be achieved. However, when the output voltage Vl of the loop filter reaches a negative level, the phase difference φ increases and locking becomes impossible. From this, the condition for phase locking is Vaax-Vlim≧0.
...(2) is derived. Therefore, the limit voltage IVliml of the loop filter is set to the peak value 1 of the synthesis circuit 6.
If you limit it to be smaller than Vmax l,
Phase lock can be achieved.

Here, we will consider the frequency error.

The frequency error of the PN code of the received signal is Δω, , VCo2
The frequency error of is Δω2, and the frequency error Δω is Δω−ω1 +ω2・・・・・・・・・・・・・・・・・・
...(3). This frequency error Δω is converted into the voltage ΔV of VCo2, and if the sensitivity of VCo2 is Kvco, then ΔV=Δω/Kvco・・・・・・・・・・・・・・・・・・
・(4) becomes. The conditions for locking when considering the frequency error are from equations (2) and (4): −V Iim + Vmax−Δv〉0・・・・・・・・・
・(5), and if the voltage of VCo2 when the frequency error is maximum is greater than the limit voltage Vlim, it cannot be locked, so Δv<Vlim・・・・・・・・・・・・・・・...
...(6). From equations (5) and (6),
V max ≧2ΔV・・・・・・・・・・・・・・・
・・・・・・(7) Vth 1 ≧ΔV・・・・・・・・・
.........The limit voltage Vl is set so that (8) holds true and formulas (5), (7), and (8) are satisfied.
If the phase of the phase comparator 53.4 changes by π, the output of the phase comparator 3゜4 changes by Vvsax, so if the phase of the phase comparator 53.4 changes by π, the output of the phase comparator 3゜4 changes by Vvsax. The sensitivity Kpc of No. 4 is K pc −V tsax/π・・・・・・・・・・・・
・・・・・・・・・(9) Therefore, the loop gain is Kvco −Kpc・・・・・・・・・
・・・・・・・・・・・・(10) From equation (4),
(K vco−Δω/Δ■), from equation (9), (Kpc
= Vtaax/π), (7) From 2 (V w
ax ≧2ΔV), so Δω〈π/2...
(11) Therefore, the relationship between the loop gain and the lock-in range W is /2 for ω and -π.・・・・・・・・・・・・・・・
(12) By limiting the limit voltage 1VIia+I of the loop filter and limiting the integration range, phase locking can be ensured.

〔Effect of the invention〕

According to the present invention, a completely integral type loop filter having a limited integral range is used as the loop filter constituting the DLL. By thus limiting the integration range of the loop filter, it is possible to make the steady phase error of the loop filter zero and ensure phase lock.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of an embodiment of this invention, Fig. 2 is a connection diagram of an example of a loop filter in an embodiment of this invention, and Fig. 3 is another example of a loop filter in an embodiment of this invention. FIG. 4 is a characteristic diagram used to explain an embodiment of the present invention, FIG. 5 is a block diagram of a conventional DLL circuit, FIG. 6 is a waveform diagram used to explain the DLL circuit, and FIG.
8 is a characteristic diagram used to explain the operation of the DLL, FIG. 8 is a connection diagram of an example of a loop filter in a conventional DLL, and FIG. 9 is a characteristic diagram used to explain problems in the conventional DLL. Explanation of main symbols in the drawings 1: PN code generator, 2: VCo, 3.4: Phase comparator, 5: Input terminal, 7: Loop filter,
11: Operational amplifier, 16.17: Zener diode representative Patent attorney Tadashi Sugiura Figure 1 Loop Method 9 Part 1 Figure 2 Loop 1 Lua's IIe I Published by Hina e Month 1] Figure 4 A Mosquito Moe's Fig. 4B Example of bruise spring Fig. 5 Fig. 6 Fig. 8 Mosquito d4 [F] Fig. 7 A Fig. 7 B t Aimei n Fig. 7 C

Claims (1)

[Claims] A code generator that generates the same code as the received signal is provided, the received code and the code output from the received code generator are phase-compared, and the comparison output is passed through a loop filter. In a delay lock loop circuit that supplies a signal to a voltage controlled oscillator and controls the output phase of the code generator using the output of the voltage controlled oscillator, the loop filter has a completely integral configuration, and the loop filter A delay lock loop circuit characterized in that the integral range of is limited.