JPS5542443A - Clock supervisory system - Google Patents
Clock supervisory systemInfo
- Publication number
- JPS5542443A JPS5542443A JP11576078A JP11576078A JPS5542443A JP S5542443 A JPS5542443 A JP S5542443A JP 11576078 A JP11576078 A JP 11576078A JP 11576078 A JP11576078 A JP 11576078A JP S5542443 A JPS5542443 A JP S5542443A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- circuit
- output
- oscillator
- phase
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04M—TELEPHONIC COMMUNICATION
- H04M3/00—Automatic or semi-automatic exchanges
- H04M3/22—Arrangements for supervision, monitoring or testing
- H04M3/24—Arrangements for supervision, monitoring or testing with provision for checking the normal operation
- H04M3/244—Arrangements for supervision, monitoring or testing with provision for checking the normal operation for multiplex systems
Landscapes
- Engineering & Computer Science (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Monitoring And Testing Of Exchanges (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Use Of Switch Circuits For Exchanges And Methods Of Control Of Multiplex Exchanges (AREA)
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To facilitate an easy cut-off of the fault and thus to realize an earlier detection of the clock-system fault by separating the input clock break detection circuit from the output clock phase step-out detection circuit of the phase lock oscillator, thus enhancing the reliability for supply and distribution of the clock. CONSTITUTION:Phase lock oscillator PLO3 is constituted with phase detector 31, LPF3(LPF32, oscillator 33 and local divider 34 each. Then the output clock frequency of oscillator 3 is divided through divider circuit 4 to deliver clock frequencies 4fN, 2fN and fN each to the output terminal. The step-out detection is given to oscillator 3 via output clock supervisory circuit 11 which supplies the output of detector 31, and the beat signal is generated in case the phase step-out is detected. At the same time, the phase step-out detection is given to the input clock via output clock supervisory circuit 11 which uses the output of lock route switch circuit 1 and circuit 4 as the input. Then the output of circuit 11 is applied to circuit 1 via clock route switch control circuit 2 to facilitate the switching of the clock route.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53115760A JPS59179B2 (en) | 1978-09-22 | 1978-09-22 | Clock monitoring method |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53115760A JPS59179B2 (en) | 1978-09-22 | 1978-09-22 | Clock monitoring method |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5542443A true JPS5542443A (en) | 1980-03-25 |
JPS59179B2 JPS59179B2 (en) | 1984-01-05 |
Family
ID=14670360
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP53115760A Expired JPS59179B2 (en) | 1978-09-22 | 1978-09-22 | Clock monitoring method |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS59179B2 (en) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57194685A (en) * | 1981-05-26 | 1982-11-30 | Shinko Electric Co Ltd | Disturbance detecting system for printed image of video hard copy printer |
JPS59114925A (en) * | 1982-12-20 | 1984-07-03 | Nec Corp | Detecting circuit of input and output fault |
JPS63217409A (en) * | 1987-03-06 | 1988-09-09 | Ando Electric Co Ltd | Detecting circuit for abnormality of received clock |
US6163224A (en) * | 1998-08-24 | 2000-12-19 | Nec Corporation | PLL circuit and method of controlling the same |
CN113556201A (en) * | 2021-08-03 | 2021-10-26 | 中国科学院国家授时中心 | Multi-reference clock switching device and method based on beat digital frequency measurement |
-
1978
- 1978-09-22 JP JP53115760A patent/JPS59179B2/en not_active Expired
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS57194685A (en) * | 1981-05-26 | 1982-11-30 | Shinko Electric Co Ltd | Disturbance detecting system for printed image of video hard copy printer |
JPS59114925A (en) * | 1982-12-20 | 1984-07-03 | Nec Corp | Detecting circuit of input and output fault |
JPH0318773B2 (en) * | 1982-12-20 | 1991-03-13 | Nippon Denki Kk | |
JPS63217409A (en) * | 1987-03-06 | 1988-09-09 | Ando Electric Co Ltd | Detecting circuit for abnormality of received clock |
US6163224A (en) * | 1998-08-24 | 2000-12-19 | Nec Corporation | PLL circuit and method of controlling the same |
CN113556201A (en) * | 2021-08-03 | 2021-10-26 | 中国科学院国家授时中心 | Multi-reference clock switching device and method based on beat digital frequency measurement |
Also Published As
Publication number | Publication date |
---|---|
JPS59179B2 (en) | 1984-01-05 |
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