JPS59114925A - Detecting circuit of input and output fault - Google Patents

Abstract

PURPOSE:To constitute the titled circuit by logic elements and to miniaturize the circuit by providing a differentiating circuit which differentiates the changing point of the input signal of a phase locked oscillation circuit to obtain the 1st output and then differentiates the output signal of said oscillation circuit to obtain the 2nd output, respectively, and detecting the coincidence and discordance between the 1st and 2nd outputs. CONSTITUTION:A phase locked oscillation circuit PLO1 is provided with a phase comparator 2, loop filter 3 and a voltage controlled oscillator 4. An input signal IN is applied to the comparator 2 and to a differentiating circuit 16. The changing point of the signal IN is differentiated by a delay circuit 21 and an AND circuit 22 to deliver the 1st signal (e). While the changing point of the output signal of the osillator 4 is differentiated by a delay circuit 23 and an AND circuit 24 of the circuit 16 to deliver the 2nd signal (f). The coincidence and dissidence between the signals (e) and (f) are detected by an asynchronism detecting circuit 5. Then an asynchronism detecting output (b) is outputted when no coincidence is detected between both signals, and only logic elements are used to constitute a circuit for miniaturization.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of the Invention] The present invention relates to an input/output failure detection circuit for a phase-locked oscillator. In particular, the present invention relates to an improvement in a phase synchronized oscillator suitable as a circuit for generating each frequency required by a time division switching device in synchronization with a clock signal of a main clock supply device.

[Description of prior art]

Conventionally, a phase-locked oscillator circuit (hereinafter referred to as rPLOJ) is used.

) The input/output fault detection circuit uses resistive elements and It uses a capacitive element.

FIG. 1 shows a conventional input/output failure detection circuit.

In FIG. 1, 1 is a PLO, which is composed of a phase comparator 2, a loop filter 3, and a voltage controlled oscillator 4. P
When the input and output of the LOI are in an asynchronous state, a beat signal appears at the output of the phase comparator 2, but this beat signal is rectified by the rectifier circuit 6 in the asynchronous detection circuit 5 and converted to DC, which is then passed to the comparator. 7, an asynchronous failure is detected and output to the asynchronous detection output.

In addition, the output disconnection detection circuit 9 uses a monostable multi-high break 10 that can be retriggered, and includes a resistive element 11 and a capacitive element 1.
2 is set to be larger than the repetition period of the PLOI output a. As a result, when a disconnection failure occurs in the output a of the PLOI, the detection result is sent to the output disconnection detection output C after approximately a set time has elapsed.

The input disconnection detection circuit 13 can also have the same configuration as the output disconnection detection circuit 9, and its operating principle is the same as that of the output disconnection detection circuit 9.

In this way, conventional input/output fault detection circuits use resistive elements, capacitive elements, etc., and their detection characteristics vary over a wide range over time.
This was a hindrance to economicization.

[Purpose of the invention]

The present invention improves on this point, and aims to provide an input/output failure detection circuit that does not cause characteristic fluctuations and is suitable for semiconductor integrated circuits.

[Key points of the invention]

The present invention includes a differentiation circuit that differentiates a signal change point of an input of a phase-locked oscillator circuit to produce a first output, and differentiates a signal change point of an output of the phase-locked oscillator circuit to produce a second output, The first feature is that it includes an asynchronous detection circuit that detects coincidence or mismatch between the first output and the second output.

The second point of the present invention is that the first output is connected to the divided signal input of a frequency divider that has a frequency division ratio of 2 or more and is resettable, and the second output is connected to the reset signal input. It is characterized by being equipped with an output cutoff detection circuit.

The third point of the present invention is that the first output is connected to the cent signal input of a frequency divider that has a frequency division ratio of 2 or more and is resettable, and the second output is connected to the divided signal input. The device is characterized by being equipped with an input disconnection detection circuit.

[Explanation based on examples]

An embodiment of the present invention will be described based on the drawings.

FIG. 2 is a block diagram of main parts of an embodiment of the present invention. Compared to the conventional example circuit shown in FIG.
It is characterized in that it is composed of an N frequency divider 18, and the input disconnection detection circuit 13 is composed of a 1/M frequency divider 19.

That is, the input signal IN is input to the delay element 21 of the differentiating circuit 16.
and one input terminal of the AND circuit 22, and the output of the delay element 21 is guided to the inverting input terminal of the AND circuit 22. In addition, the output a of PLOl is transferred to the delay element 23.
and one input terminal of the AND circuit 22 , and the output of the delay element 23 is guided to the inverting input terminal of the AND circuit 24 .

The outputs esf of the AND circuits 22 and 24 are respectively guided to the input terminals of the AND circuit 17, and the output e is 1/
The output f is led to the input terminal of the N frequency divider 18 and the reset terminal of the 1/M frequency divider 19, and the output f is led to the reset terminal of the 1/N frequency divider 1B and the input terminal of the 1/PI frequency divider 19.

The other configurations are the same as in FIG. 1, and the same reference numerals indicate the same parts.

Now, the input IN signal is input to the differentiating circuit 16, and the input I
For the operation delay time of the delay element 21 from the time when N transitions from the state of logical value "0" to the state of logical value "1", the output e of the AND circuit 22 becomes the logical value "1", and at other times it becomes the logical value "1". Outputs the value "0". Therefore, a differential operation is performed on the rising edge of the input IN transitioning from the logic value "0" to the logic value "1".

The same holds true for the relationship between the output a of the PLOI and the output f of the AND circuit 24.

Here, the operating times of the delay elements 21 and 23 may be the same or different. Therefore, the delay elements 21 and 23 can be constructed by a cascaded circuit of logic elements that actively utilizes the operation delay time of the logic elements.

The asynchronous detection circuit 5 inputs the outputs e and f of the differentiating circuit 16, and detects whether or not their differential times match or differ. That is, when the input IN of the PLOI and the output a of the PLOI are not synchronized, the differential pulses of the outputs e and f of the differentiating circuit 16 are generated at the same time as time passes. The asynchronous detection circuit 5 detects the coincidence of these times, and when there is no coincidence, outputs an asynchronous failure to the asynchronous detection output.

Here, the signal form of the asynchronous detection output is a repetitive pulse signal that depends on the frequency of the input IN of PLO1 and the frequency of the output a of PLOI. It is possible with a simple technique to convert this flip-flop into a sustained signal by resetting it.

Output interruption detection circuit 9 detects output interruption. That is, P.L.
When the OI is operating normally, the differential times of e and f are in a mismatched state, so the frequency division operation and the reset operation are repeated alternately. Therefore, if the frequency division ratio N of the 1/N frequency divider 18 is N>2, the normal operation of PLOI is 1/N.
No signal appears at the output C of the N frequency divider 18. On the other hand, P.L.
If OI output a is disconnected, 1/N frequency divider 1
Since the reset input R of 8 is not input and only the frequency division input is input, when N or more differential pulses of the output e of the differentiating circuit 16 are counted, a signal is detected at the frequency division output C □, 48
Kaaaaaah. 1. Thereby, the detection result of the disconnection failure of the output a of the PLOI can be sent to the output disconnection detection output C.

By appropriately selecting the frequency division ratio N, it becomes possible to construct an output disconnection detection circuit that also has the ability to eliminate malfunctions caused by noise or the like using only logic elements.

Here, if the output a of the PLOI becomes disconnected for a long time, the signal form of the output disconnection detection output C becomes a repetitive pulse signal, but as a means to maintain this signal continuously, 1 by the same method as the processing for the asynchronous detection result described above, or by the signal of the output disconnection detection output C.
A possible method is to provide feedback so that the frequency dividing operation of the /N frequency divider 18 is stopped and maintained.

The operation of the input disconnection detection circuit 13 is the same as that of the output disconnection detection circuit 9, and when the PLOI is operating normally, the operation is 1/1.
No output is generated at the frequency divided output d of the M frequency divider 19,
When the input IN of the PLOI is disconnected, an output is generated at the frequency division output d, and a detection result is outputted at the input disconnection detection output d.

Here, the frequency division ratio M of the 1/M frequency divider 19 must satisfy M>2, but the frequency division ratio N of the 1/N frequency divider 18 may be the same or different. The frequency division ratio is also arbitrary. Further, the means for continuously holding the input disconnection detection output d can be easily realized in the same way as the means for continuously holding the output disconnection detection output C.

Further, in the above embodiment, as an example of the operation of the differentiating circuit 16, PL
Although the operation of differentiating the rising portion of each signal of the input IN and output a of OI has been described as an example, it is also possible to perform an operation of differentiating the falling portion.

In this case,! /N frequency divider 18, 1/M frequency divider 19
By matching the operation polarity of each input so that the frequency division operation and the reset operation alternate, and by making the AND circuit 17 of the asynchronous detection circuit 5 an OR circuit or a NOR circuit, it is possible to detect coincidence and mismatch of differential times. I can do it. Also,
By leading the asynchronous detection output to an external counter and dividing the frequency of the asynchronous detection output, malfunctions due to noise can be prevented, and the configuration can be configured so that it does not respond to non-identical states that occur during the synchronization pull-in process of the PLO1. is possible.

〔Effect of the invention〕

As explained above, according to the present invention, it is possible to configure only logic elements without using resistive elements and response capacitive elements that are indispensable in conventional configuration techniques, and there is no change in characteristics over time and there is no noise. Measures to prevent malfunction due to
It can have excellent characteristics with a means for making the transient response of LOI insensitive, and it is possible to stabilize quality, miniaturize the circuit, and make it economical.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a main part of a conventional device. FIG. 2 is a diagram showing the main circuit configuration of an embodiment of the present invention. 1... PLO12... Phase comparator, 3... Loop filter, 4... Voltage controlled oscillator, 5... Asynchronous detection circuit, 6... Rectifier circuit, 7... Comparator, 9 ... Output disconnection detection circuit, 10... Monostable multi-bi break, 11... Resistance element, 12... Capacitive element, 13... Input disconnection detection circuit, 16... Differential circuit, 1
8...1/N frequency divider, 19...1/M frequency divider, 21
．． 23...1 extension circuit. %1a 2nd 1-7-12 Toranomon, Minato-ku, Tokyo ■Applicant: Fujitsu Ltd. 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi Procedural Amendment March 1981 Commissioner of the Japan Patent Office Kazuo Wakasugi 1; Display of incident 1982 Patent Application No. 224614 2, Title of invention Input/output failure detection circuit +11 name
(423) NEC Corporation (2) Name (422) Nippon Telegraph and Telephone Public Corporation (3) Name (510) Hitachi, Ltd. (4) Name (029) Oki Electric Industry Co., Ltd. (5)
) Name (522) Fujitsu Ltd. 4, Agent 5, Date of amendment order (Voluntary amendment) Mlrb-c & of “Claims” in the specification. 8. Contents of amendment (11. Claims are amended as shown in the attached sheet. (2) On page 7, line 10 of the specification, "logic element as a stage" is amended to "logic element as a stage." 3) Delete "If there is no match" from page 7, line 19 to line 20 of the same page. (4) Delete "-" from page 10, line 10 of the specification to line 11 of the same page.
・・・・・・It is possible. ” and “In this case,” add the following sentence: ``Also, the differential result as the output of the differentiating circuit 16 is converted into a logical value.''
Although the operation of outputting the differential result as a logical value rOJ has been described as an example, it is also possible to output the differential result as a logical value rOJ. ” [Attachment] [Claims] (11 The signal change point of the input of the phase-locked oscillator circuit is differentiated to obtain the first output, and the signal change point of the output of the phase-locked oscillator circuit is differentiated to obtain the second output. An input/output failure detection circuit comprising a differentiation circuit as an output, and an asynchronous detection circuit for detecting coincidence or mismatch between the first output and the second output. (2) Signal change point at the input of the phase-locked oscillator circuit and a differentiation circuit that differentiates the signal change point of the output of the phase-locked oscillator circuit to produce a second output, and a resettable frequency divider with a frequency division ratio of 2 or more. , an input/output failure detection circuit in which the first output is connected to the divided signal input of this frequency divider, and the second output is connected to the recent signal input of this frequency divider. (3) Phase synchronization A differentiation circuit that differentiates a signal change point of an input of an oscillator circuit to produce a first output, and differentiates a signal change point of an output of a phase-locked oscillator circuit to produce a second output; and a frequency division ratio of 2 or more. An input/output fault detection device comprising a resettable frequency divider, the first output being connected to the reset signal input of the frequency divider, and the second output being connected to the divided signal input of the frequency divider. circuit.

Claims (1)

[Claims] +11 A differentiation circuit that differentiates a signal change point of an input of a phase-locked oscillator circuit to obtain a first output, and differentiates a signal change point of an output of a phase-locked oscillator circuit to obtain a second output. and an asynchronous detection circuit for detecting coincidence or mismatch between the first output and the second output. (2) A differentiation circuit that differentiates the signal change point of the input of the phase-locked oscillator circuit to produce a first output, and differentiates the signal change point of the output of the phase-locked oscillator circuit to produce a second output; and a frequency division ratio. is 2 or more and is resettable, the first output is connected to the divided signal input of this frequency divider, and the second output is connected to the reset signal input of this frequency divider. input/output failure detection circuit. (3) a differentiation circuit that differentiates a signal change point of the input of the phase-locked oscillator circuit to provide a first output, and differentiates a signal change point of the output of the phase-locked oscillator circuit to provide a second output; A resettable frequency divider with a ratio of 2 or more is provided, the first output is connected to the υcent signal input of this frequency divider, and the second output is connected to the divided signal input of this frequency divider. or a connected input/output fault detection circuit.