JP3295868B2 - Frame clock synchronization circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a circuit for generating a clock signal and a frame signal in synchronization with an external clock, and more particularly to a frame clock synchronization circuit in a duplicated clock generator in an electronic exchange.

2. Description of the Related Art An electronic exchange handling voice and data signals is provided with a dual clock generator as a synchronization establishing mechanism for an external communication network when performing communication centering on its own device, and synchronizes with an external communication network. A clock signal and a frame signal are generated to perform an internal operation.

In such a duplicated clock generator, it is necessary that the two clock generators can be used interchangeably by synchronizing with each other.

[0004]

2. Description of the Related Art A clock generator in a conventional electronic exchange is duplicated in the same manner as the exchange itself in order to ensure reliability. However, no synchronization is established between the two clock generators, and the respective clock generators are not synchronized. The device output its own clock and frame signals. Therefore, the frame signals output by both clock generators are not synchronized between the systems.

[0005]

Therefore, switching between clock generators, that is, when switching from a 0-system clock generator to a 1-system clock generator, or switching from a 1-system clock generator to a 0-system clock generator. At this time, since there is a phase difference between the frame signals output from the two clock generators, a problem such as occurrence of frame synchronization loss in the line device based on the phase difference has inevitably occurred in communication centered on the own device. .

[0006] The present invention solves the conventional problems.
Output the frame clock synchronized with the external clock.
Clock generators synchronized with each other
When switching between the system and the 1 system, the frame clock
The purpose is to maintain the initial state.

[0007]

FIG. 1 shows the principle configuration of the present invention, and shows a 0-system clock generator and a 1-system clock generator. In the 0-system clock generator, 1 is a 0-system phase synchronization (PLO) circuit, 2 is a 0-system timing generation circuit (TG), 3 is a 0-system selection circuit, 4 is a 0-system duty adjustment circuit, 5 Denotes a 0-system load signal disconnection detection circuit. In the system 1 clock generator, 6 is a system 1 phase locked loop (PLO) circuit,
Reference numeral 7 denotes a system 1 timing generation circuit (TG), 8 denotes a system 1 selection circuit, 9 denotes a system 1 duty adjustment circuit, and 10 denotes a system 1 load signal disconnection detection circuit.

FIG. 2 shows an input signal of the clock generator, and shows a 64K + 8K clock (low-speed clock). Clock 64K + 8K, as shown, consists AMI code 8K cycle of 64K polarity at a period of (Hz) (t ₁₎ is inverted (Hz) (t _2), for example, has an amplitude value of ± 1V ing.

Each of the PLO circuits 1 and 6 generates a 16M clock (high-speed clock) synchronized with a 64K + 8K clock from an external communication network. The timing generation circuits 2 and 7 count 16 M clocks, respectively, so that a frame clock (MFC) having a period of 4 milliseconds, which defines the absolute time of the network (NW) and is used in a line device in the electronic exchange, Generates various timing signals such as a frame clock (1FC) having a period of 1.44 seconds, a load signal (MFCM) having a period of 4 milliseconds, and a load signal (1FCM) having a period of 1.44 seconds to be transmitted to a timing generation circuit of another system. I do.

The selection circuits 3 and 8 are provided with timing generation circuits 2 and 7 in accordance with settings from a control unit (not shown).
Is operated by the own system clock or the other system clock. Duty adjustment circuits 4 and 9 each have 16M
Is adjusted to 50%. The load signal disconnection detection circuits 5 and 10 monitor the load signals MFCM and 1FCM transmitted from the other system, and when the own system is in the standby (SBY) state, the load signal MFC from the other system.
Alarm (ALM) when disconnection of M and 1FCM is detected
Turn on the lamp.

The timing generation circuits 2 and 7 have 16M (1
6.384 MHz) by counting the clock from 0 to 65535, thereby operating at a period of 4 milliseconds.
Bit counter and 4 milliseconds from 152 to 511
It has a 9-bit counter that operates at a period of 1.44 seconds by counting 60, and the counter value can be initialized by inputting the load signals MFCM and 1FCM. , One of the timing generation circuits that output the load signals MFCM and 1FCM, and the other timing generation circuit can generate various timing signals at the same timing.

Now, in FIG. 1, the system 0 is active (ACT).
In this case, the 0-system selection circuit 3 selects its own (0-system) input. Therefore, the clock from the 0-system PLO circuit 1 is used as a clock input to the 0-system timing generation circuit 2. The signal is input through the adjustment circuit 4 and a signal of “H” which is a polarity when no load is performed is input as a load signal input.

The timing generation circuit 2 outputs a load signal MFCM which becomes "L" when the value of the 4-millisecond cycle counter is 0, and outputs a load signal MFCM having a value of 0 and 1.44 sec. "L" when the value of the cycle counter is 152
And outputs a load signal 1FC.

On the other hand, the selection circuit 8 of the 1 system is connected to the other system (0 system).
Therefore, the clock from the 0-system PLO circuit 1 is input to the 1-system timing generation circuit 7 through the duty adjustment circuit 9 as the clock input, and the 0-system timing generation circuit is input as the load signal input. The load signals MFCM and 1FC generated by the circuit 2 are input.

When the load signal MFCM is "L", the timing generation circuit 7 sets the value of the 4-millisecond period counter to 1 in consideration of the transmission delay. The value of the 44 second cycle counter is set to 152.

Therefore, the counters in the timing generation circuits of both systems always take the same value, and the timing generation circuits of both systems can output various timing signals at the same timing. As described above, the entire electronic switch having the dual configuration operates at the same timing by the clock from one PLO circuit.

At this time, when the load signals MFCM and 1FCM are not input to the timing generation circuit 7 on the SBY side (1 system), the SBY side (1 system) is not connected to the ACT side (0 system).
System) cannot operate at the same timing as
The load signal disconnection detection circuit 10 of the 1 system monitors the load signals MFCM and 1FCM of the 0 system, and when the disconnection is detected, turns on an alarm (ALM) lamp, so that the SBY side (1 system) is on the ACT side. It indicates that the operation cannot be performed at the same timing as (0 system).

In this case, the switching of the clock generator is performed by the selection circuit 3 of the 0 system selecting the other system (1 system).
The selection is performed by the selection circuit 8 of the first system selecting the own system (the first system).

That is, on the 0-system side, the selection circuit 3 is selectively changed from the own system (0-system) to the other system (1-system), and the clock input to the 0-system timing generation circuit 2 is changed to the 0-system PLO circuit 1 Is switched to the clock of the PLO circuit 6 of the first system, and the load signal input is switched from "H" fixed to the load signals MFCM and 1FCM output from the timing generation circuit 7 of the first system. Since the counter values in the circuit 2 and the 1-system timing generation circuit 7 are the same, the counter in the 0-system timing generation circuit 2 does not change the clock counting operation before and after the system switching. The counting operation can be continued as it is, and therefore, various timing signals are generated at the same timing as before the system switching.

The same applies to the 1-system side, where the selection circuit 8 is selectively changed from the other system (0-system) to the own system (1-system) and
When the clock input to the system timing generation circuit 7 is
The clock of the LO circuit 1 is switched to the clock of the PLO circuit 6 of the 1 system, and the load signal input is changed to the load signals MFCM and 1F output from the timing generation circuit 2 of the 0 system.
Although the CM is switched to “H” fixed, the counters in the 0-system timing generation circuit 2 and the 1-system timing generation circuit 7 have the same value. Before and after the system switchover, the count operation can be continued without any change in the clock counting operation. Therefore, various timing signals are generated at the same timing as before the system switchover.

[0021]

[Action]

(1) Each of the clock generators has a duplicated configuration. Each of the clock generators includes a PLO circuit for generating a high-speed clock synchronized with a low-speed clock from an external communication network, and a counter. A timing generation circuit that generates a frame clock that defines the absolute time of the network.

In this case, the timing generation circuit of the standby clock generator receives the high-speed clock and the frame clock from the active clock generator, and operates with the high-speed clock. By loading the counter in the own system timing generation circuit with the frame clock, the frame clock generated by the standby clock generation device is synchronized with the frame clock generated by the active clock generation device.

(2) In such a duplicated clock generator, a selection circuit is provided for selecting its own system input when the clock generator becomes the active system and selecting the other system input when it becomes the standby system. .

In the case of own system input, while the output of the own system PLO circuit is input as a high-speed clock,
By inputting the "H" level as a load signal of the timing generation circuit, the timing generation circuit is loaded upon completion of the counting of the counter to generate a frame clock, and when another system is input, the output of the PLO circuit of the active system is output at high speed. By inputting the clock as the clock and the frame clock of the active system as a load signal of the timing generating circuit, the timing generating circuit of the standby system generates the frame clock in synchronization with the frame clock of the active system.

Therefore, according to the present invention, since the frame clocks generated by the timing generation circuits of both systems are always synchronized, and the frame clock does not shift at the time of switching between the working system and the protection system, the connection to the network is prevented. Loss of frame synchronization of the line device is prevented.

(3) In the case of (1) or (2), when loading the counter of the timing generation circuit in the clock generating device, the initial value of this counter is set to a predetermined value other than 0, so that other systems The frame clocks generated by the two systems can be synchronized even if the load signal from the clock generator has a transmission delay.

In the case of a clock generation device serving as a standby system,
It is inevitable that the load signal transmitted from the counterpart system is accompanied by a transmission delay. However, by setting the initial value of the counter in the timing generation circuit of the clock generator to, for example, “1”, even in such a case, The frame clocks of both systems can be synchronized.

(4) In the case of (1) or (2), the output clock of the PLO circuit of the other system is used as the counter clock in the timing generation circuit of the clock generation device serving as the standby system. The load timing of the counter is adjusted using the transmission delay of the clock.

In the case of a clock generator serving as a standby system,
Since the high-speed clock for punching out the load signal transmitted from the active system is also of the active system, the output clock of the active PLO circuit is used as the high-speed clock, and the transmission delay generated in the timing generation circuit is used. Thus, a margin between the setup time and the hold time of the load signal can be secured.

(5) In the case of (1) or (2), when there are a plurality of types of frame clocks generated by the timing generation circuit, the timing generation circuit serving as the standby system uses the plurality of types of frame clocks as the timing of the working system. Counters corresponding to a plurality of types of frame clocks received from the generation circuit are respectively loaded.

This makes it possible to achieve frame synchronization between the systems in a shorter time than when, for example, only one frame clock having the maximum cycle is transmitted and the counter is loaded.

(6) In the case of (1) or (2), each clock generator is provided with a load signal disconnection detecting circuit for detecting disconnection of the load signal, and when the clock generator becomes the standby system, the active system becomes active. Of the load signal received from the clock generation device of the above is detected and an alarm is issued.

By doing so, it is possible to early detect an abnormal operation of the standby system due to the interruption of the load signal, which is difficult to notice during normal operation, and to improve the reliability of the frame clock synchronization.

(7) In the case of (2), a duty adjustment circuit is provided on the high-speed clock output side of the selection circuit, and the duty of the high-speed clock from the selection circuit is adjusted to 50% and output.

The duty of the clock transmitted to each part of the network via the timing generation circuit may be deviated from 50% due to the insertion of the selection circuit. Evils due to distortion can be eliminated.

[0036]

FIG. 3 shows an embodiment of the present invention, in which the same elements as those in FIG. 1 are indicated by the same reference numerals. FIG. 4 shows a configuration example of the timing generation circuit. In the timing generation circuits (TG) 2 and 7, 21 and 71 are 16-bit counters, respectively, and 22 and 72 are 9
Bit counters, 23, 24, 73 and 74 are D
Type flip-flop (D-FF), 25, 26,
75 and 76 are AND circuits, respectively.

FIG. 5 shows a configuration example of the duty adjustment circuit. In the duty adjustment circuits 4 and 9, reference numerals 41 and 91 denote delay elements of 0 to 20 ns, reference numerals 42 and 92 denote delay elements of 10 ns and 20 ns, respectively. 93 is an inverter, 44 and 94 are NAND circuits,
45 and 95 are D-type flip-flops (D
-FF).

FIG. 6 shows an example of the configuration of the load signal disconnection detection circuit.
101 is a clock disconnection detection circuit for the load signal MFCM, and 52 and 102 are load signals 1FC, respectively.
M, a clock loss detection circuit, 53 and 103 are OR circuits, and 54 and 104 are light emitting elements (LE
D) and the like, and the alarm lamps 55 and 105 are resistors.

FIG. 7 is a time chart showing the operation of the duty adjustment circuit, showing the input / output timing of each clock, and each signal has the same number and the corresponding position in FIG. FIG. 8 is a time chart showing the operation of the timing generation circuit, and shows the clock and the load signal MF.
The timing with the CM output is shown. Each signal has the same number and the corresponding position is shown in FIG.

When the 0 system is ACT, the 0 system selection circuit 3
Indicates that the system switching signal from the control unit (not shown) is “0”, the own system (system 0) is selected, and the clock from the PLO circuit 1 of system 0 and the load signal fixed at “H” are output. Output.

In FIG. 5, in the 0-system duty adjustment circuit 4, the D-FF 45 is set at the rise of the 16M clock input (1) from the selection circuit 3. At this time, for example, a delay of 6 ns occurs. On the other hand, clock input (1)
Is delayed by 0 to 20 ns by the delay element 41, and the delay output (2)
The reset output (5) is generated by taking the NAND of the delay output (3) obtained by delaying the delay output (2) by 10 ns by the delay element 42 and the inverted signal of the delay output (4) delayed by 20 ns. , D-FF 45 are reset.

At this time, for example, a delay of 3 ns occurs before the input of the D-FF 45, and a delay of 4 ns occurs in the D-FF 45. Therefore, a 16M clock output at the output of the D-FF 45
In (6), the high level period is 30 ns. 16M
Since one cycle of the (16.384 MHz) clock is 60 ns, a clock having a duty of 50% is obtained. The same applies to the operation of the duty adjustment circuit 9 of the first system.

In FIG. 8, in the timing generation circuit 2, a 16M clock input (1
1), a 16M clock input (12) whose duty has been adjusted to 50% in the duty adjustment circuit 4 through a selection circuit delay of 14 ns is delayed by 10 ns in the circuit,
This produces a clock output (13). Further, the timing generation circuit 2 uses the clock input (12) to generate the counters 21 and 22.
And the D-FFs 23 and 24, the load signal MFC
Generate M and 1FCM.

On the load signal MFCM side, the counter 21
After counting the 16M clock output (13) by "65536", the carry output CO is latched by the D-FF 23, and the QN output of the D-FF 23 and the "H" input enable
A load signal is given through an AND circuit 25, and a counter 2
By loading an initial value "1" into the "1", a load signal MFCM consisting of a pulse which becomes "L" in a period of 4 milliseconds
(Frame clock signal MFC) Output (14) is 10 ns
Output with a delay of.

On the load signal 1FCM side, the counter 22
As a result, the carry output CO of the counter 21 is changed to “36”.
After counting "0", the carry output CO is latched by the D-FF 24, and a load signal is given through the AND circuit 26 by the QN output of the D-FF 23 and the "H" input, and the initial value "152" is supplied to the counter 22. By loading
A load signal 1FCM (frame clock signal 1FC) consisting of a pulse which becomes “L” at a period of 1.44 seconds is output.

The selection circuit 8 of the first system is configured such that the system switching signal from the control unit (not shown) is “1” and the other system (the first system)
Is selected, and the clock from the 0-system PLO circuit 1 and the load signals MFCM and 1FCM from the timing generation circuit 2 are selected.
Select and output.

In FIG. 8, in the timing generation circuit 7, the 0-system clock input (1
In contrast to 1), a 16M clock having an inter-system delay of 20 ns is supplied to a duty adjustment circuit 9 through a selection circuit delay of 14 ns.
The clock input (15) of 16M whose duty is adjusted to 50% is delayed by 10 ns in the circuit to generate a clock output (17). Further, the timing generation circuit 2
The load signal MFCM is output from the counters 71 and 72 and the D-FFs 73 and 74 using the clock output (17).
And 1FCM.

On the load signal MFCM side, the counter 71
After counting the "65536" clock output (17) of 16M, the carry output CO is latched by the D-FF 73, and the QN output of the D-FF 73 and the load signal MFCM input (16) given through an inter-system delay of 20 ns. By
When the load signal MFCM input (16) is at "L" via the AND circuit 75, the counter 71 is loaded with the initial value "1", so that the load signal MFCM comprising a pulse which becomes "L" in a period of 4 milliseconds. (Frame clock signal MF
C) Output (18) is output with a delay of 10 ns.

On the load signal 1FCM side, the counter 72
As a result, the carry output CO of the counter 71 becomes “36”.
After counting "0", carry output CO is latched by D-FF 74, and QN output of D-FF 73 and load signal 1FCM are output.
By inputting a load signal via an AND circuit 76 and loading the initial value "152" into the counter 72, the load signal 1FCM (frame clock signal) consisting of a pulse which becomes "L" in a period of 1.44 seconds is provided. 1F
C) is output.

In FIG. 6, load signal disconnection detection circuits 5 and 5
Reference numeral 10 denotes clock disconnection detection circuits 51 and 101 for detecting disconnection of the load signal MFCM from another system, and clock disconnection detection circuits 52 and 102 for detecting load signal 1FCM from another system.
Is detected. When disconnection of the load signal MFCM or 1FCM is detected through the OR circuits 53 and 103, the resistance 5
By passing current through the alarm lamps 54 and 104 via the lamps 5 and 105 and lighting them, a load signal disconnection is warned, and an alarm signal is output to a control unit (not shown) to notify the occurrence of the load signal disconnection. I do.

As is clear from the above description,
According to the present invention, the counters in the timing generation circuits of both systems always operate at the same timing even when the system switching occurs in the clock generation device including the system 0 and the system 1; At the same timing before the switching is performed, the frame clocks MFC and 1FC can be generated and supplied to a network (NW) and a line circuit (not shown).

[0052]

As described above, according to the present invention, the upper network
The high-speed clock is synchronized with the external low-speed clock.
Output phase synchronization (PL0) circuits 1 and 6 and high-speed clock
Timing that counts clocks and outputs the frame clock
System including system generation circuits 2 and 7
It has a clock generation device and
Frame clock synchronization circuit
The clock generation circuits 2 and 7 load the initial values and
Is provided, and when the own system is the active system,
Selects a high-speed clock from its own phase synchronization (PLO) circuit.
Output to the counter of the timing generator of the own system.
Count up by force, and own frame clock
And outputs it to the counter of the timing generation circuit of the own system.
Set the load signal to load the initial value.
The high-speed clock from its own phase-locked loop (PLO) circuit
And the high level from other system phase locked loop (PLO) circuit.
Speed clock is selected and output to
Input to the counter to count up, and
Select and output the frame clock from the
Loads the initial value of the counter of the timing generator of own system
Provided with selection circuits 3 and 8 as load signals to be changed
The frame clocks from the 0-system and 1-system clock generators
Since the lock can be always synchronized,
Synchronization is also possible by system switching when applied to electronic exchanges, etc.
There is an advantage that separation does not occur.

[Brief description of the drawings]

FIG. 1 is a diagram showing a basic configuration of the present invention.

FIG. 2 is a diagram showing input signals of a clock generator.

FIG. 3 is a diagram showing one embodiment of the present invention.

FIG. 4 is a diagram illustrating a configuration example of a timing generation circuit.

FIG. 5 is a diagram illustrating a configuration example of a duty adjustment circuit.

FIG. 6 is a diagram illustrating a configuration example of a load signal disconnection detection circuit.

FIG. 7 is a time chart illustrating an operation of the duty adjustment circuit.

FIG. 8 is a time chart illustrating an operation of the timing generation circuit.

[Explanation of symbols]

 Reference Signs List 1 PLO circuit 2 Timing generation circuit 3 Selection circuit 4 Duty adjustment circuit 5 Load signal disconnection detection circuit 6 PLO circuit 7 Timing generation circuit 8 Selection circuit 9 Duty adjustment circuit 10 Load signal disconnection detection circuit

──────────────────────────────────────────────────続 き Continuation of the front page (56) References JP-A-4-290348 (JP, A) JP-A-1-273451 (JP, A) JP-A-61-267493 (JP, A) JP-A-4-294 371096 (JP, A) JP-A-56-31248 (JP, A) JP-A-62-137934 (JP, A) (58) Fields investigated (Int. Cl. ⁷ , DB name) H04M 3/22 H04L 7 / 00

Claims (5)

(57) [Claims] A high-speed synchronous with an external low-speed clock.
A phase synchronization circuit for outputting a clock, and the high-speed clock
To output frame clock by counting
Duplicated clock of system 0 and system 1 including generation circuit
Generating a frame from the clock generator.
Frame clock synchronization for synchronizing system clocks with each other
In the circuit, the timing generation circuit loads an initial value and
A counter for counting the speed clock, and when the own system is an active system , a counter from the phase synchronization circuit of the own system is provided.
Select and output the high-speed clock to generate the timing
Input to the counter of the circuit
Selects and outputs the frame clock of the
Low to load the initial value to the counter of the timing generator
When the own system is a standby system, the phase synchronization of the own system
Block the high-speed clock from the circuit, and
Selects and outputs the high-speed clock from the phase locked loop and automatically
Input to the counter of the timing generation circuit of the
From the timing generation circuit of another system
Select and output the frame clock of
Signal that loads the initial value of the counter of the clock generation circuit
A frame clock synchronization circuit, comprising: a selection circuit for: 2. The counter of the timing generation circuit.
Initial value to be loaded to the load signal path delay compensation
Claims having a configuration set to a value
2. The frame clock synchronization circuit according to 1. 3. The timing generation circuit according to claim 2, wherein
A counter for outputting a frame clock;
Type of frame clock for the own system and other systems.
Configuration as load signal for frame clock compatible counter
The frame clock synchronization circuit according to claim 1 or 2, further comprising: 4. A counter for the timing generation circuit of its own system.
And other systems input to the selection circuit as a load signal
Detection of frame clock from the timing generation circuit
A load signal disconnection detection circuit for performing the output is provided.
The frame clock synchronization circuit according to any one of claims 1 to 3 . 5. The timing generation circuit according to claim 5, wherein
The high-speed clock input to the road
Set the rise and fall delay times of the
The duty adjustment circuit using a 50% high-speed clock is
A timing generator provided before the timing generator.
The frame clock synchronization circuit according to any one of claims 1 to 4 .