JP2949310B2 - Clock supply device and communication network system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock supply device and a communication network system, and more particularly, to a clock supply device suitable for supplying a clock from one communication network to another communication network, and an information processing system using the same. The present invention relates to a communication network system provided in a transmission system.

[0002]

2. Description of the Related Art In a communication network system, when a clock is supplied from one communication network to another communication network, the clock supply system is duplicated, and the other communication network supplies the other clock via the one clock supply system. A method is used in which a clock is supplied to a communication network, and when a failure occurs in one clock supply system, a clock from the other clock supply system is supplied to the other communication network.

[0003] As means for switching the clock supply system,
A selection circuit for selecting one of the clocks from the clock supply systems; a phase comparator for comparing the phase of the output clock of the selection circuit with the clock obtained by multiplying and dividing the clock; A loop filter that smoothes the output signal of the phase comparator, a voltage-controlled oscillator that controls the oscillation frequency according to the output signal of the loop filter, and a frequency-divided output signal of the voltage-controlled oscillator. There is known a frequency divider including a frequency divider returned to a comparator, and a comparator that compares an output signal of a loop filter with a reference voltage and outputs a switching signal to a selection circuit based on a comparison result.

[0004] Also, "IEEE JOURNAL OF"
SOLID-STATE CIRCUIT, VOL2
4, No. 6, December 1989, pp. 1647 to 1655, instead of the comparator for comparing the output of the loop filter with the reference voltage, a counter for counting the number of pulses of the output clock of the selection circuit. A counter for counting the output clock of the frequency divider,
A comparator having a comparator that compares the count values of the respective counters and outputs a switching signal when the two count values are different, and a flip-flop that latches an output pulse of the comparator and outputs a switching signal to a selection circuit. Are known.

[0005]

In each of the above prior arts,
The multiplication means for multiplying the clock selected by the selection circuit is constituted by a PLL having a phase comparator, a loop filter, a voltage controlled oscillator, and a frequency divider. The system adopts a method of detecting an abnormality in the pull-in state of the clock and switching the clock selection circuit based on this detection output.
There is a problem that the response time of LL is included and the clock switching time becomes long. For example, in a system which receives a clock from a time division multiplexing device (TDM) which is widely used in a public network, the clock speed is as low as 64 KHz. Therefore, when supplying a clock to a network system exceeding a transmission speed of 100 Mbps, If jitter suppression is sufficiently considered, the clock pull-in time of the PLL is on the order of several seconds. If the pull-in time is about several seconds, the network is not supplied with the regular clock during this period, so that the telephone system will be disconnected from the "call". Therefore, as described in JP-A-62-73817, the PLL is driven in accordance with an external clock in a normal state, and when a failure occurs in the external clock, the PLL is switched to the self-running clock of the PLL, and the failure of the external clock is detected. It is also conceivable to adopt a method of switching to an external clock again when recovery has been made, but it is difficult to switch the clock supply system while holding the self-running clock even if this method is simply adopted.

An object of the present invention is to provide a clock supply device and a communication network system capable of switching a clock supply system while holding a free-running clock when a failure occurs in the clock supply system.

[0007]

To SUMMARY OF THE INVENTION To achieve the above object, the present invention includes a clock selecting means for selecting in response to the switching signal one of the clock of the clock from a plurality of clock supply system, clock selection Means for multiplying the frequency of the input clock selected by the means and outputting a clock obtained by multiplying the frequency, and monitoring the generation state of the input clock selected by the clock selecting means with reference to the output clock of the multiplying means. Fault detecting means for detecting that a fault has occurred in an input clock; and switching means for outputting a switching signal to a clock selecting means based on a detection output of the fault detecting means, wherein the multiplying means is selected by a clock selecting means. Signal corresponding to the phase difference between the input clock obtained and the feedback clock obtained based on this input clock. A phase comparison DT flip-flop, a loop filter for smoothing an output pulse of the phase comparison DT flip-flop, and an input clock multiplied by controlling an oscillation frequency according to an output signal of the loop filter. A voltage-controlled oscillator that outputs a clock, and a clock obtained by dividing the output clock of the voltage-controlled oscillator and dividing the clock by D
Is composed of a frequency divider for feedback to -T flip-flop, said fault detection means for feedback
DT flip-flop for phase comparison based on clock
Monitor the generation state of the output pulse from the
Prescribed pulse synchronized with clock from flip-flop
For fault detection that outputs a fault detection signal when no fault occurs
This is a configuration of a clock supply device composed of flip-flops .

In configuring the clock supply device,
Can add the following elements:

(1) N failure detection flip-flops connected in cascade are provided, and when N input pulses of the phase comparison DT flip-flop are continuously lost, failure detection is performed from the last flip-flop. It outputs a signal .

(2) When receiving the switching command signal, the switching means is provided with a switching command means for forcibly executing the generation of the switching signal in synchronization with the feedback clock .

The present invention also provides a communication network system in which one communication network and the other communication network are connected via a plurality of clock supply systems, and each clock supply system is connected to the other communication network. between communication networks having any one of the above clock supply device - is obtained by constituting the click system.

Constituting the communication network system
In the Rukoto provided to desirable respective clock supply system division multiplex device when the output impedance of the clock supply system to a high impedance when a failure occurs on the clock from one of the communication networks.

[0013]

When the clock selected by the clock selecting means is multiplied by the multiplying means, the input clock is multiplied according to the output pulse of the DT flip-flop, and the multiplied clock is divided and fed back to the DT flip-flop. Then, based on the feedback clock, it detects that the input clock has failed, and switches the clock supply system based on this detection output.Therefore, it is necessary to switch the clock supply system while holding the free-running clock. PL during the system switching time
Since the response time of L is not included, system switching can be performed in a short time . In addition, if multiple fault detection flip-flops are connected in cascade and a fault is detected when multiple input pulses are continuously lost, the fault can be reliably generated without being affected by external noise. Can be detected .

[0014]

An embodiment of the present invention will be described below with reference to the drawings.

1 and 2, a plurality of stations 14, 16, 18, and 20 are used in a second network 12 for exchanging information with the public network 10. Connected in a loop. The first station 14 is connected to a time-division multiplexer 28, via duplicated clock supply lines 24, 26.
The time division multiplexers 28 and 30 are connected to the public network 10 via transmission lines 32 and 34, respectively. The station 14 has public networks 10 to 64.
A KHz clock is supplied via the time division multiplexers 28 and 30 and the clock supply lines 24 and 26. The clock supply line 24 is used as a clock priority supply system, the clock supply line 26 is used as a standby system, and the station 14 selects a clock from the clock supply line 24 at normal time, and the line 24 fails. Sometimes the clock from line 26 is selected and the frequency of each selected clock is multiplied by 1920 times to 64 KHz
Is output to the transmission line 22 as a clock of 122.88 MHz. The time-division multiplexers 28 and 30 use tristat gates 36 and 38, respectively. Each of the gates 36 and 38 outputs an L signal to the output side when the gate is in the L state and the input side is in the L state. When the input side is an H level signal, an H level signal is output to the output side, and when the gate becomes H level, the output impedance is set to high impedance. That is, each of the time division multiplexers 28 and 30
When a failure occurs in the clock from the public network 10, the outputs of the gates 36 and 38 are set to high impedance.

On the other hand, the station 14 has pull-up resistors 40 and 42, input buffers 44 and 46, waveform shaping circuits 48 and 50, a clock selection circuit 52, and a fault detection circuit 5.
4. A multiplier 56 is used. Each buffer 44, 4
6 is configured so that the clock selected by the clock selection circuit 52 is maintained at a high level even when the clock supply line 24 or 26 is disconnected by using pull-up resistors 40 and 42 in the preceding stage. ing. Further, as shown in FIG. 3, the waveform shaping circuits 48 and 50 have L times smaller than the clock cycle Tc (15.625 μs).
The level period Tl is configured to generate a sufficiently short pulse. The output clocks of the waveform shaping circuits 48 and 50 are supplied to a clock selection circuit 52. The clock selection circuit 52 normally selects a clock from the clock supply line 24, and selects a clock from the clock supply line 26 by a signal from the failure detection circuit 54 when a failure occurs in the clock from the clock supply line 24. It is configured to be.

The multiplier 56 comprises a phase comparator 58, a buffer 6
0, 62, a loop filter 64, a voltage controlled oscillator 66,
The circuit is provided with a frequency divider 68,
Is composed of flip-flops 70, 72 and 74. The phase comparator 58 is composed of a DT flip-flop, compares the phase of the clock selected by the clock selection circuit 52 with the phase of the clock divided by the frequency divider 68, and outputs a clock corresponding to the phase difference to the buffer 60. , 62 to the loop filter 64. The loop filter 64 is configured to smooth the signals from the buffers 60 and 62 to generate a DC voltage. The voltage controlled oscillator 66 controls the oscillation frequency according to the output voltage of the loop filter 64, and multiplies the input clock 52A selected by the clock selection circuit 52 by a clock (122.8).
8 MHz). Divider 6
Reference numeral 8 designates an output clock 66A of the voltage controlled oscillator 66 as 1/1.
Divided to 920, clock 68A with 50% duty ratio
(64 KHz) is returned to the phase comparator 58 as a feedback clock. The multiplier 56 configured as described above functions as a PLL, and when a clock as shown by timings T1 to T3 in FIG.
From the output of the terminal and the divider 68, the clocks 58A, 68
A is output.

On the other hand, the fault detecting circuit 54 is constituted by cascading DT flip-flops 70, 72, 74, and a clock 6 is connected to the T terminals of the flip-flops 70, 72.
8A is input, the clock 52A is input to the R terminal,
The clock 58A based on the output of the phase comparator 58 is input to the D terminal of the flip-flop 70.
The Q terminal of the flip-flop 72 is connected to the T terminal of the flip-flop 74, and the R terminal of the flip-flop 74
The switching command signal C from the controller is input to the terminal. Further, the Q terminal of the flip-flop 74 is connected to the clock selection circuit 52. Then, the flip-flops 70 and 72 monitor the generation state of the clock 58A with reference to the clock 68A. When two clocks 58A are continuously lost, it is determined that a failure has occurred in the clock from the clock supply line 24.
4 is output as a pulse as a failure detection signal. The flip-flop 74 receives a failure detection signal from the flip-flop 72 and outputs a pulse as a switching signal from the Q terminal to the clock selection circuit 52. That is, the flip-flops 70 and 72 are configured as fault detecting means, and the flip-flop 74 is configured as switching means.

In the above configuration, the clock from the clock supply line 24 is supplied to the multiplier 50 via the clock selection circuit 52, and the input clock 52A is multiplied according to the PLL function of the multiplier 50 and the clock 52
When the clock A and the clock 68A are synchronized, the phase comparator 58 and the frequency divider 68 output the timings T1 to T in FIG.
A clock as shown in FIG. That is, P
When LL is locked, the clock 68A is output as a signal having a duty ratio of approximately 50%. Next, as shown after the timing T3R in FIG. 4, when a failure occurs in the clock supply line 24 and the clock 52A is continuously lost, first, the clock 52 at the timing T3R is lost.
A is maintained at the H level, and the output clock 58A of the phase comparator 58 is maintained at the H level without being inverted to the L level. When this state is continued, the flip-flop 70 is set at the timing T4, and the flip-flop 70 detects that one clock is missing. When such a state is further continued, the clock 52A is maintained at the H level also at the timing T4R, the flip-flop 72 is set at the timing T5, and the output pulse of the flip-flop 72 is latched by the flip-flop 74. When the output pulse of the flip-flop 72 is latched by the flip-flop 74, a pulse is output from the flip-flop 74 as a switching signal, and the line is switched by the clock switching circuit 52. That is, the clock from line 26 is selected instead of the clock from line 24.
When the clock is switched, a digital signal of 32 KHz and a duty ratio of approximately 50% is output from each output terminal of the phase comparator 58 by a so-called toggle operation of the phase comparator 58, so that the self-running clock is held. To monitor whether or not the clock 52A has been lost, and can switch the clock when the clock 52A has been lost twice consecutively, and perform the switching without including the response time of the PLL for switching the clock. The clock can be switched on the order of, for example, several milliseconds.

In the above embodiment, the clock 52
Since it is assumed that a failure has occurred when two consecutive A's have been lost, it is possible to prevent the occurrence of a failure from being erroneously detected when the clock 52A is lost due to external noise or the like. Further, when detecting missing clocks, if N flip-flops having the same function as the flip-flops 70 and 72 are connected in cascade, it is possible to detect that a failure has occurred when N clocks 52A are continuously lost. it can.

When the fault is recovered after the timing T4 shown in FIG. 4 and one clock 52A is lost, each flip-flop 70,
Since the clock 72 is reset, it is possible to detect that a failure has occurred only when the clock 52A is lost twice consecutively.

The clocks transmitted through the transmission lines 32 and 34 and the clock supply lines 24 and 26 have the same frequency and the same phase.
Even when the frequency is switched, the frequency and the phase of the output clock 66A of the voltage controlled oscillator 66 do not fluctuate greatly even when the frequency multiplier 56 is pulled back in again as a function of the PLL at the time of the switching, and the stable clock 66A is transmitted to the transmission line 22. Can be supplied.

Next, another embodiment of the present invention will be described with reference to FIGS.
It will be described based on.

In this embodiment, the synchronization circuit 70 is used in a signal system for supplying a switching command signal to the R terminal of the flip-flop 74. When the synchronization circuit 70 receives the switching command signal 200, Clock 6 for feedback
It is configured to generate an output pulse for forcibly latching the flip-flop 74 in synchronization with 8A. The switching command signal 200 is a command from a register in the station 14, and as shown in FIG. 6, a fault occurs, and after switching from the line 24 to the line 26, the fault in the line 24 is removed and the line 24 is in a normal state. Is used to forcibly switch from the line 26 to the line 24 when returning to. In this case, as shown after the timing T6R in FIG. 6, when switching from the line 24 to the line 26 and then switching from the line 26 to the line 24, if the signal 200 and the clock 68A are asynchronous, the line 26 The timing for switching to 24 is asynchronous with the clock 68A, and the time for the multiplier 56 to perform the re-pulling operation becomes longer. However, if the signal 200 is switched from the line 26 to the line 24 while being synchronized with the clock 68A, the synchronization relationship between the clock on the line 26 and the output clock 52A of the clock selection circuit 52 is changed to the clock on the line 24. It is taken over between the clock and the clock 68A, and the redrawing time of the multiplier 56 can be shortened.

In each of the above embodiments, when the clock is switched, the switching can be performed with a switching time of several milliseconds, so that the telephone communication system can be prevented from being disconnected from the "call".

[0026]

As described above, according to the present invention,
When switching clocks from a plurality of clock supply systems, the phase ratio is maintained while the self-running clock of the PLL is held.
Based on the output signal of較用D-T flip-flop, along with failure to clock monitors whether occurs, because you like to switch the clock when the failure occurs from the monitoring result, the clock switching operation Can be greatly reduced. Therefore, if this device is used in a communication network system, the "call" of the communication network
Disconnection can be avoided.

[Brief description of the drawings]

FIG. 1 is a main part configuration diagram showing one embodiment of the present invention.

FIG. 2 is an overall configuration diagram of a system to which the present invention is applied.

FIG. 3 is a waveform diagram of an input clock.

FIG. 4 is a time chart for explaining the operation of the device shown in FIG. 1;

FIG. 5 is a main part configuration diagram showing another embodiment of the present invention.

FIG. 6 is a time chart for explaining the operation of the device shown in FIG. 5;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 Public network 14, 16, 18, 20 Station 36, 38 Time division multiplexer 52 Clock selection circuit 54 Failure detection circuit 56 Multiplier 58 Phase comparator 64 Loop filter 66 Voltage controlled oscillator 68 Divider 70, 72, 74 Flip-flop Step

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Sadao Mizogawa 5-2-1 Omikacho, Hitachi City, Ibaraki Prefecture Inside the Hitachi, Ltd. Omika Plant (72) Inventor Hiroshi Tomizawa 5-chome Omikacho, Hitachi City, Ibaraki Prefecture No. 1 In the Omika Plant of Hitachi, Ltd. (56) References JP-A-55-42443 (JP, A) JP-A-63-50131 (JP, A) JP-A-3-16441 (JP, A) 63-35127 (JP, U) (58) Fields investigated (Int. Cl. ⁶ , DB name) H04Q 11/04 H04L 7/00

Claims (5)

(57) [Claims] 1. A clock selecting means for selecting any one of clocks from a plurality of clock supply systems in accordance with a switching signal, and a clock obtained by multiplying a frequency of an input clock selected by the clock selecting means. A multiplying means for outputting, and a fault detecting means for monitoring a generation state of the input clock selected by the clock selecting means with reference to an output clock of the multiplying means, and detecting from the monitoring result that a fault has occurred in the input clock; Switching means for outputting a switching signal to the clock selecting means in response to a detection output of the fault detecting means, wherein the multiplying means includes an input clock selected by the clock selecting means and a feedback signal obtained based on the input clock. Phase comparison DT flip-flop that outputs a signal corresponding to the phase difference with the clock Filter for smoothing an output pulse of a DT flip-flop for use, a voltage-controlled oscillator for controlling an oscillation frequency according to an output signal of the loop filter and outputting a clock obtained by multiplying an input clock, and an output of the voltage-controlled oscillator Divide the clock and divide the clock by D
Is composed of a frequency divider for feedback to -T flip-flop, said fault detection means for feedback
DT flip-flop for phase comparison based on clock
Monitor the generation state of the output pulse from the
Prescribed pulse synchronized with clock from flip-flop
For fault detection that outputs a fault detection signal when no fault occurs
Clock supply device composed of flip-flops . 2. A cascade-connected N number of fault detection flip-flops, and when N input pulses of a phase comparison DT flip-flop are continuously lost, a fault detection signal is output from the last flip-flop. Claims that output
2. The clock supply device according to 1 . Wherein in synchronization with the clock for feedback when receiving a switching instruction signal, the clock supply of which claim 1 or 2, wherein a switching command means for forcibly executing the generation of the switching signal to the switching means apparatus. 4. the one communication network and the other communication networks connected via a plurality of clock supply system, any one of claims 1, 2 and 3 between the respective clock supply system and the other communication networks A communication network system comprising the clock supply device according to any one of the preceding claims. 5. The communication according to claim 4 , wherein each clock supply system is provided with a time-division multiplexing device that sets the output impedance of each clock supply system to a high impedance when a failure occurs in a clock from one communication network. Network system.