JP2874632B2 - Clock switching circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a system which uses one of two input system clocks.
The present invention relates to a clock switching circuit that switches to another spare clock.

[0002]

2. Description of the Related Art A clock switching circuit is used, for example, when switching one of two input clocks to a spare clock when one of the currently used clocks is disconnected due to some abnormality. Used for

When two clocks are input with their phases synchronized, a slight phase difference occurs between the clocks due to differences in the transmission path environment such as a cable. Depending on the timing at which the clock is switched due to this phase difference, an extra pulse with a short width is generated in the output clock (so-called “clock cracking”). In the clock switching circuit, it is important to prevent the output clock from cracking. For example, a circuit as shown in FIG. 6 (see Japanese Patent Application Laid-Open No. 4-51716) is disclosed.

FIG. 6 is a block diagram showing a configuration of a conventional clock switching circuit.

In FIG. 6, a working clock which is normally used is inputted from a first input terminal and inputted to a working PLO circuit 21 which converts the inputted clock into a clock having a frequency which is a predetermined ratio multiple of that of the inputted clock. The backup clock used for backup is input from the second input terminal, and is input to the backup PLO circuit 22 which converts the input clock into a clock having a frequency which is a predetermined multiple of the input clock in the same manner as the current clock.

Output of working PLO circuit 21 and spare PLO
The output of the circuit 22 is input to a selection circuit 29 for selecting two clocks. The active PLO circuit 21 and the backup PLO circuit 22 output an alarm signal indicating an abnormality of the clock input or the like, and input the alarm signal to a switching control unit 23 that outputs a clock switching control signal.

[0007] In addition to the above two alarm signals, a switching signal for instructing clock switching is input to the switching control unit 23 via a switching control input terminal, and a switching signal as an external switching command or an alarm signal. Changes the clock.

The working PLO circuit 21 and the spare PLO circuit 2
2 output from the working PLO circuit 21 and the standby PLO circuit 2
An AND circuit 24 for capturing the later rising phase of the clock output from the PLO circuit 2;
1 and a clock output from the backup PLO circuit 22 and a NOR circuit 25 for capturing the later falling phase.

The output of the AND circuit 24 is the first output for dividing by two.
, And the outputs of the first flip-flop circuit 26 and the NOR circuit 25 are input to an OR circuit 27 for calculating the logical sum of each. Here, the first flip-flop circuit 26 is turned on when the clocks output from the working PLO circuit 21 and the backup PLO circuit 22 are completely in phase (steady phase difference = 0).
It is inserted so that the output of the R circuit 27 does not disappear.

The output of the switching control unit 23 and the output of the OR circuit 27 are respectively input to a second flip-flop circuit 28, and the output of the switching control unit 23 is retimed by the output of the OR circuit 27. The output of the second flip-flop circuit 28 is input to a selection circuit 29 for selecting one of the clocks output from the working PLO circuit 21 and the backup PLO circuit 22, and the clock selected from the selection circuit 29 is output from the clock output terminal. Is output.

With such a circuit configuration, of the outputs of the working PLO circuit 21 and the backup PLO circuit 22, the clock switching timing is set to the rising edge of the clock having the later phase or the falling edge of the clock having the later phase. To prevent the output clock from cracking at the time of clock switching even if there is a steady phase difference between the two clocks.

As another example of the conventional clock switching circuit, there is a circuit disclosed in Japanese Patent Application Laid-Open No. 2-128208.

In the clock switching circuit disclosed in Japanese Patent Application Laid-Open No. 2-128208, a synchronization clock generation means for detecting a period in which one clock signal and the other clock signal are simultaneously at a low level, and a synchronization clock generation circuit A switching synchronizing means for generating a clock switching signal in synchronization with an output of the means, and synchronizing clock switching operations during a period when both clock signals are at a low level to prevent cracking of an output clock. Have been.

[0014]

However, among the conventional clock switching circuits as described above, Japanese Patent Application Laid-Open No. 4-51
In the clock switching circuit disclosed in Japanese Patent No. 716, in order to prevent the output of the OR circuit from being lost when the output clock of the working PLO circuit and the output clock of the backup PLO circuit are completely aligned, The first flip-flop circuit divides the output pulse of the AND circuit by two.

At this time, since the cycle for synchronizing the clock switching signal with the phase of the working clock or the spare clock is twice as long as the clock, for example, the working clock is cut off and the cycle becomes high or low. When fixed, the number of pulses of the output clock becomes smaller than that of the input clock depending on the switching timing.

On the other hand, in the clock switching circuit disclosed in Japanese Patent Application Laid-Open No. 2-128208, when one clock is cut and fixed at a high level, one clock and the other clock are simultaneously set to a low level. , The clock switching period is not detected, and the clock is not switched, so that the clock may not be supplied to the system connected to the output of the clock switching circuit.

The present invention has been made to solve the above-mentioned problems of the prior art, and is not affected by a minute phase difference generated between two clocks, and is used. It is an object of the present invention to provide a clock switching circuit that can surely switch clocks even when a clock that has been cut is fixed at a high level or a low level.

[0018]

In order to achieve the above object, a clock switching circuit according to the present invention is a clock switching circuit for switching from a used first clock to a spare second clock as required and outputting the clock. In the circuit, an exclusive OR of the first clock and a signal obtained by delaying the phase of the first clock by 90 degrees is used, and the first clock is set to 2
A first reception processing means for doubling the frequency, an exclusive OR of the second clock and a signal obtained by delaying the phase of the second clock by 90 degrees to obtain a second frequency of the second clock A second reception processing unit, an OR circuit for performing an OR operation on an output signal of the first reception processing unit and an output signal of the second reception processing unit, and negation of an output signal of the OR circuit A NOT circuit for outputting a signal, the first clock, an output signal of the first reception processing means, and an output signal of the NOT circuit are input, and indicate whether or not the first clock is disconnected. A clock monitoring circuit that outputs a clock monitoring signal, a flip-flop circuit that samples and holds the clock monitoring signal with an output signal of the negation circuit, the first clock and the second clock.
Is selected, and the first clock is selected and output according to the output signal of the flip-flop circuit when the first clock is not cut off,
A selection circuit for selecting and outputting the second clock while the first clock is cut off.

At this time, the clock monitoring circuit sets the phases of the first clock and the first clock to 180.
A third reception processing means for taking an exclusive OR of the delayed signals, an output signal of the first reception processing means, and an output signal of the negation circuit, respectively, and the first reception processing means and ANDing the output signal of the third reception processing means and the output signal of the monitoring means with the monitoring means for detecting whether or not there is an output pulse of the reception processing means;
And an AND circuit that outputs a clock monitoring signal as to whether or not the clock is cut off.

As another configuration of the clock switching circuit, a clock switching circuit for switching from the first clock being used to a spare second clock as necessary and outputting the second clock is provided. First reception processing means for taking an exclusive OR of a signal obtained by delaying the phase of the first clock by 90 degrees to make the frequency of the first clock double, the second reception processing means, and the second clock; A second reception processing means for calculating an exclusive OR of a signal obtained by delaying the phase of the clock by 90 degrees to make the second clock a double frequency; an output signal of the first reception processing means; An OR circuit that performs an OR operation on an output signal of the second reception processing unit, a NOT circuit that outputs a NOT signal of an output signal of the OR circuit, and a disconnection of the first clock, wherein The clock Control means for outputting a clock monitoring signal for switching to the second clock; a flip-flop circuit for sampling the clock monitoring signal with an output signal of the NOT circuit and holding a result; Receiving the second clock,
According to the output signal of the flip-flop circuit, when the first clock is not cut off, the first clock
And a selection circuit for selecting and outputting the second clock while the first clock is cut off.

In the clock switching circuit configured as described above, since the logical sum of the output signal of the first reception processing means and the output signal of the second reception processing means is calculated by the logical sum circuit, the first clock , The signal supplied to the clock monitoring circuit and the flip-flop circuit for operating the selection circuit for selecting the clock is not interrupted.

The first and second reception processing means convert the first clock and the second clock into clocks each having a half cycle, and the clock having the phase delayed Since the flip-flop circuit operates when the phase is delayed by 90 degrees from the rising and falling edges, the selection circuit operates without being affected even if there is a slight phase difference between the first clock and the second clock. I do.

[0023]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of the clock switching circuit of the present invention, and FIG. 2 is a time chart showing the operation of the clock switching circuit shown in FIG.

The symbols in parentheses below represent the signals shown in the time chart of FIG.

In FIG. 1, 1 is a first clock (A).
Is a first delay circuit for delaying the phase of the first delay circuit by 90 °, and a first exclusive OR circuit 2 calculates the exclusive OR of the first clock (A) and the output signal (C) of the first delay circuit 1 The circuit 3 is a second delay circuit for delaying the phase of the second clock (B) by 90 °, and the reference numeral 4 is the second clock (B) and the second delay circuit 3.
A second exclusive OR circuit 5, which takes an exclusive OR with the output signal (D) of the second exclusive OR circuit 5, and an output (E) of the first exclusive OR circuit 2 and a second exclusive OR circuit 4 A logical sum circuit for calculating a logical sum with the output (F); and 6, an output (G) of the logical sum circuit 5
, The first clock (A), the output (E) of the first exclusive OR circuit 2 and the output (K) of the negative circuit 6 are input to the first clock (A). A) a clock monitoring circuit for monitoring a fault; 8) sampling the output (M) of the clock monitoring circuit 7 with the output (K) of the NOT circuit 6;
The flip-flop circuit 9 for holding the result uses the first clock (A) and the second clock (B) to detect a failure in the first clock (A) by the output (N) of the flip-flop circuit 8. A selection circuit for selecting the second clock (B) during the operation.

In such a configuration, the operation of the clock switching circuit shown in FIG. 1 will now be described with reference to FIG.

Note that the time chart of FIG. 2 shows that the first clock (A) is disconnected from the state in which the phase of the first clock (A) is advanced with respect to the phase of the second clock (B), and becomes high level. The state when fixed is shown.

In FIG. 2, the output signal (E) of the first exclusive OR circuit 2 which is the exclusive OR of the first clock (A) and the output signal (C) of the first delay circuit 1 is obtained. ) Is a signal having a half cycle of the first clock (A). Similarly, the output signal (F) of the second exclusive OR circuit 4 which is the exclusive OR of the second clock (B) and the output signal (D) of the second delay circuit 3 is the second Clock (B) 2
It becomes a signal with a period of 1 /.

The rising edge of the output signal (K) of the NOT circuit 6 which outputs the logical sum of the signal (E) and the signal (F), which is the logical OR of the signal (F),
That is, the second clock (B) coincides with the phase where the phase is delayed by 90 ° from the rising edge and the falling edge.

Since the flip-flop circuit 8 samples the clock monitoring signal (M) indicating the result of monitoring the failure of the first clock (A) at the timing of the signal (K), the clock selection signal (N) Has a phase of 90 ° from the rising and falling of the second clock (B).
Match where delayed.

The fault monitoring operation of the clock monitoring circuit 7 will be described later.

Here, as shown in FIG. 2, since the logical sum of the signal (E) and the signal (F) is obtained by the logical sum circuit 5, even if the first clock (A) is cut off, the signal (K)
Is not fixed to the high level or the low level, so that the clock switching process is reliably performed.

In addition, since the clock selection signal (N) for switching the clock is delayed by 90 ° from the rising and falling of the second clock (B), the clock selection signal (N) is synchronized. It is not affected by the phase difference (clock crack, etc.).

Next, the clock monitoring circuit 7 will be described with reference to FIGS.

FIG. 3 is a block diagram showing a configuration of the clock monitoring circuit shown in FIG. FIG. 4 is a time chart showing the operation of the clock monitoring circuit shown in FIG.

In FIG. 3, reference numeral 71 denotes a 180 ° delay circuit for delaying the phase of the first clock (A) by 180 °;
An EXOR circuit 72 takes an exclusive OR of the first clock (A) and the output (W) of the 180 ° delay circuit 71.

Reference numeral 74 denotes an output signal (K) of the NOT circuit 6
The counter circuit 75 outputs the signal (S) after a predetermined time, and the output signal (E) of the first exclusive OR circuit 2 is used as a down-counting clock, and the output signal (K) of the NOT circuit 6 UP as a clock for counting up
A / DOWN counter circuit 76 has an output BO of a down counter and an output CA of an up counter for notifying a predetermined count performed by the UP / DOWN counter circuit 75.
An OR circuit 77 for obtaining a logical sum of the signals; a delay circuit 78 for delaying the output signal (S) of the counter circuit 74 by a predetermined time;
Is the first F / F which is set by the output signal (R) of the OR circuit 76 and reset by the output signal (T) of the delay circuit 77
(Flip-flop) circuit, 79 is the first F / F circuit 7
8 is a second F / F (flip-flop) circuit which samples the output signal (U) of the counter circuit 74 with the output signal (S) of the counter circuit 74 and outputs the sampled signal. Reference numeral 73 denotes the output signal (X) of the EXOR circuit 72 and the second signal. This is an AND circuit that takes the logical product of the output signal (V) of the F / F circuit 79 and outputs a clock monitoring signal (M). Note that “m” in FIG. 3 sets the count number of the UP / DOWN counter circuit 75 and is set to a predetermined value.

In such a configuration, the operation of the clock monitoring circuit 7 will now be described with reference to FIG.

FIG. 4A shows a state in which the phase of the first clock (A) is ahead of the phase of the second clock (B), and the first clock (A) is cut off and becomes low. This shows a case where the level is fixed. FIG.
(B) shows a case where the first clock (A) recovers from the disconnected state and its phase rises later than the second clock (B).

First, when the first clock (A) is normal, an up / count clock (signal (K)) and a down / count clock (signal (E)) are input, respectively, so that the UP / DOWN counter circuit is used. 75 does not work,
The output signal (R) of the OR circuit 76 is fixed at a low level “L”, and the output (V) of the second F / F circuit 79 is fixed at a high level “H”.

Here, when the first clock (A) is cut off, the output (X) of the EXOR circuit 72 becomes low level.
The clock monitoring signal M becomes L level, and the clock monitoring signal M becomes low level L, and the clock switching process is performed within one clock (see FIG. 4A).

At this time, the output signal (E) of the first exclusive OR circuit 2 is fixed at the low level "L", and the UP / DO
After the WN counter circuit 75 starts counting up, a signal CA notifying a predetermined count number of the up-count is output after a predetermined time. Then, the output (R) of the OR circuit 76 becomes high level “H”, and the first F / F circuit 7
The output (U) of No. 8 becomes high level "H". Second F /
The F circuit 15 samples this signal (U) at the timing of the output signal (S) of the counter circuit 74, and the inverted output (V) becomes low level "L".

On the other hand, when the first clock (A) recovers from the disconnected state, the signal (X) becomes high level "H" within one clock.

At this time, the output signal (T) of the delay circuit 77
Thereby, the first F / F circuit 78 is reset.
However, according to the timing of the output signal (S), the second F / F circuit 79 performs the second sampling until sampling is performed.
The output (V) of the F / F circuit 79 is fixed at the low level "L", and the clock monitoring signal (M) is also held at the low level "L" (see FIG. 4B).

That is, the clock monitoring signal M becomes high level "H" a predetermined time after the recovery of the first clock (A), so that the received clock is stabilized in the clock switching process. It is done after.

With this configuration, when the first clock (A) is cut off, the clock monitor signal (M) is output so that the clock switching process is performed within one clock, and the first clock (M) is output. When the clock is recovered, the clock monitoring signal (M) is output so that the switching process is performed after the clock is stabilized.

The clock monitoring circuit is not included in the configuration as shown in FIG.
May be configured to monitor the disconnection of the clock and input a clock monitoring signal (M) for switching to the second clock to the flip-flop circuit (F / F circuit). In this case, the other components operate in the same manner except that the clock monitor signal (M) is generated internally or input externally.

[0049]

Since the present invention is configured as described above, the following effects can be obtained.

The OR circuit takes the logical sum of the output signal of the first reception processing means and the output signal of the second reception processing means, so that the selection circuit selects the clock even if the first clock is cut off. The signal supplied to the clock monitoring circuit and the flip-flop circuit for operating the circuit is not interrupted, and the clock switching operation is performed reliably.

When the phase is delayed by 90 degrees from the rising and falling edges of the clock having the delayed phase,
Since a clock monitoring circuit and a flip-flop circuit for operating a selection circuit for selecting a clock operate,
The selection circuit can switch clocks without being affected even if there is a small phase difference between the first clock and the second clock.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a clock switching circuit according to the present invention.

FIG. 2 is a time chart illustrating an operation state of the clock switching circuit illustrated in FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a clock monitoring circuit illustrated in FIG. 1;

FIG. 4 is a time chart showing an operation state of the clock monitoring circuit shown in FIG. 3;

FIG. 5 is a block diagram showing another configuration of the clock switching circuit of the present invention.

FIG. 6 is a block diagram illustrating a configuration of a conventional clock switching circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 1st delay circuit 2 1st exclusive OR circuit 3 2nd delay circuit 4 2nd exclusive OR circuit 5 OR circuit 6 Negation circuit 7 Clock monitoring circuit 8 Flip-flop circuit 9 Selection circuit 71 180 ° Delay circuit 72 EXOR circuit 73 AND circuit 74 Counter circuit 75 UP / DOWN counter circuit 76 OR circuit 77 Delay circuit 78 First F / F circuit 79 Second F / F circuit

Continuation of the front page (58) Fields investigated (Int.Cl. ⁶ , DB name) G04F 7/00-13/06 G06F 1/04 H03L 7/00 H04L 1 / 22,7 / 00

Claims (3)

(57) [Claims] 1. A clock switching circuit for switching from a used first clock to a spare second clock as necessary and outputting the same, wherein the phases of the first clock and the first clock are 9
First reception processing means for taking an exclusive OR of the signals delayed by 0 degrees to make the first clock a double frequency; and setting the phases of the second clock and the second clock to 9
A second reception processing means for taking an exclusive OR of the signal delayed by 0 degrees to make the second clock a double frequency; an output signal of the first reception processing means and the second reception processing An OR circuit for obtaining a logical sum of output signals of the means, a NOT circuit for outputting a NOT signal of an output signal of the OR circuit, the first clock, an output signal of the first reception processing means, and A clock monitoring circuit to which an output signal of the negation circuit is input and which outputs a clock monitoring signal indicating whether or not the first clock is disconnected; and sampling and holding the clock monitoring signal with an output signal of the negation circuit. And the first clock and the second clock are input, and the first clock is cut off according to an output signal of the flip-flop circuit. A clock selector for selecting and outputting the first clock when there is no clock, and selecting and outputting the second clock while the first clock is cut off. circuit. 2. The clock switching circuit according to claim 1, wherein the clock monitoring circuit sets the phases of the first clock and the first clock to one.
A third reception processing unit that takes an exclusive OR of the signal delayed by 80 degrees, an output signal of the first reception processing unit, and an output signal of the negation circuit are input, respectively, Monitoring means for detecting whether there is an output pulse of the reception processing means, and ANDing the output signal of the third reception processing means and the output signal of the monitoring means, and cutting off the first clock. And a logical AND circuit for outputting a clock monitoring signal indicating whether or not the clock is switched. 3. A clock switching circuit for switching from a used first clock to a spare second clock as necessary and outputting the same, wherein the phases of the first clock and the first clock are 9
First reception processing means for taking an exclusive OR of the signals delayed by 0 degrees to make the first clock a double frequency; and setting the phases of the second clock and the second clock to 9
A second reception processing means for taking an exclusive OR of the signal delayed by 0 degrees to make the second clock a double frequency; an output signal of the first reception processing means and the second reception processing A logical sum circuit for calculating a logical sum of the output signals of the means, a negative circuit for outputting a negative signal of the output signal of the logical sum circuit, and detecting a disconnection of the first clock; Control means for outputting a clock monitoring signal for switching to the second clock; a flip-flop circuit for sampling the clock monitoring signal with an output signal of the negation circuit and holding a result; 2 is input, and the first clock is selected and output according to the output signal of the flip-flop circuit when the first clock is not cut off. Wherein while the first clock is disconnected clock switching circuit characterized by having a selection circuit for selecting and outputting said second clock.