JPH05324118A - Automatic clock switching system and its circuit - Google Patents

Abstract

PURPOSE:To switch a working clock to a stand-by clock without generating a hazard by detecting an OFF level state also simultaneously with OFF detection when the working clock is turned off CONSTITUTION:When a clock CKA OFF detecting circuit 1 or a clock CKB OFF detecting circuit 2 detects the generation of clock OFF, an automatic clock switching display part 3 detects whether the OFF clock is a working clock or not by comparing the detected result with the set state of a manual switching signal SEL. On the other hand, an OFF clock 'H' level fixing detecting part 4 detects which level, 'H' or 'L', turns the working clock turned off to an OFF fixed state. A clock switching control part 7 generates a switching command signal at a position where the level of a stand-by clock coincides with that of the OFF working clock and controls a clock selector 8, so that the working clock is automatically switched to the stand-by clock.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an automatic clock switching system and its circuit in an electric device having two clock circuits.

[0002]

2. Description of the Related Art In a digital signal processing type communication device or the like, a synchronous clock as a reference for processing operation is indispensable. If this clock is cut off, the system will go down. Therefore, in the prior art, two systems of the same clock circuit are prepared, one of them is operated in parallel and the other is operated in parallel, and when a failure occurs in the current clock circuit, the spare clock circuit is used. I was trying to switch to.

FIG. 8 shows a configuration example of a conventional clock loss detection circuit, and FIG. 10 shows a configuration example of a conventional clock switching circuit. Note that the clock break detection circuit in FIG. 8 shows only the clock break detection circuit for the clock CKA of the two systems of clocks CKA and CKB. In fact, the same detection circuit is provided for the other clock CKB.

The operation of the clock loss detection circuit of FIG. 8 will be described with reference to the time chart of FIG. Timer circuit 10
The clock disconnection detection pulse S1 output by 1 is frequency-divided by the frequency dividing circuit 102, and is input to the clock terminal CK of the flip-flop 103 as the frequency divided signal S2. The frequency-divided signal S2 is inverted by the NOT gate 104, given a slight delay in the delay cell 105, and input to the reset terminal R of the flip-flop 106.

When the disconnection detection target clock CKA is disconnected, the signal S3 turns off the flip-flop 106,
The output S4 becomes "L". Then, after a predetermined time set by the division ratio, the division pulse S2 is output from the division circuit 102.
Is given to the clock terminal CK of the flip-flop 103, the output S4 of the flip-flop 103 is "L".
, And outputs a clock CKA disconnection alarm signal ALMA from the Q ^- terminal to inform that the clock CKA has been disconnected by, for example, an alarm lamp or alarm buzzer (not shown).

Next, the operation of the clock switching circuit of FIG. 10 will be described with reference to the time chart of FIG. When the clock CKA is selected as the working clock, the manual clock switching signal SEL is set to "L". Therefore, "L" is given to one input terminal of the AND gate 202, and "H" inverted by the NOT gate 203 is given to one input terminal of the AND gate 201. It becomes conductive and the clock CKA is output as the current clock CKO through the OR gate 204.

Now, when the occurrence of the clock CKA interruption is detected by the clock interruption detection circuit shown in FIG. 8 and this is notified by an alarm lamp or a buzzer, the monitoring staff changes the manual clock switching signal SEL from "L" to "L". Switch to H ".
As a result, the AND gate 201 is turned off, the AND gate 202 is turned on, and the clock CKB is replaced by the AND gate 202 and the OR gate 204 instead of the clock CKA.
Is output as the current clock through.

[0008]

As described above, conventionally, the disconnection detection circuit and the clock switching circuit are provided as separate circuits, and the clock disconnection detection circuit of FIG. 8 detects the occurrence of the clock disconnection. By notifying the outside and recognizing this by the monitor, by manually switching the manual clock switching signal SEL of the clock switching circuit of FIG. 10 from “L” to “H” or from “H” to “L” , The current clock from CKA to CKB, or CK
I was switching from B to CKA.

Therefore, there is a problem that it takes a considerable time from the detection of the clock failure to the actual switching to the other clock, and the system down time due to the clock failure becomes long. Further, since the clock switching is manually performed asynchronously with the clock, depending on the switching timing, a hazard may occur during the switching, as shown in FIG.

The present invention has been made in view of the above circumstances, and an object thereof is to automatically switch clocks to a spare clock without causing a hazard when a clock break occurs in a working clock. A method and its circuit are provided.

[0011]

The automatic clock switching system of the present invention is provided with two clocks, and one of the clocks is used as an active clock and the other clock is used as a spare automatic clock switching in an electric device. In the system, when the active clock is disconnected, the disconnection level state is detected at the same time as the disconnection detection, and the standby clock is detected from the active position at a timing position matching the disconnection level state of the disconnected active clock. It automatically switches to the spare clock.

Further, the automatic clock switching circuit of the present invention has a clock CKA disconnection detecting unit 1 for monitoring the occurrence of disconnection of the first clock CKA, as shown in the principle configuration of FIG.
Clock CK for monitoring occurrence of disconnection of second clock CKB
B disconnection detection unit 2, automatic clock switching display unit 3 that generates an automatic clock switching signal CHGCK based on the disconnection detection signals of the two disconnection detection units 1 and 2, and disconnects when the current clock is in the "H" level state. Disconnection clock “H” level fixed detection unit 4 for detecting whether or not the disconnection clock “H”
A clock “H” level coincidence detection unit 5 for detecting a timing position at which the backup clock becomes “H” level when the level fixation detection unit 4 detects “H” level disconnection fixation.
A clock "L" level coincidence detection unit 6 for detecting a timing position at which the backup clock becomes "L" level when the disconnection clock "H" level fixation detection unit 4 does not detect "H" level disconnection fixation. Based on the automatic clock switching signal of the automatic clock switching display unit 4 and the level matching signals of the clock “H” level matching detection circuit 5 and the clock “L” level matching detection circuit 6, a switching command is issued at a timing position where no hazard occurs. The clock switching control unit 7 outputs a signal, and the clock selector 8 switches a clock from a working clock to a backup clock based on a switching command signal from the clock switching control unit 7.

[0013]

[Operation] FIG. 2 shows a switching state diagram when the two systems of clocks CKA and CKB are arbitrarily switched. In the figure,
SEL is a manual clock switching signal for switching the clock, and CKO is a currently used clock that is selectively output. As is clear from FIG. 2, the clocks CKA and C
When the clocks are switched in the area portion where the levels of KB are “H” level and “L” level disagreement, a hazard occurs at the clock switching position.

On the other hand, when the clocks are switched at the area position where both the clocks CKA and CKB have the level matching at the "L" level and the area position where the clocks CKA and CKB have the level matching at the "H" level, a hazard occurs at the clock switching position. There is nothing to do. Therefore, when the working clock is cut off, if the working clock is switched to the spare clock at the timing position where the levels of the broken working clock and the spare clock match each other, the clock is switched without causing a hazard. be able to. The present invention is based on such a principle.

In FIG. 1, the clock CKA disconnection detection circuit 1 monitors the disconnection of the clock CKA, and the clock CKB disconnection detection circuit 2 monitors the disconnection of the clock CKB. When the disconnection occurs, disconnection alarm signals ALMA and ALMB are output. It occurs respectively.

When the clock CKA disconnection detection circuit 1 or the clock CKB disconnection detection circuit 2 detects the occurrence of a clock disconnection, the automatic clock switching display unit 2 compares the setting state of the manual switching signal SEL to disconnect. Whether or not the clock is the working clock is detected, and when the working clock is cut off, the automatic clock switching signal CHGCK is generated.

On the other hand, in the disconnection clock "H" level fixed detection section 4, the disconnected current clock is "H" or "L".
The level at which the disconnection / fixation state is reached is detected.
When the working clock is fixed at the "H" level, the clock "H" level coincidence detecting section 6 detects the timing position at which the spare clock goes to the "H" level, and the level is set at that position. Output a match signal. When the working clock is "L" level and is fixedly disconnected, the clock "L" level coincidence detecting section 6 detects the timing position at which the spare clock becomes "L" level, and Outputs the level match signal.

The clock switching control section 7 generates a switching command signal at a position that matches the level state of the working clock in which the level of the backup clock is cut off, and controls the clock selector 8 to shift the working clock from the working clock. Automatically switch the clock to the spare clock.

[0019]

FIG. 3 shows an embodiment of an automatic clock switching circuit of the present invention constructed by applying the method of the present invention. In the figure, the clock CKA disconnection detection unit 1 is composed of flip-flops 11 and 12, a frequency dividing circuit 13, a NOT gate 14, and a delay cell 15. The clock CKB break detection unit 2 includes flip-flops 21 and 22, a frequency dividing circuit 23,
It is composed of a NOT gate 24 and a delay cell 25.
The disconnection detection units 1 and 2 are the same as the conventional disconnection detection circuit (FIG. 8) except that the counterpart clocks CKA and CKB are used as the input signals of the frequency dividing circuits 13 and 14, respectively.

The automatic clock switching display unit 3 is a circuit for generating an automatic clock switching signal when the current clock is cut off, and is composed of AND gates 31, 32, an OR gate 33 and a NOT gate 34.

The disconnection clock "H" level fixed detection unit 4 is
This is a circuit for detecting whether or not the current clock is disconnected in the "H" level fixed state, and AND gates 41, 42,
It is composed of an OR gate 43.

The clock "H" level coincidence detecting section 5 uses the clock C to prevent hazards at the time of clock switching.
This is a circuit for detecting the matching position of "H" level of KA and CKB, and is composed of an AND gate 51. The clock “L” level coincidence detection unit 6 is a circuit that detects the coincidence position of the clocks CKA and CKB at the “L” level in order to prevent hazards at the time of clock switching.
It is composed of a gate circuit 61.

The clock switching controller 7 is a circuit that generates a switching command signal at a timing position where no hazard occurs, and includes a flip-flop 71 and an exclusive OR (EX).
It is composed of an OR gate 72 and an OR gate 73.

The clock selector 8 is a circuit for selectively outputting either the clock CKA or CKB as the working clock CKO in accordance with the clock switching command signal given from the clock switching control section 7, and from the AND gates 81 and 82 and the OR gate 83. It is configured.

Next, the operation of the above-described embodiment will be described in order for different cases. [I] Manual switching operation when clock is normal (see FIG. 4) FIG. 4 shows a time chart of the switching operation in this case. The embodiment circuit of FIG. 3 selectively outputs the clock CKA when the manual switching signal SEL is “L”,
The clock CKB is selectively output when it is "H".

The manual clock switching signal SEL is "L"
Is set to the clock CKA as the current clock CKO.
Is output. Now, the working clock is C
When the manual clock switching signal SEL is switched from "L" to "H" in order to switch from KA to CKB, E
The output S5 of the XOR gate 72 becomes "H". On the other hand, the NOR gate 61 of the clock “L” level coincidence detector 6
Becomes "H" when the "L" levels of the clocks CKA and CKB match, and the output S is output via the OR gate 73.
7 = “H” is the clock terminal CK of the flip-flop 71
Send to.

At the rising edge of the output S7, the flip-flop 71 latches the "H" of the output S5 sent from the EXOR gate 72, and outputs Q = "H", Q.
^- = "L". As a result, A of the clock selector 8
The ND gate 81 is turned off and the AND gate 82 is turned on, so that the clock CKB is output as the working clock CKO in place of the clock CKA output up to that point.

[II] Automatic switching operation when the clock CKA is cut off in the "L" level fixed state (see FIG. 5) A time chart of the switching operation in this case is shown in FIG. When the clock CKA is selected while the manual clock switching signal SEL is set to “H” and the clock CKA is fixed at the “L” level, the flip-flop 12 of the clock CKA disconnection detection circuit 1 causes the frequency division circuit 13 to operate. This is detected after a certain time given by the output S3 and the clock CKA disconnection alarm signal ALM is output from the Q ^- terminal.
A = “H” is output to inform that the clock CKA is cut off.

When the clock CKA disconnection alarm signal ALMA becomes "H", AN of the automatic clock switching display unit 3 is displayed.
The D gate 31 becomes conductive, and the OR gate 33 outputs the automatic clock switching signal CHGCK = "H". This CHGCK signal is output to the outside, and at the same time, sent to one input terminal of the EXOR gate 72 of the clock switching control unit 7. Since the manual clock switching signal “L” (CKA selected state) is input to the other input terminal of the EXOR gate 72, the output S5 of the EXOR gate 72 becomes “H” at this point, and S5 = “H” It is sent to the D terminal of the flip-flop 71.

On the other hand, the clock "L" level coincidence detector 6
The NOR gate 61 sets the output S7 to "H" at the time when the clock CKB becomes "L" level and sends the output S7 to the clock terminal CK of the flip-flop 71.

The flip-flop 71 at the rising edge of the S7, the latches "H" of the output S5 in EXOR gate 72, the output Q = "H", ^Q - = becomes "L". As a result, the AND gate 81 of the clock selector 8
Is turned off and the AND gate 82 is turned on. Instead of the clock CKA that has been output until then, the clock CK
B is output as the working clock CKO.

[III] Automatic switching operation when the clock CKA is cut off in the "H" level fixed state (see FIG. 6) FIG. 6 shows a time chart of the switching operation in this case. The operation until the clock CKA disconnection detection unit 1 detects the disconnection of the clock CKA and the output S5 of the EXOR gate 72 in the clock switching control unit 7 is switched to “H” is completely the same as the operation of the above [II]. Is the same. However, as shown in FIG. 6, when the clock CKA is disconnected in the “H” level fixed state, the clock “L” level coincidence detection unit 6 cannot detect the “H” level coincidence. Cannot be automatically switched.

Therefore, in the present invention, the disconnection clock "H" level fixing detector 4 monitors whether or not the current clock is disconnected in the "H" level fixing state, and the current clock is fixed at "H" level. When the disconnection occurs in the state, instead of the clock “L” level coincidence detection unit 6, the clock “H”
The level coincidence detecting section 5 detects a timing position where the clocks CKA and CKB coincide at the “H” level, and switches the clock from CKA to CKB at this timing position.

That is, the current clock CKA is "H".
When the disconnection occurs in the level-fixed state, the AND gate 41 in the disconnection clock “H” level fixation detection unit 4 becomes conductive, and the OR gate 43 outputs the output S6 = “H” indicating the “H” level fixation. The output S6 is sent to the NOR gate 61 of the clock “L” level coincidence detection unit 6 and the AND gate 51 of the clock “H” level coincidence detection unit 5, respectively.

AN of the clock "H" level coincidence detector 5
The other input terminals of the D gate 51 are connected to the clocks CKA and C.
KB has been entered. Therefore, when the standby clock CKB becomes "H" level, the AND gate 51
Becomes conductive, and the output S7 = "H" is output through the OR gate 73.
To the clock terminal CK of the flip-flop 71.

The flip-flop 71 at the rising edge of this S7, the latches "H" of the output S5 in EXOR gate 72, the output Q = "H", ^Q - = becomes "L". As a result, the AND gate 81 of the clock selector 8
Is turned off and the AND gate 82 is turned on. Instead of the clock CKA that has been output until then, the clock CK
B is output as the working clock CKO.

In the above description of the operation, the clock CKA is used.
The switching operation in the case where is output as the current clock CKO has been described, but the switching can be performed in the same manner when the clock CKB is the current clock CKO.

As an example, FIG. 7 shows a time chart of the automatic switching operation in the case where the clock CKB is cut off in the "L" level fixed state. In this case, the clock CK
The operation is the same as in the case of [II] described above except that the clock CKB disconnection detection unit 2 detects that B has disconnected.

[0039]

According to the automatic clock switching system and the automatic clock switching circuit of the present invention, when the current clock is disconnected, the disconnection level state is detected, and the timing coincides with the disconnected level state. Since the clock is automatically switched to the spare clock at the position, the clock can be switched without causing a hazard.

[Brief description of drawings]

FIG. 1 is a principle configuration diagram of an automatic clock switching circuit according to the present invention.

FIG. 2 is an explanatory diagram of the occurrence of a hazard at the time of clock switching and its preventive measures.

FIG. 3 is a circuit diagram of one embodiment of an automatic clock switching circuit according to the present invention.

FIG. 4 is a time chart of a manual switching operation when the clock is normal.

FIG. 5 is a time chart of an automatic switching operation when the clock CKA is cut off in the “L” level fixed state.

FIG. 6 is a time chart of an automatic switching operation when the clock CKA is disconnected in the “H” level fixed state.

FIG. 7 is a time chart of the automatic switching operation when the clock CKB is disconnected in the “L” level fixed state.

FIG. 8 is a circuit diagram showing an example of a conventional clock loss detection circuit.

FIG. 9 is a time chart of the operation of the conventional clock loss detection circuit.

FIG. 10 is a circuit diagram showing an example of a conventional clock switching circuit.

FIG. 11 is a time chart of the operation of the conventional clock switching circuit.

[Explanation of symbols]

 1 clock CKA disconnection detection unit 2 clock CKB disconnection detection unit 3 automatic clock switching display unit 4 disconnection clock “H” level fixed detection unit 5 clock “H” level coincidence detection unit 6 clock “L” level coincidence detection unit 7 clock switching control Part 8 Clock selector

Claims (2)

[Claims] 1. An automatic clock switching method in an electric device, comprising two clocks, one of which is used as a current clock and the other of which is used as a backup clock when the current clock is cut off. At the same time as the disconnection detection, the disconnection level state is also detected, and the standby clock is automatically switched to the standby clock at the timing position where the standby clock matches the disconnection level state of the disconnected current clock. Automatic clock switching method. 2. An automatic clock switching circuit in an electric device, comprising two clocks, wherein one of the clocks is used as a working clock and the other clock is used as a backup clock, and the occurrence of the first clock interruption is monitored. A first clock loss detection unit, a second clock loss detection unit that monitors the occurrence of a second clock loss, and an automatic clock that generates an automatic clock switching signal based on the loss detection signals of the two loss detection units The switching display section, the disconnection clock “H” level fixed detection section for detecting whether or not the active clock is disconnected in the “H” level state, and the disconnection clock “H” level fixed detection section A clock "H" level coincidence detection unit for detecting a timing position at which the backup clock becomes "H" level when fixed is detected, and the disconnection clock "H" A clock "L" level coincidence detection unit for detecting a timing position at which the backup clock becomes "L" level when the level fixation detection unit does not detect "H" level fixation, and an automatic clock switching display unit. A clock switching control unit that outputs a switching command signal at a timing position where no hazard occurs based on the clock switching signal and the level matching signals of the clock "H" level matching detection unit and the clock "L" level matching detection unit; An automatic clock switching circuit comprising: a clock selector that switches a clock from a working clock to a backup clock based on a switching command signal from the clock switching control unit.