JPS62138914A - Clock circuit - Google Patents

Abstract

PURPOSE:To reduce a phase shift in clock switching by monitoring a clock from the opposite high frequency clock source mutually, selecting the clock from either block source according to the monitoring result, and then dividing its frequency and outputting the result. CONSTITUTION:A switching circuit 4a is controlled with the output (c) of a clock break detecting and holding circuit 3a to outputs the other clock when the clock is normal or its clock when abnormal. When the frequency division ratio of a frequency dividing circuit 5a is set to 1/2, the output (d) of the switching circuit 4a shifts in phase by a 1/4 period owing to switching at the time of a break of a clock (a), but the output (e) of the frequency dividing circuit 5a is out of phase only by 1/8 as much as a period T'. For the purpose, the rate of the clock is increased and the frequency division ratio is also increased to obtain a clock circuit output (e) which has a small phase shift.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a clock circuit that can output a clock with a small phase shift when switching clocks.

[Background of the invention]

As far as getting a highly reliable clock.

For example, as described in Japanese Patent Application Laid-Open No. 60-93819,
A circuit that switches between two clock inputs is known. This means that when the first clock S1 from the first tarlock input terminal 1 is continuously obtained as shown in FIGS. 4 and 5, the output signal S2 of the detector 3 is at the 0" level. Therefore, the RS flip-flop 6 is placed in the set state.In other words, in this case, the first clock S1 is outputted via the delay circuit 4, the AND gate 7, and the OR gate 8, and then becomes the output clock S. , and is output to the output terminal 13. However, if the first clock S1 cannot be obtained, the output signal S
2 becomes the "1" level, and on the condition that the first clock S from the delay circuit 4 is at the "0" level, the RS flip-flop 6 is placed in a reset state, and its Q output is kept constant by the delay circuit 9. It is designed to be delayed by a time d. Therefore, the AND gate 10 detects that the second clock S4 from the second clock input terminal 2 is at the "0" level after a certain period of time d has elapsed since the RS flip-flop 6 was placed in the reset state. If the RS flip-flop 11 is set, the second clock S4 is input to the AND gate 12 and the OR gate 8.
It is designed to be output to the output terminal 13 as an output clock S5.

Switching the clock in this way may be useful in some cases, but as is clear from Figure 5, the phase shifts significantly when switching, so it is useful for digital transmission equipment that requires phase continuity, etc. It is inappropriate for

Moreover, no means for creating two clock sources as inputs, or even two mutually synchronized clock sources, is shown.

[Purpose of the invention]

It is an object of the present invention to have a small phase shift when switching clocks, to ensure the output of at least one clock even in the event of a power failure, and to be able to output two clocks that are almost phase-synchronized with each other during normal times. The purpose of this invention is to provide a clock circuit that can output signals.

[Summary of the invention]

For this purpose, the present invention provides that each taroch switching circuit including a high frequency clock source with different operating power supplies:
Each clock is monitored by the other party's high-frequency clock source, and depending on the monitoring result, the clock from one of the clock sources is selected and output in frequency-divided form.

[Embodiments of the invention]

The present invention will be explained below with reference to FIGS. 1 to 3.

First, a clock circuit according to the present invention will be described. FIG. 1 shows the configuration of an example thereof. According to this, the clock circuit consists of two clock switching circuits 6a and 6b having the same configuration. However, the operating power supplies are not the same, but are different power supplies.

As shown in FIG. 1, a clock switching circuit 6a.

6b are connected to each other so that the output of the other clock source becomes the other clock input. As a result, if the other clock is normal, the other clock is output in a frequency-divided form, and if it is abnormal, the own clock is output in a frequency-divided form.

Now, although the operations of the clock switching circuits 6a and 6b are the same, the configuration and operation of the clock circuit 6a will be explained as follows.

That is, as shown in FIG. 1, there is a switching circuit 4a that switches between the output of the clock source 1a and the output a of the other clock source 1b, and a clock disconnection detection and holding circuit 2a that detects and holds each clock disconnection.

3a, and a frequency dividing circuit 5a that divides the output d of the switching circuit 4a.
It consists of. In this case, the clock disconnection detection and holding circuit 2a is provided to output an alarm when detecting disconnection of its own clock. The switching circuit 4a is controlled by the output C of the clock disconnection detection and holding circuit 3a, and is configured to output the other clock when the other clock is normal, and output the own clock when the other clock is abnormal.

The output d of this switching circuit 4a is divided into a predetermined frequency by a frequency dividing circuit 5a, and then outputted as a clock circuit output e.

Here, the operation when the frequency dividing ratio of the frequency dividing circuit 5a is set to 172 is as shown in FIG. 2, for example.

However, the case where the clock phase is shifted by 1/4 of the period T is shown. As can be seen, the phase of the output d of the switching circuit 4a is shifted by 1/4 cycle due to switching when the clock a is cut off, but the phase of the output e of the frequency dividing circuit 5a is shifted by only 1/8 of the cycle T'. Therefore, by increasing the clock rate and increasing the 1 frequency division ratio, it is possible to obtain a clock circuit output e with a small 1 phase shift.

Therefore, the clock circuit according to the present invention outputs either clock a or b as shown in FIG. 3 depending on its operating state.

As shown in FIG. 3, when the other circuits are normal and the power is turned on at the initial stage or during troubleshooting, the clocks of the other circuits are output. Therefore, both circuits always output clocks that are almost phase-synchronized. Note that the frequency dividing circuit 5a.

For example, by adding a connection between the clocks 5b and 5b that resets each other using the carry signal of the other clock, it becomes possible to obtain two clocks whose phases are also synchronized.

〔Effect of the invention〕

As explained above, in the case of the present invention, the phase shift at the time of clock switching is small, the output of at least one clock can be guaranteed even in the event of a power failure, and moreover, the phase is almost synchronized during normal times. Since it can output two clocks, it is suitable for cases where accuracy and continuity of clocks are required, such as in digital transmission equipment.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the configuration of an example of a clock circuit according to the present invention, FIG. 2 is a diagram for explaining its operation, and FIG.
The figure shows how the clock circuit output changes depending on the operating state, and FIGS. 4 and 5 are diagrams for explaining the configuration and operation of the conventional clock switching circuit. la, lb... clock source, 3 a, 3 b-
Clock disconnection detection holding circuit, 4a, 4b... switching circuit. 5a, 5b... Frequency divider circuit, 6a, 6b... Clock switching circuit

Claims (1)

[Claims] 1. In each clock switching circuit including a high-frequency clock source with different operating power supplies, the clock from the other high-frequency clock source is monitored by a clock disconnection detection and holding circuit, and depending on the monitoring result, one of the clock sources is switched. 1. A clock circuit characterized by a configuration in which a clock is selected by a switching circuit, and the clock is divided by a frequency dividing circuit and outputted in the form.