KR100332205B1 - Clock signal monitor circuit - Google Patents

Abstract

PURPOSE: A clock signal monitor circuit is provided to monitor whether an output clock signal is abnormal and whether a phase error is generated. CONSTITUTION: A clock signal monitor circuit includes the first clock signal detecting part(10), the second clock signal detecting part(30), and a phase detecting part(20). The first clock signal detecting part(10) detects whether the first output clock signal(CLKA) is abnormal or not, and the second clock signal detecting part(30) detects whether the second output clock signal(CLKB) is abnormal or not. The phase detecting part(20) detects a phase difference between the first output clock signal(CLKA) and the second output clock signal(CLKB).

Description

Clock signal monitor circuit

The present invention provides a clock monitor for monitoring an abnormality of the reference clock in an electronic circuit system (hereinafter referred to as a system) that uses a reference clock multiplexed through multiplexing means (for example, a plurality of commonly connected butters). In particular, the present invention relates to a circuit for monitoring abnormality of a reference clock (hereinafter referred to as an output clock signal) multiplexed with a reference clock (hereinafter referred to as an input clock signal) input to the system.

As is well known, a reference clock is a clock that is a reference for various clocks used in system operation, and the various clocks operate in synchronization with the reference clock. This plays a similar role in communication with other systems, and the various clocks mean clocks made by changing the reference clock or made by separate clock generating means.

Therefore, whether or not the reference clock is stable is the biggest factor in determining the stability of the system. Therefore, the reference clock should be supplied most stably, and it is necessary to continuously detect the abnormality of the operation and to deal with it quickly according to each situation.

1 shows an example of a conventional clock monitoring apparatus used for a control board (PCB BOARD ASSEMBLY) that is responsible for network management and relay of a data transmission bus as part of a PCS (PERSONAL COMMUNICATION SERVICE).

In FIG. 1, the input clock signal CLKIN, which is the reference clock, is doubled into a first output clock signal CLKA and a second output clock signal CLKB by a first buffer BUF1 and a second buffer BUF2. The operation of the conventional clock monitor circuit illustrated in FIG. 1 will now be described.

First, connect to the outputs of D flip flop 1 (DFF1), D flip flop 2 (DFF2), and D flip flop 3 (DFF3) in the initial reset state, and the output terminal of the counter. The outputs (OUT2), (OUT3), (OUT5), and (OUT4) of the NAND gate NAND become "1" which is a high state.

Subsequently, when a reset signal (/ RESET: indicates a reversed signal by prefixing "/" with a character below) to the AND gate AND, D flip-flop 1 (DFF1), D flip-flop 2 (DFF2), and D Flip-flop 3 (DFF3) is operated to operate the counter (COUNTER).

That is, when the reset signal / RESET is applied while the initial value "1" of D flip-flop 2 (DFF2) is applied, the output value of the AND gate AND becomes "1", and thus the input clock signal. At the rising edge of CLKIN, the output of D flip-flop 1 (DFF1) becomes "0" which is a low state.

Further, when "0" is output from the D flip-flop 1 (DFF1), the value of (OUT3) that is the output of the D flip-flop 2 (DFF2) at the next falling edge (FALLING EDGE) of the input clock signal CLKIN is " 0 ".

Then, the value of OUT1, which is the output value of the AND gate AND, becomes "0", and the counter COUNTER which makes this value of OUT1 the input of the CLEAR terminal is cleared.

However, if the input clock signal CLKIN is not applied for some reason, the value of the counter COUNTER is increased by the (REFC) signal input through the clock terminal CLK, and eventually, the NAND gate NAND. The output value of becomes "0" which is a low state, indicating that the input clock signal CLKIN is not normal. Here, the (REFC) signal is a system reference signal (SYSTEM REFERENT CLOCK), and uses twice or more times the input clock signal.

That is, when the input clock signal CLKIN is normally input, the counter COUNTER is cleared every clock to maintain "1" in which the output value of the NAND gate NAND is high, but the input clock signal CLKIN If an error occurs and is not input for a predetermined time (during the set time required for the output value of the NAND gate to become "0"), a value of "0" which is a low state is output to indicate that an error has occurred.

Therefore, it is possible to know whether the input clock signal CLKIN is abnormal from the output value of the NAND gate NAND.

However, in the conventional clock monitoring apparatus as described above, when the output clock signal is not normal due to an abnormality in a circuit element (buffer) that multiplexes the reference clock due to monitoring only the input clock signal, or other causes. There is a problem in that it cannot be detected, so that the output clock signal cannot be guaranteed, and a large phase difference (eg, 180 ^O ) between the multiplexed output clock signals cannot be detected.

An object of the present invention is to solve the conventional problems as described above, and in particular, to provide a "clock signal monitor circuit" that can monitor whether the output clock signal is abnormal and whether the phase difference occurs.

Configuration 1 of the "clock signal monitor circuit" of the present invention for achieving the above object is a clock signal monitor circuit of an electronic circuit system which multiplexes an input clock signal into a plurality of output clock signals through multiplexing means, The clock signal monitor circuit includes a plurality of clock signal detectors for detecting and outputting an abnormality of the output clock signal by detecting and comparing the output clock signal propagated by the multiplexing means at the rising edge and the falling edge of the input clock signal; ; The present invention is characterized in that it comprises a phase detection unit for detecting and outputting a phase difference by detecting and comparing two or more output clock signals at a rising edge or a falling edge of the input clock signal.

The clock signal detecting unit includes a first D flip-flop, a second D flip-flop, and an exclusive OR gate (hereinafter referred to as an XOR) gate, and includes a data input terminal of the first D flip-flop. The data input terminal of the 2D flip-flop is commonly connected to the output clock signal, the reset terminal of the 1D flip-flop and the set terminal of the 2D flip-flop are commonly connected to the reset signal, and connected to the clock input terminal of the 1D flip-flop. An input clock signal is connected, an inverted input clock signal is connected to the clock input terminal of the second flip flop, and the output terminals of the first and second flip flops are input to the XOR gate.

The phase detection unit may include an exclusive NOR gate (hereinafter referred to as XNOR) for inputting two or more output clock signals; The output terminal of the XNOR gate is connected to the data input terminal, the set terminal is connected to the reset signal, and the D flip-flop is connected to the clock input terminal.

Configuration 1 of the present invention " clock signal monitor circuit " is configured to poll an output clock signal propagated by multiplexing means for multiplexing the input clock signal with the rising edge of the input clock signal using two D flip-flops and an XOR gate. By detecting and comparing each edge at the edge, the signal for the presence or absence of the output clock signal is output, as well as comparing two or more output clock signals to detect and output a phase shift.

On the other hand, the configuration 2 of the "clock signal monitor circuit" of the present invention is a clock signal monitor circuit of an electronic circuit system which uses an input clock signal multiplexed into a plurality of output clock signals through multiplexing means. A plurality of clock signal detection units for detecting and outputting an abnormality of the output clock signal by detecting and comparing the output clock signal propagated by the multiplexing means at the rising edge and the falling edge of the input clock signal; A phase detection unit for detecting and outputting a phase difference by detecting and comparing two or more output clock signals at a rising edge or a falling edge of the input clock signal; When an error occurs in any one of the plurality of output clock signals or a phase difference occurs between the output clock signals connected to each of the output terminals of the plurality of clock signal detection units and the output terminals of the phase detection unit, An abnormal signal merger for outputting a monitor signal indicating that an abnormality has occurred in the output clock signal; And a phase abnormal signal detection unit connected to each output terminal of the plurality of clock signal detection units and an output terminal of the output terminal of the phase detection unit and outputting a signal indicating a phase difference between output clock signals. The technical configuration features.

Here, the configuration of the clock signal detection unit and the phase detection unit is the same as that in Configuration 1.

Further, when the plurality of output clock signals are all normal, the abnormal signal converging unit sets the plurality of clock signal detectors and the signals output from the phase detector to be in a high state. A detector and an AND gate that receives the output of the phase detector, and when the plurality of output clock signals are normal, the plurality of clock signal detectors and the signals output from the phase detector are in a low state. In the case of setting, the plurality of clock signal detectors and an OR gate are used as inputs to the output of the phase detector.

The phase abnormal signal detection unit may further include an OR gate configured to invert a signal output from the plurality of clock signal detection units and a signal output from the phase detection unit; The output terminal of the OR gate is connected to the data input terminal, the set terminal is connected to the reset signal, and the D flip-flop is connected to the clock input terminal.

The configuration 2 of the "clock signal monitor circuit" of the present invention detects and outputs an abnormality of an output clock signal through the clock signal detection unit, detects an abnormality of a phase through a phase detection unit, and then outputs the abnormal signal combination unit. By outputting the monitor signal merged with the abnormal signal output from each detection unit, and outputting only the signal when the phase difference occurs through the phase abnormal signal detection unit, each of whether the output clock signal abnormality and phase difference In addition to outputting a signal, the abnormality of each signal can be monitored.

1 is a circuit diagram showing a conventional input clock signal monitor circuit;

2 is a block diagram showing a configuration of Embodiment 1 of the present invention;

3A is a circuit diagram illustrating an example in which an input clock signal is doubled;

3B is a circuit diagram showing a configuration according to Embodiment 1 of the present invention;

4 is a block diagram showing a configuration according to Embodiment 2 of the present invention;

5 is a circuit diagram showing a configuration according to Embodiment 2 of the present invention.

6 is a timing diagram showing an output waveform of each unit according to the present invention;

6A is a timing diagram illustrating a case where an output clock signal is normal;

6B is a timing diagram illustrating a case where an output clock signal is abnormal;

6C is a timing diagram showing a case where a phase difference occurs between output clock signals.

<Explanation of symbols for main parts of the drawings>

10: first clock signal detector 20: phase detector

30: second clock signal detection unit 40: abnormal signal merger

50: phase abnormal signal detection unit

Hereinafter, with reference to the accompanying drawings, the configuration, operation and effect of the embodiment according to the technical concept of the present invention "clock signal monitor circuit" configured as described above in detail as follows.

Example 1

The first embodiment shows an embodiment according to the configuration 1 according to the technical idea of the "clock signal monitor circuit" of the present invention, and is for detecting a phase difference generated between an abnormality of the output clock signal and the output clock signal.

In addition, in the first embodiment, as shown in Fig. 3A, the number of output clock signals is limited to two of the first output clock signal CLKA and the second output clock signal CLKB.

First, as shown in FIG. 2, a first clock signal detection unit 10 for detecting an abnormality of the first output clock signal CLKA; A second clock signal detection unit 30 for detecting an abnormality of the second output clock signal CLKB; The first embodiment includes a phase detector 30 which detects a phase difference between the first output clock signal CLKA and the second output clock signal CLKB.

In addition, as illustrated in FIG. 3B, the first clock signal detection unit 10 is configured by using the first D flip flop DFF1, the second D flip flop DFF12, and the first XOR gate XOR11. The second clock signal detection unit 30 is configured by using the 4D flip flop DFF14, the fifth D flip flop DFF15, and the second XOR gate XOR12.

The phase detection unit 30 includes an XNOR gate XNOR and a 3D flip flop DFF13.

Hereinafter, the operation of the first embodiment configured as described above will be described.

Initial values of the first D flip-flop DFF11, the second D flip-flop DFF12, and the first XOR gate XOR11 of the first clock signal detector 10 are “0”, “1”, and “1”, respectively.

This is because the reset terminal CLR of the first D flip-flop DFF11 is connected to the reset signal / RESET of the set terminal PR of the second D flip-flop DFF12.

Thereafter, when the reset state is released by the reset signal / RESET, the input clock signal CLKIN is applied to the first D flip-flop DFF11, and the inverted input clock signal / CLKIN is inverted by the second D flip-flop ( The clock input terminals CK of the DFF12 are respectively input.

Then, the first D flip flop DFF11 and the second D flip flop DFF12 are operated by an input clock signal (or an inverted input clock signal) to generate data at the rising edge of the signal applied through the clock input terminal CK. The first output clock signal CLKA is received through the input terminal D and output.

Thereafter, the first XOR gate XOR11 receives a signal output from the output terminal Q of the first D flip-flop DFF11 and the second D flip-flop DFF12 to perform an XOR gate-specific operation function to output the same. do.

This will be described as follows.

First, since the first D flip-flop DFF11 is connected to the input clock signal CLKIN and the second D flip-flop DFF12 is connected to the inverted input clock signal / CLKIN, as a result, the first D flip-flop DFF11 The DFF11 performs the operation of receiving the first output clock signal CLKA at the rising edge of the input clock signal CLKIN and the second D flip-flop DFF12 at the falling edge of the input clock signal CLKIN.

Here, the first output clock signal CLKA is delayed by the propagation time of the first buffer BUF1, which is a multiplexing means, and always has a value of "0" at the rising edge of the input clock signal CLKIN, and always at the falling edge. A value of "1" is input to the first D flip-flop DFF11 and the second D flip-flop DFF12, respectively.

Therefore, when the first output clock signal CLKA operates normally, the output of the first XOR gate XOR11 becomes "1" which is always in a high state.

However, if the period of the first output clock signal does not have the input clock signal or is not output for some reason, the sample is sampled at the rising edge or the falling edge of the input clock signal CLKIN. The value is changed, and thus, the output value of the first XOR gate XOR11 is changed to "0", thereby indicating that the first output clock signal CLKA is not normal.

That is, when the period of the first output clock signal CLKA is increased or decreased compared to the input clock signal or there is no output, the output value of the first D flip-flop DFF11 and the second D flip-flop DFF12 is the same. As a result, the output of the first XOR gate XOR11 becomes " 0 ", thereby indicating whether there is an abnormality.

On the other hand, since the configuration and operation of the second clock signal detection unit 30 is the same as the configuration and operation of the first clock signal detection unit 10, a detailed description thereof will be omitted.

6A shows an output waveform when the output clock signal is normal, and FIG. 6B shows an output waveform when the output clock signal is not normal.

Hereinafter, the operation of the phase detector 20 will be described.

First, since the reset signal / RESET is connected to the set terminal PR of the 3D flip-flop DFF13, the initial state value is "1", and the clock input terminal CK is the input clock signal CLKIN. ) Is operated at the rising edge.

On the other hand, the XNOR gate XNOR receives the first output clock signal CLKA and the second output clock signal CLKB, and the first output clock signal CLKA and the second output clock are inherently logic. If the signal CLKB is the same, " 1 "

Therefore, when the phase of the first output clock signal CLKA and the second output clock signal CLKB is the same normal operation, "1" is output, and this signal is input to the 3D flip-flop DFF13. The signal "1" will be output.

However, when the phases of the first output clock signal CLKA and the second output clock signal CLKB are not equal to each other due to some cause, the output of the XNOR gate XNOR becomes "0" and the 3D flip-flop ( The output of DFF13) becomes "0".

Accordingly, it can be seen that a phase difference between the first output clock signal CLKA and the second output clock signal CLKB is generated from the output of the 3D flip-flop DFF13.

6C illustrates an output waveform when a phase difference occurs between the first output clock signal CLKA and the second output clock signal CLKB.

Example 2

This embodiment 2 shows an embodiment according to the configuration 2 according to the technical idea of the "clock signal monitor circuit" of the present invention, in which the abnormality of the output clock signal and the occurrence of phase difference between the output clock signal are collectively determined from the monitor signal. In addition to being known, the cause of the abnormality can be monitored.

In other words, each abnormal signal detected in Example 1 is outputted, and whether or not each abnormal signal is generated can be known from one monitor signal.

Therefore, when the monitor signal is monitored to detect whether an output clock signal is abnormal, and when it is determined that an abnormality occurs in the output clock signal, the cause of the error signal can be checked by examining each abnormal signal output terminal.

In addition, in the second embodiment, the number of output clock signals is limited to two of the first output clock signal CLKA and the second output clock signal CLKB, similarly to the first embodiment. And use the same symbols for circuit components that operate.

First, as shown in FIG. 4, a first clock signal detector 10 for detecting an abnormality of the first output clock signal CLKA; A second clock signal detection unit 30 for detecting an abnormality of the second output clock signal CLKB; A phase detector 30 detecting a phase difference between the first output clock signal CLKA and the second output clock signal CLKB; An abnormal signal converging unit for merging the signals of the first clock signal detecting unit 10, the second clock signal detecting unit 30, and the phase detecting unit 20 and outputting a monitor signal indicating that an abnormality has occurred in the output clock signal ( 40); A phase abnormal signal detector for outputting a signal indicating that a phase difference has occurred between the output clock signals from the output signals of the first clock signal detector 10, the second clock signal detector 30, and the phase detector 20 ( 50, the present Example 2 is comprised.

Hereinafter, the operation of the second embodiment will be described with reference to FIG. 5.

First, since the configuration and operation of the first clock signal detector 10, the second clock signal detector 30, and the phase detector 20 are the same as those in the first embodiment, detailed description thereof will be omitted.

On the other hand, the abnormal signal merger 40 is set to "1" which is a high state value when the outputs of the first clock signal detector 10, the second clock signal detector 30, and the phase detector 20 operate normally. When configured to output, it is configured as an AND gate, when configured to output a low state value "0" is configured as an OR gate. In the second embodiment, when the output clock signals (CLKA, CLKB) is normal, "1" ", So that it is configured to output an AND gate (AND11) having three input terminals.

The abnormal signal merger 40 has a normal first output clock signal CLKA and a second output clock signal CLKB, so that the first clock signal detector 10 and the second clock signal detector 30 are normal. And outputting a value of "1" indicating normal when the output of the phase detector 20 is "1", and wherein the first clock signal detector 10, the second clock signal detector 30, and a phase are output. When one of the detection units 20 inputs a signal "0" indicating that an abnormality has occurred in the output clock signals CLKA and CLKB, a value of "0" is output.

Therefore, by monitoring only the monitor signal which is the output signal of the abnormal signal merger 40, it is possible to know whether the output clock signals CLKA and CLKB are abnormal.

On the other hand, the phase abnormal signal detection unit 50 inverts the output signals of the first clock signal detection unit 10 and the second clock signal detection unit 30 and the output signal of the phase detection unit 20 to the An OR gate OR11 serving as an input; The fifth D flip-flop DFF15 receives an output signal of the OR gate OR11.

When the output clock signals CLKA and CLKB are normal, the phase abnormal signal detection unit 50 has a signal obtained by inverting the output signals of the first clock signal detection unit 10 and the second clock signal detection unit 30. Since the phase detection unit 20 always outputs a signal of "1" because the output signal is "1", a phase difference occurs between the output clock signals CLKA and CLKB. When the signal becomes "0", "0" is output in accordance with the logic of the OR gate.

Therefore, outputting this through the 6D flip-flop DFF16 becomes a signal indicating only the occurrence of the phase difference, and it is possible to detect whether the phase difference between the output signals is generated through this signal.

As described above, the "clock signal monitor circuit" of the present invention has an effect of being able to know whether the multiplexed clock signal is abnormal and the kind of the failure, thereby facilitating system maintenance.

Claims (2)

A clock signal monitor circuit of an electronic circuit system for multiplexing an input clock signal into multiple output clock signals through multiplexing means, A phase detector which detects at least two output clock signals on the rising edge or the falling edge of the input clock signal, compares them, detects whether there is a phase difference, and outputs a result signal; And a phase abnormal signal detector for searching for a result signal output from the phase detector and outputting a signal indicating a phase difference between an input clock signal and an output clock signal. 2. The apparatus of claim 1, wherein the phase detector comprises: an exclusive NOR gate configured to input two or more output clock signals; And a D flip-flop which connects an output terminal of the exclusive NOR gate to a data input terminal, a set terminal to a reset signal, and an input clock signal to a clock input terminal.

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