KR100196723B1 - Frequency generating apparatus - Google Patents

Abstract

The present invention relates to a frequency generating device capable of outputting a constant frequency even if any one input frequency is influenced by an external influence by duplexing the input frequency, and by a predetermined time by the first input frequency and the delay element. A first variable delay unit configured to receive the delayed first input frequency and variably delay or output the first input frequency in response to the first control signal; A second variable delay unit configured to receive a second input frequency delayed by a predetermined time by the second input frequency and the delay element and to variably delay or output the second input frequency in response to the second control frequency; A phase comparison unit comparing the output frequencies of the first and second variable delay units with a phase difference between the two frequencies so that a phase difference becomes less than a predetermined level; A switch switching unit for receiving an output frequency of the first and second variable delay units and automatically switching a switch when an abnormality occurs in one input frequency so that an input frequency having no abnormality is constantly output; And a CPU (Centrl Process Unit) for detecting the output frequency of the phase comparison unit and the output frequency of the switch switching unit to generate first and second control signals.

Description

Frequency generator

1 is a block diagram of a frequency generating device according to the present invention.

2 is a, b, c is a view for explaining a variable delay unit according to the present invention.

3 is a, b, c is a view for explaining a phase comparison unit according to the present invention.

4 is a, b, c is a view for explaining a switch according to the invention.

5 is a, b, c, d is a view for explaining a frequency abnormality detection circuit according to the present invention.

6 is a diagram illustrating a logic circuit of a switch delay (SW-DELAY) according to the present invention.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a frequency generating device, and more particularly, to a frequency generating device capable of constantly outputting a frequency even if any one input frequency is affected by an external influence by duplexing two input frequencies.

In general, accurate timing is required for high-speed digital network communications.

However, in the high speed digital communication, when the input frequency is abnormal due to external influence among devices that need to generate the frequency at the correct timing, the sensitivity is poor at the receiving side due to the timing mismatch. In particular, when a problem occurs in a device that supplies a synchronization signal and the phase of the supplied synchronization signal is delayed, decoding on the receiving side becomes difficult and only noise occurs.

For example, when a problem occurs in a device that supplies a synchronization signal in a communication between a base station and a control station of a wireless communication network using a code division multiple access (CDMA), etc., it is difficult to correctly decode the receiving side, and confusion of many subscribers is expected. If is continued, there is a problem that only the noise is generated on the receiving side, and the reception becomes impossible.

An object of the present invention is to duplicate the input frequency to solve the above problems, when one input frequency is abnormal, by generating the output frequency by the other input frequency to generate a stable frequency continuously The present invention provides a frequency generating device.

The frequency generating device of the present invention for achieving the above object receives the first input frequency and the first input frequency delayed by a predetermined time to the delay element to variably delay the first input frequency in response to the first control signal. A first variable delay unit which is output or disabled; A second variable delay unit configured to receive a second input frequency delayed by a predetermined time by the second input frequency and a delay element, and variably delay or output the second input frequency in response to the second control frequency; A phase comparison unit for comparing the output frequencies of the first and second variable delay units and outputting a phase difference between the two frequencies so that the phase difference becomes less than a predetermined level; A switch switching unit for receiving an output frequency of the first and second variable delay units and automatically switching the switch when an abnormality occurs in one input frequency so that an input frequency having no abnormality is constantly output; And a central process unit (CPU) configured to detect an output frequency of the phase comparator and an output frequency of the switch switching unit to generate first and second control signals.

Hereinafter, the present invention will be described in detail with reference to the accompanying drawings.

1 is a block diagram of an apparatus for generating a frequency according to the present invention, and includes a CUP 10, first and second variable delay units 20 and 30, a phase comparator 40, and a switch switching unit 50. do.

Looking at the operating characteristics of each block in the configuration as described above, the first variable delay unit 20 is a first input in which the first input frequency (1) of 10 MHz is delayed by a time of 3.5 Nano Second predetermined by the delay element In response to the first frequency (DIN1) and the first control signal (B) which is the CPU CON1 output from the CUP 10, the first input frequency (1) is variably delayed and outputted or disabled. .

Similarly, the second variable delay unit 30 is also delayed by a time of 3.5Nano Second predetermined by the second input frequency (1) of 10 MHz and the delay element, and receives the second input frequency (2) by the CPU CON2. In response to the second control signal D, the second input frequency D1 is variably delayed and output or disabled.

The phase comparator 40 compares output frequencies (ma and bar) of the first and second variable delay units 20 and 30 and compares the satellite difference between the two output frequencies (ma and bar) to the CPU 10. The outputs of the first and second variable delay units 20 and 30 are output so that the phase difference is controlled to be 3.5 Nano Second or less. The switch switching unit 50 receives the output frequencies (e, bar) of the first and second variable delay units 20 and 30 and automatically switches when an abnormality occurs in the input frequency (10 MHz-IN1,2). Switch over to output constant 10MHz frequency.

FIG. 2A is a block diagram in which the first variable delay unit 20 or the second variable delay unit 30 is embodied. The variable delay control unit 22, the variable delay output unit 24, and the phase delay element 26 are illustrated in FIG. It is configured.

In the above configuration, the variable delay control unit 22 and the variable delay output unit 24 are enabled or disabled by the data enable signals A, B, H, and I, and the variable delay control unit 22 is used. ) Is synchronized by the 50 MHz flip-flop synchronization signal (D), and the output is initialized by the clear frequency (E). In addition, the variable delay output unit 24 uses a delay element 26 having a 3.5Nano Second delay value externally to minimize the delay step. It has a delay value and outputs 30 steps by combining two 16-bit mux, and controls it through the variable delay control section 22 according to the control data value C given by the CPU 10. Do it.

FIG. 2B is a logic circuit diagram of the variable delay unit. First and second D flip-flops DFF2-1 and DFF2 outputting first and second data enable signals A and B in response to an input frequency of 10 MHz. -2) and the first OR gate ORS2-1 for outputting the first test signal TEST1 by ORing the outputs of the first and second D-flip flops DFF2-1 and DFF2-2. Third and fourth D flip-flops DFF2- which slightly delay the output signals of the first and 22D flip-flops DFF2-1 and DFF2-2, respectively, in response to the flip-flop synchronization signal D, respectively. 3, DFF2-4, the output signal of the first OR gate OR1 is the clock signal CLK, and the ground is the enable signal EN, and the first to fourth data values SELO, 1, Delay value selecting means (74437-ams) for outputting the first to fourth output values (Q1-Q4) according to 2,3), and outputs of the third and fourth D flip-flops (DFF3-3, DFF3-4). In response to the signal, the ground signal is delayed slightly. Fifth and sixth D-flop flops DFF2-5 and DFF2-6 for outputting a signal TEST2 and 3, an output signal of the third D-flip flop DFF2-3, and the sixth D-flip flop The second OR gate ORS-2 and the fourth D flip-flop DFF2 that logically add the output signal of the DFF2-6 to output the preset PRN signal of the fifth D flip-flop DFF2-5. And a third OR gate for outputting the output signal of -4) and the output signal of the fifth D flip-flop DFF2-5 to output the preset PRN signal of the sixth D flip-flop DFF2-6. OR2-3) and the output value of the fifth and sixth D-flip flops DFF2-5 and DFF2-6 as the first and second enable signals ENABLE1 and ENABLLE2, and the delay value selecting means 74437- and a delay unit DELAY100 for delaying and outputting an input frequency of 10 MHz according to a selection value given by ams).

FIG. 2C is a detailed circuit diagram of the delay unit DELAY100 shown in FIG. 2B and includes two first and second 216-bit multiplexers (MUX1 and MUX2) to enable the first and second enable signals ENABLE1, According to ENABLE2) and the given data values (SELO, 1,2,3), the output values are respectively determined by the delay values of the inputs (10 MHz_IN, DELAY35), and the output first and second multiplexers (MUX1), respectively. It is shown that the output signal of MUX2 is ORed so that the 10 MHz signal is delayed output (10 MHz_OUT).

FIG. 2d is a diagram illustrating signals input to the variable delay units 20 and 30 and corresponding output waveforms. FIG. 2d is a view showing a data value (SELO, 1, 2, 3) at a time of 281 μs where 0000 (①). When comparing the output signal (10MHz_OUT) and the output signal (10MHz_OUT) appearing at 581 Hz when the data values (SELO, 1,2,3) are 0001 (②), after two cycles from 581 Hz It shows that the output signal appears at 784.5㎱, which is 3.5㎱ delayed from 781㎱. In other words, it can be seen that a delay of 3.5 ms occurs when the data changes by one bit.

3a, b, and c are flowcharts, logic circuits, and waveform diagrams for explaining the operation of the phase comparator 40. Rising edges of two input frequencies 10 MHz-IN1,2 of 10 MHz are shown. The interval is counted by a 4-bit counter using a 100 MHz clock frequency and read by the CPU. The CPU detects the moment when the READ-RDY frequency becomes high as shown in FIG. If (S1) high occurs (Fig. 3a), the signal of the two input frequencies (10MHz-IN1,2) is first inputted as a SIGN-CHECK frequency to determine high and low (S2). Thus, the high input frequency (10 MHz-IN1 / 10-MHz-IN2) is read (S3), and the low input frequency (10 MHz-IN1 / 10 MHz-IN1) is cleared (S4). Here, the second input frequency (10 MHz-IN2; 10 MHz-2 in 3b, c) for the first input frequency (10-MHz-IN1; denoted 10-MHz-1 in FIGS. 3b and c). If the high), the second input frequency (10MHz-IN2) is ahead, if the low indicates that the second input frequency (10MHz-IN2) is slow.

4A is a logic circuit diagram of the switch switching unit 50 according to the present invention, in which the first and second input frequencies 10 MHz-IN1 / 10 MHz-IN2 are respectively converted into a 100 MHz clock frequency (100 MHz-IN). First and second error check units (error-chk1 and error-chk2) for error checking; A three-input first NAND gate gate (NaND4-1) for receiving a first control signal (CPU-CTL1) generated from a CPU, an output signal of the first error check unit (error-chk1), and a latched signal; The second control signal CPU-CTL2 generated by the CPU, the output signal of the second error check unit error-chk2, and the three-input first NAND gate NAND4-1 output signal are outputted and output the latched signal. A three-input second NAND gate NAND4-2; First and second outputting states of the first and second input frequencies FREQ1 and 2-STATE, respectively, by inverting the outputs of the three-input first NAND and second NAND gate gates NAND4-1 and 2, respectively. Second inverters NOT4-1 and NOT4-2; A first end gate (AND4-1) for inputting an output signal of the first inverter (NOT4-1) and a first input frequency (10MHz-IN1); A second end gate AND4-2 which receives the output signal of the second inverter NOT4-2 and a second input frequency 10MHz-IN2; The first and second gates AND4-1 and 2 output the logical OR of the first OR gate OR4-1 to output the switch output SW-OUTPUT.

4b and c show waveform diagrams of each frequency generated when each input frequency is normal and when an abnormality occurs. In FIG. 4b, when two input frequencies are normal, two input frequencies 10MHz-IN1 and When 10MHz-IN2 is normally input, it can be seen that FREQ2-STATE is high and FREQ1-STATE is low due to the faster frequency among CPU-CTL1 and CPU-CTL2 controlled by the CPU. That is, in the current waveform, FREQ2-STATE goes high, indicating that 10 MHz-IN2 is output. Here, the two input frequencies are synchronized to the variable delay section with a phase of 3.5 Nano Second or less.

If an abnormality occurs in the input frequency in Fig. 4c, the switching occurs when the first input frequency goes one clock low in (A), and the switching when the second input frequency goes one clock low in (B). Seems. In addition (C) it can be seen that the switching when the first input frequency is high, and in (D) it can be seen that the switching when the second input frequency is high. It can be seen that the combined frequency of the two input frequencies is output.

FIG. 5A is a logic circuit diagram showing an error check unit (for example, error-chk1) shown in FIG. 4A. FIG. 5A receives an input frequency of 10 MHz (10 MHz-IN) and a clock frequency of 100 MHz (100 MHz-IN). A switch delay (SW-DESAY) for delaying a switch operation with a delayed output signal and outputting the first and second output signals Q and Q1 and the inverted signals / Q and Q1 of the first and second outputs. A first OR gate OR5-1 that outputs the first test signal TEST1 by ORing the inverted signal / Q of the first output and the second output signal Q1, and the first output signal Q and The first NOR gate NOR5-1 outputting the second test signal TEST2 by performing an NOR operation on the inverted signal / Q1 of the second output and the output signal of the first OR gate OR5-1 and 10. A second OR gate OR5-2 for outputting a third test signal TEST3 by ORing an input frequency of 10 MHz-IN and 10 MHz with an output signal of the first NOR gate NOR5-1. Negative input frequency of 10MHz-IN The first NAND gate NAND5-1, which is multiplied to output the fourth test signal TEST4, the output signal of the second OR gate OR5-2, and the output signal of the first NAND gate NAND5-1. It is shown that it is composed of a first end gate (AND5-1) that delivers an output signal by AND.

FIG. 5B is a waveform diagram showing that the enable frequency is high when the input frequency is normal, and the output is generated high. FIG. 5C and FIG. 5C are outputs from the respective parts A and B where an abnormality of the input frequency occurs. The waveform diagram shows that OUTPMT) goes low.

FIG. 6 is a detailed circuit diagram of a switch delay (SW-DESAY) part of the elecheck portion shown in FIG. 4a, which first delays the input frequency 10 MHz-IN in response to a 100 MHz clock signal. A plurality of D-flip flops DFF6-1-11 for outputting the signal Q, a first inverter NOT6-1 for inverting and outputting the output signals of the D-flip flops DFF6-11; And a second inverter (NOT6-) which inverts and outputs an output signal of the 12D flip-flop (DFF6-12) and the 12D flip-flop (DFF6-12) for delaying the first output signal by one more clock. 2) is shown.

As such, the present invention duplicates an input frequency so that one frequency is enabled and the other frequency is disabled, and when an abnormality occurs in the input enabled frequency, the disabled frequency is enabled. By disabling the frequency at which the abnormality occurs, a stable frequency can be generated at the time of frequency generation.

Therefore, the present invention can generate the frequency continuously and stably at the time of frequency generation, and when used for digital high-speed communication, etc., it is possible to remove the noise caused by the occurrence of an abnormal input frequency.

Claims (2)

A first variable delay unit that receives the first input frequency and the first input frequency delayed by a predetermined time by the delay element and variably delays or outputs the first input frequency in response to the first control signal; A second variable delay unit configured to receive a second input frequency delayed by a second input frequency and a delay element by a predetermined time, and to variably delay or output the second input frequency in response to the second control frequency; A phase comparator for comparing the output frequencies of the first and second variable delay units and outputting a phase difference between the two frequencies so that the phase difference becomes less than a predetermined level; A switch switching unit for receiving an output frequency of the first and second variable delay units and automatically switching a switch when an abnormality occurs in one input frequency so that an input frequency having no abnormality is constantly output; And a central process unit (CPU) configured to detect an output frequency of the phase comparator and an output frequency of the switch switching part to generate first and second control signals. The variable delay unit of claim 1, wherein the variable delay unit is enabled by a data enable signal and determines and outputs a delay value of an input frequency according to a plurality of data values given by the CPU in response to a synchronization signal; A phase delay device for outputting a delayed input frequency by a predetermined time; And a variable delay output unit configured to be enabled or disabled by a data enable signal and to delay and output the delay value of the phase delay element according to the delay value determined by the variable delay control unit. .