KR950007458B1 - Clock syncronous circuit - Google Patents

Abstract

The precise clock synchronization circuit reduces the synchronization time error to a half clock period at asynchronous signal output mode. The circuit includes: (a) an edge detector which detects the edge of the clock signal; (b) the first synchronization circuit which delays the asynchronous data to synchronize with the edge detect signal; (c) the second synchronization circuit which shapes the first synchronization data to the second synchronization data according to the edge detect signal; (d) a transition detector which detects the transition state of the synchronization data using the second synchronization data signal and the first inverted synchronization data.

Description

Clock synchronization circuit

1 is a circuit diagram of a conventional clock synchronization circuit.

2A to 2E are operational waveform diagrams for the clock synchronization circuit shown in FIG.

3 is a block diagram according to an embodiment of a clock synchronization circuit according to the present invention.

4 is a detailed circuit diagram of the clock synchronizing circuit shown in FIG.

5A to 6H are operational waveform diagrams for the clock synchronization circuit shown in FIG.

* Explanation of symbols for main parts of the drawings

10: frequency multiplication unit 20: data output unit

30: clock control unit 40: frequency division unit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clock synchronization circuit in a digital signal processing circuit, and more particularly, to a clock synchronization circuit for clock synchronization of an asynchronous signal including a jitter component during edge detection.

Conventionally, the clock synchronizing circuit for the input data is composed of the de-flip flop 1 as shown in FIG.

As shown in FIG. 2A, the clock signal CK is input to the clock terminal of the de-flop flop 1, and the input data Din is input to the input terminal D of the de-flop flop 1 from FIGS. When the input data Din is input in any section of T _A when it is input as shown in FIG. 2d, the output of the de-flip-flop 1 is input as shown in FIG. 2e. It is output at the first rising edge of the post clock signal (Figure 2a).

Here, the range of t _Q (Quantizing Error) of output data is

0 <t _Q <1 period of clock signal CK... … … … … … … … … … … … … … … … … … (One)

Becomes

As shown in Equation (1), the range of this t _Q is not constant as one cycle in the maximum clock signal, so that there is a problem that precise control cannot be performed during edge detection.

Accordingly, an object of the present invention is to provide a clock synchronization circuit capable of precise control by reducing the synchronization time error to one half of a clock period when outputting an asynchronous signal in synchronization with a clock synchronization in an edge detection circuit.

In order to achieve the above object, a clock synchronization circuit according to the present invention is a clock synchronization circuit for forming an asynchronous data signal into a synchronous data signal according to a clock signal: generating an edge detection signal by detecting an edge of the clock signal. Edge detection means; First synchronous means for forming and outputting the asynchronous data signal as a first synchronous data signal in accordance with the edge detection signal; And second synchronizing means for forming and outputting the first synchronizing data signal as a second synchronizing data signal according to the edge detection signal to reduce the synchronization time error of the asynchronous data signal within a half period of a clock signal. I am doing it.

Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the clock synchronization circuit according to the present invention.

3 is a block diagram according to an embodiment of a clock synchronization circuit according to the present invention.

According to the configuration of the present invention, the frequency multiplier 10 multiplies the frequency of the input clock signal CKin and the input clock Din is synchronized with the multiplied clock signal of the frequency multiplier 10 to synchronize the input clock. A data output unit 20 for outputting a synchronization time error range corresponding to one-half cycle of the signal, a frequency divider 40 for dividing a frequency corresponding to the embedded frequency of the frequency multiplier 10, Input the data output from the data output unit 20 and the output of the frequency divider 40 so that the phase of the output clock signal of the frequency divider 40 is always output in a constant form at the time of the output data Dout. The clock control section 30 controls the output of the frequency division section 40 to be inverted or non-inverted.

FIG. 4 is a detailed circuit diagram of the clock synchronization circuit shown in FIG.

Referring to FIG. 4, the frequency multiplier 10 includes first to third inverters 11-13 for inverting the incoming input clock signal CK in, input clock signals CK in, and third inverter. The negative exclusive logic sum element 14 which performs negative exclusive logic on the output of (13).

The data output unit 20 includes a first di flip-flop 21 connected to an input data Din of the data input terminal D, and a clock terminal of which is connected to an output terminal of the negative exclusive logic element 14; The data input terminal D is connected to the non-inverting output terminal YQ of the first di flip-flop 21, and the clock terminal is connected to the output terminal of the non-exclusive logic device 14. ) Here, the first di flip-flop 21 may be a first synchronous means, the second di flip-flop 22 may be a second synchronous flip flop 22.

In the clock controller 30, the first input terminal is folded to the non-inverting output terminal YQ of the second di flip-flop 22, and the second input terminal is the inverted output terminal NQ of the first di flip-flop 21. ) And the first input terminal are the AND gate 32 connected to the output terminal of the NAND gate 31. The clock controller 30 may be a transition detection means.

In the frequency divider 40, the data input terminal D is connected to the output terminal of the AND gate 32, the clock terminal is connected to the output terminal of the non-exclusive logic device 14, and the non-inverted output terminal YQ. The output clock signal CKout is outputted as a signal, and the inverted output terminal NQ is a third di flip-flop connected to the second input terminal of the AND gate 32. The frequency divider 40 may be a clock output means.

Next, the operation of FIG. 4 will be combined with the waveform diagrams shown in FIGS. 5A to 6H.

According to FIG. 4, input data Din as illustrated in FIG. 5A is input to the first di flip-flop 21.

At this time, the input clock signal CKin as shown in FIG. 5B is input to the frequency multiplier 10.

In the negative exclusive logic element 14 of the frequency multiplier 10, the negative clock logic inverted by the input clock signal (Fig. 5b) and the inverted clock signal through the first to third inverters 11-13 is shown in Fig. 5c. A clock signal of which the frequency is doubled as shown in the drawing is output to the first di flip-flop 21.

In the first di flip-flop 21, the signal shown in FIG. 5d is shifted at the rising edge of the first clock signal at the transition time of the input data according to the clock signal (FIG. 5C) multiplied by the input data (FIG. 5A). Is output.

In the second di flip-flop 22, a clock signal multiplied by the clock signal (figure 5c) delays the output of the first di flip-flop 21 shown in FIG. At the second rising edge of the transition point, the final data is lowered and output as shown in FIG. 5f.

In the NAND gate 31, when the output data Dout shown in FIG. 5F and the inverted output (FIG. 5D) of the first D flip-flop 21 are negatively logically multiplied, the signal shown in FIG. 5E is output. . That is, the output of the NAND gate 31 is maintained at the ″ low ″ level from the falling edge of the output of the first di flip-flop 21 to the falling edge of the output data Dout.

In the AND gate 32, the output of the NAND gate 31 and the inverted output of the third di flip-flop 40 are logically multiplied and input again to the third di flip-flop 41.

In this case, the output of the AND gate 32 is affected by the inverted output of the third di flip-flop 40, and the initial inverted output of the third di flip-flop 40 is in the form of a ″ high ″ or ″ low ″ signal. It can be entered in two ways.

Accordingly, in the third di flip-flop 40, the output of the AND gate 32 is input in accordance with the multiplied clock signal of the frequency multiplier 20 (FIG. 5C), as shown in FIGS. 5G and 5H. It can be output as well.

Here, the output clock output in synchronization with the transition time of the output data will be described in more detail.

1) As shown in FIGS. 5A to 5F, the output clock signal CKout has the same phase as the input clock signal CKin and the output data Dout is at the ″ low ″ level of the input clock signal CKin. When the transition occurs, as shown in FIG. 5G at the transition time t11 of the output data Dout, when the output clock signal CKout is a falling edge, the output signal is not reversed.

That is, since the transition time point t1 of the output data is a portion where the output clock signal CKout is originally "low", it is output as it is, without being inverted.

2) As shown in FIGS. 5A to 5F, the output clock signal CKout has a 180 ° phase difference from the input clock signal CKin, and the transition time t11 of the output data Dout is the input clock signal CKin. Transition at the ″ low ″ level of the NAND gate 31 is the same until the output of the NAND gate 31 (figure 5e) remains at the ″ low ″ level, but the output clock signal at the transition time t11 of the output data is the NAND gate 31 Shown in FIG. 5h on the basis of the transition time t11 because the data toggled by the third D flip-flop 40 is continuously output after the ″ low ″ is maintained by the output of As described above, the output clock signal CKout is inverted and output.

3) As shown in FIGS. 6A to 6E, the output clock signal CKout transitions at the ″ high ″ level of the input clock signal CKin without a phase difference from the input clock signal CKin. In this case, the output of the NAND gate 31 is the same until the output (Fig. 6e) is maintained at the ″ low ″ level, but the output clock signal CKout is the output of the NAND gate 31 at the time t12 of the output data Dout. As shown in FIG. 6G on the basis of the transition time point t12, since the data continuously toggled by the third D flip-flop 41 is output after the ″ low ″ is maintained by The clock signal CKout is inverted and output.

4) As shown in FIGS. 6A to 6F, the output clock signal CKout has a 180 ° phase difference from the input clock signal CKin and the output data Dout transitions at a high level of the input clock signal CKin. If the output clock signal CKout is a falling edge at the transition time t12 of the output data Dout, the output signal is not inverted as shown in FIG. 6h.

That is, the transition time point t12 is the portion where the output clock signal CKout is originally "low" and is output as it is, without being inverted.

Therefore, as shown in FIGS. 5f and 6f, the synchronization time error is always constant at 1/2 clock periods before and after the output data transition time point t11 or t12, that is, t _a , t _b , t _c , t _d. The synchronization time error can be reduced to / than the conventional method with <t _Q </ clock period.

In summary, the present invention detects whether the output clock signal is at the high level or the low level at the time of transition of the asynchronous signal, and if the high level continues after the time of transition of the asynchronous signal, the output clock signal remains in its current state. If it is maintained but the low level is maintained, the output clock signal is inverted and output.

When output data and output clock signal, which are synchronized signals, are output in this way, there is a synchronization time error every 1/2 clock cycle, and the output data is always output at the same position and the output clock is always out of phase after output data is output. Done.

As described above, the clock synchronization circuit according to the present invention has the effect of precise control by reducing the synchronization time error during clock synchronization of the asynchronous signal during the edge detection to 1/2 input clock period.

Claims (1)

CLAIMS 1. A clock synchronous circuit for forming an asynchronous data signal into a synchronous data signal in accordance with a clock signal, comprising: edge detection means for detecting an edge of the clock signal and generating an edge detection signal; Forming and outputting the asynchronous data signal as a first synchronous data signal in accordance with the edge detection signal by using a first delay element that delays the asynchronous data signal for a predetermined period in synchronization with the edge detection signal of the edge detection means. First synchronous means; The first synchronous device according to the edge detection signal using a second delay device that outputs the first delay element in synchronization with the edge detection signal of the edge detection means to form a second synchronous data signal and outputs the second synchronous data signal. Second synchronous means for forming and outputting a data signal as a second synchronous data signal; A first logic element for detecting a period corresponding to one-half cycle of a clock signal after the transition of the first synchronous data signal by negatively multiplying the output of the second delay element and the inverted output of the first delay element; When the transition time of the second synchronous data signal transitions from the rising edge of the output clock signal by the logical multiplication of the output of the logic element and the inverted output of the clock output means, the detection signal is outputted such that the phase of the clock output means is inverted by 180 degrees. Transition detection means for inputting the second synchronous data signal and the inverted first synchronous data signal by using a second logic element output to the clock output means to detect and output a transition state of the synchronous data signal; And inputting the edge detection signal using a third delay element which inputs the output of the second logic element and outputs the clock signal having the same phase at the time of transition of the output data according to the edge detection signal. And a clock output means for outputting a clock signal having the same frequency as that of the clock signal at a transition point of the synchronous data signal according to the signal.