JPH04337924A - Synchronizing detection circuit - Google Patents

Abstract

PURPOSE:To constitute the synchronizing detection circuit with simple circuit configuration and to facilitate circuit design by composing the synchronizing detection circuit of delay circuits, logic circuits and latch circuit. CONSTITUTION:A synchronizing detection circuit 1 is equipped with serially connected delay circuits DL1 and DL2, logic circuits I1 and E1 to execute logic arithmetic for the input of the delay circuit DL1 and the output of the delay circuit DL2, and latch circuit FF1 for the output of the logic circuit E1. Namely, the output of a phase locked loop 2 is inputted to the delay circuit DL1 and the inverter I1. The phase locked loop 2 is composed of a phase comparator circuit 21, loop filter 22 and voltage controlled oscillation circuit 23. The delay circuits DL1 and DL2 are circuits to apply fixed time delay to an output A of the voltage controlled oscillation circuit 23, and the flip-flop FF1 holds input data D at the rise edge of an input signal I as a clock. Then, a signal S showing synchronism/asynchronism is obtained from an output terminal Q of the flip-flop FF1.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a synchronization detection circuit, and more particularly to a synchronization detection circuit for a phase-locked loop circuit.

0002

2. Description of the Related Art A conventional synchronization detection circuit 4, as shown in FIG. It consisted of a low-pass filter 42 that smoothes the output F, and a comparison circuit 43 that compares the output G of the low-pass filter 42 with a threshold voltage V. When the input signal I and the output E of the voltage controlled oscillation circuit 23 are logical outputs, the multiplier circuit 4
Exclusive OR may be used for 1.

Next, the operation will be explained.

FIG. 6 is a time chart showing the operation of the conventional synchronization detection circuit 4 shown in FIG. The output F of the multiplier circuit 41 is the negation of the exclusive OR of the input signal I and the output E of the voltage controlled oscillation circuit 23, and the time period in which this output F contains "0" is the input signal I and the voltage It is proportional to the phase difference with the output E of the controlled oscillation circuit 23. Therefore, the output G of the result of smoothing the output F of the multiplier circuit 41 with the low-pass filter 42
also becomes a voltage proportional to the phase difference. If a threshold voltage V corresponding to a phase difference that allows the phase-locked loop 3 to be considered to be synchronized is applied to the reference input of the comparator circuit 43, it is possible to detect synchronization-asynchronous state using the output S of the comparator circuit 43. Met.

[0005]

[Problems to be Solved by the Invention] This conventional synchronization detection circuit requires many circuits such as a multiplier circuit, a low-pass filter, a comparator circuit, and a threshold voltage generation circuit, resulting in a complicated circuit configuration. . In addition, since many analog circuits such as low-pass filters, comparison circuits, and threshold voltage generation circuits are required, circuit characteristics tend to be sensitive to variations and fluctuations in elements, making circuit design difficult. .

[0006]

[Means for Solving the Problems] The synchronization detection circuit of the present invention includes a phase comparison circuit, a loop filter, and a voltage-controlled oscillation circuit, and detects a phase synchronization state of a phase-locked loop. a first delay circuit that receives one of the output signals of the voltage controlled oscillator circuit, delays this signal by a predetermined delay time, and outputs the output signal that is input to one input terminal of the phase comparison circuit; a second delay circuit that is connected in series to the first delay circuit and delays the output of the first delay circuit by the delay time; and a logic between the input of the first delay circuit and the output of the second delay circuit. It is configured to include a logic circuit that performs calculations, and a latch circuit that uses the other input of the phase comparison circuit as a clock and latches the output of the logic circuit at the timing of this clock.

[0007]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a synchronization detection circuit according to the present invention.

In FIG. 1, the synchronization detection circuit 1 of this embodiment
are delay circuits DL1 and DL2, inverter I1, and N
It is configured to include an OR circuit E1 and a flip-flop FF1. The output of the phase-locked loop 2 is input to the delay circuit DL1 and the inverter I1, respectively.

The phase-locked loop 2 includes a phase comparator circuit 21,
It is composed of a loop filter 22 and a voltage controlled oscillation circuit 23. The delay circuits DL1 and DL2 are circuits that provide a constant time delay to the output A of the voltage controlled oscillation circuit 23. Flip-flop FF1 holds input data D at the rising edge of input signal I, which is a clock. The signal S indicating synchronous and asynchronous is the flip-flop FF1.
is obtained from the output terminal Q of.

Next, the operation of this embodiment will be explained.

FIG. 2 is a time chart showing the operation of the synchronization detection circuit of this embodiment shown in FIG. In FIG. 2, a solid line indicates a case where the input signal I entering the phase comparison circuit 21 and the output signal B of the phase-locked loop 2 delayed by the delay circuit DL1 are aligned in phase and are in a phase-synchronized state. Further, a broken line indicates a case where there is a phase difference of a certain value or more between the input signal I and the signal B, and the phase synchronization is out of phase. If the phase differences generated in the delay circuits DL1 and DL2 are respectively φ, the signals A, B, and C each have a phase difference of φ, so the signal D becomes a pulse output having a width of 2φ. Flip-flop FF1 receives signal D as input signal I
Since the signal is latched at the rising edge of , when the phase difference between the input signal I and the signal B is within ±φ, the output of the flip-flop FF1, that is, the synchronization detection signal S becomes “1”. Furthermore, when the phase difference between the input signal I and the signal B is greater than or equal to ±φ, the synchronization detection signal becomes “0”. In this way, in the circuit shown in FIG. 1, by determining whether the phase difference between the input signal I and the signal B is within ±φ, it is possible to detect synchronization or asynchronous state of the phase-locked loop 2.

Next, a second embodiment of the present invention will be explained.

FIG. 3 is a block diagram showing a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the delay circuits DL1 and DL2 are connected to the input signal I instead of being connected to the output of the voltage controlled oscillation circuit 23. Along with this, the symbols of the phase-locked loop 3 and the synchronization detection circuit 5 have been changed.

Next, the operation of this embodiment will be explained.

FIG. 4 is a time chart of the circuit shown in FIG. Comparing FIG. 4 with the time chart of the first embodiment described above shown in FIG.
The output signal H of the phase-locked loop in FIG. 2 is the output signal H of the phase-locked loop in FIG.
are replaced by each. Since the operations other than this are completely the same, the explanation will be omitted.

As described above, the synchronization detection circuit of the present invention can be realized using a delay circuit and a few logic gates, so it has the advantage that it can be realized with a simpler circuit configuration than the conventional synchronization detection circuit. There is. Furthermore, the only analog circuit used is a delay circuit, and the difficulty in circuit design is relatively low.

[0018]

As explained above, the synchronization detection circuit of the present invention has first and second delay circuits connected in series, and logic between the input of the first delay circuit and the output of the second delay circuit. Since it is configured to include a logic circuit that performs calculations and a latch circuit for the output of the logic circuit, it has the advantage that the synchronization detection circuit can be configured with a relatively simple circuit configuration. It also has the effect of reducing the difficulty required for its design.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a synchronization detection circuit of the present invention.

FIG. 2 is a flowchart showing an example of the operation of the synchronization detection circuit of this embodiment.

FIG. 3 is a block diagram showing a second embodiment of the synchronization detection circuit of the present invention.

FIG. 4 is a flowchart showing an example of the operation in the synchronization detection circuit of the second embodiment.

FIG. 5 is a block diagram showing an example of a conventional synchronization detection circuit.

FIG. 6 is a flowchart showing the operation of a conventional synchronization detection circuit.

[Explanation of symbols]

1, 4, 5 Synchronization detection circuit 2, 3 Phase locked loop 21 Phase comparison circuit 22 Loop filter 23 Voltage controlled oscillation circuit 41 Multiplication circuit 42 Low pass filter 43 Comparison circuit DL1, DL2 Delay circuit E1 NOR circuit FF1 Flip-flop II Inverter

Claims (1)

[Claims] Claim 1. A synchronization detection circuit that includes a phase comparison circuit, a loop filter, and a voltage-controlled oscillation circuit and detects a phase-locked state of a phase-locked loop, wherein either an input signal or an output signal of the voltage-controlled oscillation circuit is detected. a first delay circuit which receives one signal, delays this signal by a predetermined delay time, and inputs the output to one input terminal of the phase comparison circuit; a second delay circuit that delays the output of the first delay circuit by the delay time;
A logic circuit that performs a logical operation on the input of the first delay circuit and the output of the second delay circuit, and the other input of the phase comparison circuit are used as a clock, and the output of the logic circuit is used as a clock. A synchronous detection circuit comprising a latch circuit that latches at timing.