JPH076152A - Input circuit for external control signal - Google Patents

Abstract

PURPOSE:To realize an external control signal input circuit capable of preventing the malfunction thereof at the time of switching a terminal function. CONSTITUTION:The input circuit is provided with an edge detecting circuit 1 for detecting a change in the value of an external terminal 22 correspondingly to the terminal 22 to be used also as a general port, a control signal generating circuit 2 for outputting a control signal 104 at the time of receiving an edge detection signal 103 outputted from the circuit 1, a control circuit 4 for inputting the signal 103 outputted from the circuit 1 and generating and outputting a mask signal 106 for controlling the output of an external control signal 107 through a mode control signal (PMC) 102 inputted from a mode register, and a mask circuit 3 for controlling the permission/inhibition of the output of the external control signal 107 through the mask signal 106 outputted from the circuit 4.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an external control signal input circuit.

[0002]

2. Description of the Related Art Conventionally, in a system that is required to realize more functions with a small number of terminals as seen in a single-chip microcomputer, as an example, "1991 version, NEC" 16 bits " -As shown in "Single-chip microcomputer data book", the terminal function is selected by the mode register in the external control signal input circuit in which the external control signal input terminal is also used as the general-purpose port. When the external control signal input terminal is used as a general-purpose port, a method of fixing the input signal of the control signal generation circuit is used in order to prevent generation of unnecessary control signals.

FIG. 6 is a block diagram showing the structure of the above-mentioned conventional external control signal input circuit. The mask circuit 21 and the control signal generation circuit 2 are provided corresponding to the external terminal 22 which is also used as a general-purpose port. It is configured with. When the external terminal 22 is used as a general-purpose port, a control signal (PMC) 102 input from a mode register (not shown) that performs a terminal function selecting operation on the external terminal 22 causes an external control signal 101 from the outside. The control signal 115 input to the control signal generation circuit 2 from the mask circuit 1 in response to the input of is fixed and its output is prohibited, and the external control signal 107 to be generated and output in the control signal generation circuit 2 is output. Is prevented from occurring. Also, the external control signal 1
When a predetermined control signal 107 is output from the control signal generation circuit 2 in response to the input 01, the control signal (PMC) 102 input from the mode register is canceled, and in the control signal generation circuit 2, The edge of the value of the control signal 115 input via the mask circuit 1 is detected, and the external control signal 107 is generated and output.

[0004]

In the conventional external control signal input circuit described above, when the external terminal is used as a general-purpose port, a measure for preventing the generation of an unnecessary external control signal is input from the mask circuit. This is performed in the mask circuit before the control signal generation circuit that detects the edge of the signal value and outputs the control signal. For this reason, when the terminal function of the external terminal is switched from the general-purpose port function to the control signal input function, the value of the external control signal from the external terminal is the value when the control signal for the control signal generation circuit is fixed. If the value is opposite to the above, the edge detection is performed with the level of the control signal to the control signal generating circuit being inverted, so that an incorrect external control signal is generated and output in the control signal generating circuit. However, there is a drawback that the malfunction occurs.

[0005]

An external control signal input circuit according to the present invention has an external terminal commonly used for two types of functions, that is, a general-purpose port and a control signal input. An external control signal output circuit that generates and outputs an external control signal from an input signal applied to an external terminal, detects a change in level value at the external terminal,
An edge detection circuit that outputs an edge detection signal corresponding to the change in the level value, and the edge detection signal are input,
A control signal generation circuit that generates and outputs a predetermined control signal, and the edge detection signal are input, and a mask signal that controls whether to output an external control signal via a predetermined mode control signal is generated and output. And a mask circuit that receives the control signal and outputs or stops the external control signal via the mask signal.

The edge detection circuit receives a change in the level value at the external terminal and outputs the first latch circuit in synchronization with a predetermined clock, and the output of the first latch circuit. A first flip-flop circuit that holds the level value of the external terminal one clock before via the clock is compared with the output of the first latch circuit and the output of the first flip-flop circuit, and they do not match. And an EXOR circuit that outputs an edge detection signal, and the control signal generation circuit is configured by a second latch circuit that delays the edge detection signal by 1/2 clock and outputs the delayed signal as a control signal. The control circuit delays the mode control signal by ½ clock via the clock and outputs a signal for inhibiting the output of the external control signal. Circuit, a fourth latch circuit for outputting a signal for inhibiting the output of the external control signal from the clock by delaying it by 1/2 clock, and outputting the external control signal via the clock by receiving the edge detection signal. And a first AND circuit that outputs a first timing signal that latches a signal that permits the output of the external control signal, and a signal that inhibits the output of the external control signal.
A latch circuit with a reset that holds the signal output from the fourth latch circuit via the timing signal and outputs a signal that permits the output of the external control signal; and an external output from the third latch circuit. A second AND circuit configured to output a logical product of a signal for prohibiting the output of the control signal and a signal for permitting the output of the external control signal output from the latch circuit with reset as a mask signal. The circuit includes a third AND circuit that outputs a logical product of the control signal output from the control signal generation circuit and the mask signal, and the third AND circuit when the mask signal permits the output of the external control signal. And a fifth latch circuit that receives the output signal of the AND circuit and generates and outputs an external control signal via the clock.

Further, the edge detection circuit receives a change in the level value at an external terminal and outputs a first latch circuit which outputs in synchronization with a predetermined clock, and an output of the first latch circuit, A first flip-flop circuit that holds the level value of the external terminal one clock before via the clock is compared with the output of the first latch circuit and the output of the first flip-flop circuit, and they do not match. And a first EXOR circuit for detecting an edge detection signal and outputting an edge detection signal. The control signal generation circuit receives the edge detection signal and outputs a predetermined time from the fall of the edge detection signal via the clock. A pulse generation circuit which later generates and outputs a first timing signal;
Receiving the timing signal of
A first AND circuit for generating and outputting the timing signal of No. 1, and a signal for holding the signal output from the first flip-flop circuit via the second timing signal and outputting a first level signal. A second latch circuit, a second flip-flop circuit that receives the first level signal, delays one clock through the clock, and outputs a second level signal; and the first and second flip-flop circuits. And a second EXOR circuit for detecting a mismatch and outputting the control signal as a control signal, the control circuit delays the mode control signal by 1/2 clock through the clock, A third latch circuit that outputs a signal that inhibits the output of the external control signal and an output of the external control signal that is delayed by 1/2 clock of the signal that inhibits the output of the external control signal are output. A fourth latch circuit, a second AND circuit that receives the edge detection signal, outputs a third timing signal that latches a signal that permits the output of the external control signal via the clock, and the external circuit. The third signal is reset by a signal that prohibits the output of the control signal,
A latch circuit with a reset that holds the signal output from the fourth latch circuit via the timing signal and outputs a signal that permits the output of the external control signal; and an external output from the third latch circuit. A third AND circuit which outputs a logical product of a signal for inhibiting the output of the control signal and a signal for permitting the output of the external control signal output from the latch circuit with reset as a mask signal, and the mask The circuit includes a fourth AND circuit that outputs a logical product of the control signal output from the control signal generation circuit and the mask signal, and the fourth AND circuit when the mask signal permits the output of the external control signal. And a fifth latch circuit that receives the output signal of the AND circuit and generates and outputs an external control signal via the clock.

[0008]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the basic configuration of the present invention. As shown in FIG. 1, the present invention corresponds to an external terminal 22 which is also used as a general-purpose port, and an edge detection circuit 1 for detecting a change in the value at the external terminal 22 and a change in the value 101 at the external terminal 22. Corresponding to, edge detection circuit 1
The control signal generation circuit 2 that receives the edge detection signal 103 output from the edge detection circuit 103 and outputs the control signal 104, and the edge detection signal 103 output from the edge detection circuit 1 are input and the mode control signal (from the mode register PMC)
A control circuit 4 for generating and outputting a mask signal 106 for controlling whether to output an external control signal and a control signal 104 output from the control signal generating circuit 2 are input via 102, and the control circuit 4 outputs the control signal 104. A mask circuit 3 for controlling permission / prohibition of the output of the external control signal 107 via the output mask signal 106.

In FIG. 1, when the external terminal 22 is used as a general-purpose port, a mode control signal (PMC) 102 input from a mode register (not shown) for selecting a terminal function of the external terminal 22 is a predetermined signal. The level is input to the control circuit 4. In the edge detection circuit 1, a change in the value 101 of the external terminal 22 is detected and output as the edge detection signal 103, which is input to the control signal generation circuit 2 and the control circuit 4. In the control signal generation circuit 2, the edge detection signal 103 is delayed by ½ clock, output as the control signal 104, and input to the mask circuit 3. On the other hand, the control circuit 4 receives the mode control signal (PMC) 102 from the mode register and the edge detection signal 103 output from the edge detection circuit 1 as a mask signal 106 for the mask circuit 3.
A level signal for inhibiting the output of the external control signal 107 is output and input to the mask circuit 3. In the mask circuit 3, while the mask signal 106 output from the control circuit 4 is received and the mask signal 106 is input as a level signal that prohibits the output of the external control signal 107, the control signal 104 remains in the mask circuit 106. 3 is fixed to the "0" level and the mask circuit 3 outputs the external control signal 10
7 is not output.

When the external terminal 22 is used as an input terminal for the external control signal, the mode control signal 102 input from the mode register for selecting the terminal function of the external terminal 22 is used as the general-purpose port. In this case, the signal is input to the control circuit 4 as a signal of an inverted level of the mode control signal 102 in that case. In this case, the control circuit 4 outputs, as the mask signal 106 for the mask circuit 3, a level signal for permitting the output of the external control signal, which is input to the mask circuit 3. In the mask circuit 3, while the control signal 104 output from the control signal generation circuit 2 is received and the mask signal 106 is input as a level signal that permits the output of the external control signal 107,
A predetermined external control signal 107 is output.

FIG. 2 is a block diagram showing a first embodiment of the present invention, showing the internal structures of the edge detection circuit 1, the control signal generation circuit 2, the mask circuit 3 and the control circuit 4, respectively. As shown in FIG. 2, the edge detection circuit 1 includes a latch circuit 5 for synchronizing the level change of the value 101 at the external terminal 22 with the clock 108 and a flip-flop circuit for holding the value 101 of the external terminal 22 one clock before. 6 and an EXOR circuit 7 that compares the output of the latch circuit 5 and the output of the flip-flop circuit 6 to detect a mismatch and outputs an edge detection signal 103. The control signal generation circuit 2 includes an edge detection signal. 103 to 1
The control circuit 4 is constituted by a latch circuit 8 which delays by 1/2 clock and outputs it as the edge detection signal 104.
The mode control signal 102 input from the mode register is delayed by ½ clock to output the signal 111 for inhibiting the output of the external control signal, and the signal 111 is delayed by ½ clock. , A signal 113 for designating a timing for latching a signal permitting the output of the external control signal from the edge detection signal 103 and the latch circuit 12 which outputs the signal 112 via the clock 108.
And the signal 113 which is reset by the signal 111 for prohibiting the output of the external control signal.
The latch circuit with reset 14 that holds the signal 112 output from the latch circuit 12 via the signal and outputs the signal 114 that permits the output of the external control signal, the signal 111 that prohibits the output of the external control signal, and the external control The AND circuit 15 that outputs the logical product of the signals 114 that permit the output of signals as the output control signal 106. Further, the mask circuit 3 includes an edge circuit during the period when the mask signal 106 is at "0" level. An AND circuit 9 for outputting a signal 115 for fixing the level of the detection signal 104 to "0"level;
Within the period in which the mask signal 106 is at "1" level, A
The output signal 115 of the ND circuit 9 is composed of a latch circuit 10 which generates and outputs an external control signal 107 in synchronization with the output timing of the external control signal via the clock 108.

Next, the operation of this embodiment will be described with reference to FIGS. 2 and 3 (a), (b), (c), (d), (e),
Description will be given with reference to the timing diagrams of (f), (g), (h), (i) and (j).

First, during the port mode period (T1 to T6) in which the external terminal 22 is used as a general-purpose port,
The mode control signal 102 is set to "0" level, and the signal 111 for prohibiting the output of the external control signal output from the latch circuit 11 is set to "0" level. Therefore, in the control circuit 4, The mask signal 106 output from the AND circuit 15 also becomes the “0” level and is input to one input end of the AND circuit 9 included in the mask circuit 3. Period of this general-purpose port use mode (T1 to T6
), When the level of the value 101 at the external terminal 22 changes, in the edge detection circuit 1, at the timing T2, the latch circuit 5 causes the clock 10
8 is converted into the signal 109 (see FIGS. 3A and 3C) and delayed by one clock by the flip-flop circuit 6, and then the signal 11 is output at the timing T3.
Output as 0 (see FIGS. 3 (a) and 3 (d)),
It is input to the EXOR circuit 7. In the EXOR circuit 7, the signal 109 and the signal 110 are received, and the edge detection signal 103 is generated and output at the timing T2 (see FIGS. 3A and 3E).

In the control signal generation circuit 2, the edge detection signal 103 is delayed by 1/2 clock by the latch circuit 8 and output as the control signal 104 which is synchronized with the timing in the control circuit 4 and masked. It is input to the circuit 3. In the mask circuit 3, the mask signal 1 for the AND circuit 9 included in the mask circuit 3
Since 06 is input at the "0" level, AND
The 115 output from the circuit 9 is always at "0" level regardless of the value of the control signal 104, and therefore the output of the external control signal 107 from the latch circuit 10 is kept at "0" level. It is not output to the outside because it is not brought to the "1" level.

In this state, the value of the external terminal 22 is 10
When a level change occurs at 1, the edge detection signal 103 is generated and output by the edge detection circuit 1 at timing T10 (see FIGS. (A) and (e)), and the control signal is generated, as in the above case. It is input to the circuit 2. In the control signal generation circuit 2, the edge detection signal 103
Is delayed by 1/2 clock by the latch circuit 8,
The control signal 104 synchronized with the timing in the control circuit 4 is output and input to the mask circuit 3.

On the other hand, the edge detection signal 103 is the control circuit 4
When input to the AND circuit 13 included in, the AND circuit 13 receives the edge detection signal 103 and the clock 108, outputs the timing signal 113, and inputs the timing signal 113 to the latch circuit with reset 14. The reset latch circuit 14 receives the timing signal 113 and permits the output of the external control signal 11.
4 is output at the "1" level and is input to the AND circuit 15. In this case, the signal 111 for prohibiting the output of the external control signal which is also input to the AND circuit 15 is also at the "1" level, so the mask signal 106 output from the AND circuit 15 is also output at the "1" level. Timing T10
In, the generation of the external control signal is permitted. Therefore, the signal 115 output from the AND circuit 9 included in the mask circuit 3 is output at the “1” level while the edge detection signal 104 is at the “1” level, and the external control signal 107 is output from the latch circuit 10. Is output.

The mode control signal 102 has a timing T18.
When the level changes from “1” level to “0” level in, the signal 111 for prohibiting the output of the external control signal output from the latch circuit 11 included in the control circuit 4 becomes “0” level and is output from the AND circuit 15. The mask signal 106 also becomes "0" level at the timing T18, and in the mask circuit 3, the output level of the external control signal 107 becomes "0" level and does not change.
The external control signal 107 is not output to the outside.

In the description of the operation of this embodiment, the rising edge at which the value of the external terminal changes from the "0" level to the "1" level and the falling edge at which the value of the external terminal changes from the "1" level to the "0" level. The example in which the external control signal is output for both edges of
In the above, by performing only one edge detection, it is possible to realize an external control signal generation circuit capable of outputting the external control signal only to one edge.

Next, FIG. 4 is a block diagram showing a second embodiment of the present invention, showing the internal configurations of the edge detection circuit 1, the control signal generation circuit 2, the mask circuit 3 and the control circuit 4, respectively. There is. As shown in FIG. 4, the edge detection circuit 1 changes the level of the value 101 at the external terminal 22 by the clock 108, as in the case of the first embodiment.
A latch circuit 5 for synchronizing with the flip-flop circuit 6 for holding the value 101 of the external terminal 22 one clock before,
The output of the latch circuit 5 and the output of the flip-flop circuit 6 are compared with each other, and an EXOR circuit 7 that detects a mismatch and outputs an edge detection signal 103 is provided. The control signal generation circuit 2 causes the edge detection signal 103 to rise. A pulse generation circuit 16 for generating and outputting a timing signal 116 after a predetermined time from the fall, a timing signal 116 and a clock 1
In response to 08, the AND circuit 17 that outputs the timing signal 117 that holds the signal 110 output from the flip-flop circuit 6, and the latch circuit 18 that holds the signal 110 by this timing signal 117 and outputs the level signal 118 , Level signal 118 via clock 108
A flip-flop circuit 19 for outputting a level signal 119 delayed by one clock, and the level signals 11
8 and 119 are inputted and compared to detect an inconsistency and output as an edge detection signal 104. The control circuit 4 inputs from the mode register as in the case of the first embodiment. Circuit 11 which delays the generated mode control signal 102 by 1/2 clock and outputs a signal 111 for inhibiting the output of the external control signal.
The latch circuit 12 delays the signal 111 by 1/2 clock and outputs the signal 112, and the timing for latching the signal from the edge detection signal 103 that permits the output of the external control signal via the clock 108. AND circuit 13 that outputs a signal 113 that specifies the signal 113
The signal 112 which holds the signal 112 output from the latch circuit 12 via the
A latch circuit with reset 14 that is reset by 1;
The AND circuit 15 outputs a logical product of a signal 111 for prohibiting the output of the external control signal and a signal 114 for permitting the output as the output control signal 106. Further, the mask circuit 3 also has the first embodiment. Similar to the example, the signal 1 for fixing the level of the edge detection signal 104 to the “0” level during the period when the output control signal 106 is the “0” level.
The AND circuit 9 that outputs 15 and the latch circuit 10 that generates and outputs the output signal 115 of the AND circuit 9 as the external control signal 107 in synchronization with the output timing of the external control signal via the clock 108. Has been done.

That is, the difference between this embodiment and the first embodiment is the difference in the configuration contents of the control signal generation circuit 2.

Next, the operation of this embodiment will be described with reference to FIGS. 4 and 5 (a), (b), (c), (d), (e),
(F), (g), (h), (i), (j), (k),
This will be described with reference to the timing charts of (l) and (m).

First, during the port mode (T1 to T6 and T20 to T) in which the external terminal 22 is used as a general-purpose port.
23), the mode control signal 102 is set to the “0” level, which allows the external control signal output from the latch circuit 11 in the control circuit 4 to be the same as in the first embodiment. Since the signal 111 for inhibiting the output of the signal is at "0" level, the mask signal 106 output from the AND circuit 15 is also "0" at the timing T18.
It becomes a level and is input to one input terminal of the AND circuit 9 included in the mask circuit 3. As a result, the output of the external control signal 107 is prohibited, and the value of the external control signal 107 is kept at "0" level and does not change.

Next, during a period (T7 to T19) in which the mode control signal 102 is at "1" level, the external terminal 22 is used as a control signal input terminal, and the latch circuit 11 included in the control circuit 4 operates. The signal 111 for prohibiting the output of the external control signal to be output becomes the “1” level,
The output 112 of the latch circuit 12 is also at "1" level,
Since the timing signal 113 is not output from the AND circuit 13 until the edge detection signal 103 is input,
The output 114 of the latch circuit 14 remains at "0" level, and the mask signal 106 output from the AND circuit 15 also remains at "0" level and does not change.

Here, when the level of the value 101 of the external terminal 22 changes at the timing T9, in the edge detection circuit 1, the value 101 of the external terminal 22 is changed by the latch circuit 5 to a signal synchronized with the clock 108 at the timing T9. 109 and the flip-flop circuit 6
After being delayed by one clock at, the signal 110 is output at timing T11 and input to the EXOR circuit 7 and the latch circuit 18. The EXOR circuit 7 receives the signal 109 and the signal 110, outputs the edge detection signal 103 at the timing T9, and inputs them to the pulse generation circuit 16 included in the control signal generation circuit 2 and the AND circuit 13 included in the control circuit 4. To be done. AND
The circuit 13 receives the edge detection signal 103 and receives the timing signal 11 via the clock 108.
3 is output and input to the C terminal of the latch circuit with reset 14. In the latch circuit with reset 14, the signal 114 permitting the output of the external control signal is output at the “1” level in response to the input of the signal 112 output from the latch circuit 12 and the reset input of the signal 113. ,
As a result, the mask signal 106 output from the AND circuit 15 becomes "1" level, and the output of the external control signal from the mask circuit 3 is permitted at the timing T10.

In the control signal generating circuit 2, the pulse generating circuit 16 outputs the signal 116 after a predetermined time has elapsed from the falling edge of the edge detection signal 103 and inputs it to the AND circuit 17, but during this time, at timings T10 to T11. When the level of the value 101 of the external terminal 22 changes, the edge detection circuit 1 outputs the edge detection signal 103 again at timings T11 to T12, whereby the pulse generation circuit 16 is initialized and the last edge is detected. A predetermined time after the fall of the detection signal 103, the signal 116 is output at timing T13 and the AND circuit 17
Entered in. In the AND circuit 17, the signal 116
And the timing signal 117 is generated in response to the clock 108 and is input to the latch circuit 18. Latch circuit 1
8, the signal 110 output from the flip-flop circuit 6 is held via the timing signal 117, and the level signal 118 is output at the timing T14 to output the flip-flop circuit 19 and the EXOR circuit 20.
Entered in. In response to this, when the level signal 119 is output from the flip-flop circuit 19 at the timing T15, the level signal 11 is output in the EXOR circuit 20.
8 and 119 are compared, the edge detection signal 104 is output at timing T14, and AN of the mask circuit 3 is output.
It is input to the D circuit 9.

In the mask circuit 3, the output control signal 106 for the AND circuit 9 included in the mask circuit 3 is output.
However, since it is input at the "1" level as described above, the signal 115 output from the AND circuit 9 is "1" at the timing T14 while the value of the edge detection signal 104 is at the "1" level. , And the external control signal 107 from the latch circuit 10 at timing T15.
Is output.

In the second embodiment described above, the first
As in the case of the above embodiment, the rising edge at which the value of the external terminal changes from the “0” level to the “1” level,
An example in which an external control signal is output to both edges of the falling edge that changes from the “1” level to the “0” level has been shown, but unlike the first embodiment, in the present embodiment, EXOR circuit 20 in control signal generating circuit 2
By changing the comparison method of, it is possible to realize a circuit that outputs the external control signal only to one edge.

[0029]

As described above, according to the present invention, the mask circuit is provided in the subsequent stage of the control signal generating circuit, and the control circuit is added, so that the external control is performed during the period when the external terminal is used as the general-purpose port. Switching the pin function by prohibiting signal generation and configuring the circuit to allow the output of the external control signal from the time when the value of the external pin changes after the external pin is switched from the general-purpose port to the control pin There is an effect that it can be prevented in time.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of the present invention.

FIG. 2 is a block diagram showing a first embodiment of the present invention.

FIG. 3 is a timing chart showing an operation example in the first embodiment.

FIG. 4 is a block diagram showing a second embodiment of the present invention.

FIG. 5 is a timing chart showing an operation example in the second embodiment.

FIG. 6 is a block diagram showing a conventional example.

[Explanation of symbols]

 1 Edge Detection Circuit 2 Control Signal Generation Circuit 3 Mask Circuit 4 Control Circuit 5, 8, 10-12, 18 Rich Circuit 6, 19 Flip-Flop Circuit 7, 20 EXOR Circuit 9, 13, 15, 17 AND Circuit 14 Latch with Reset Circuit 16 Pulse generation circuit

Claims (3)

[Claims] 1. An external control signal is generated from an input signal applied to the external terminal via a predetermined function selecting action, having an external terminal commonly used for two types of functions of a general-purpose port and a control signal input. An external control signal output circuit that outputs the edge detection signal that detects a change in the level value at the external terminal and outputs an edge detection signal corresponding to the change in the level value. A control signal generation circuit for generating and outputting a predetermined control signal, and a mask signal for inputting the edge detection signal and controlling whether to output an external control signal via a predetermined mode control signal. And a mask circuit that receives the control signal and outputs or stops an external control signal via the mask signal. External control signal input circuit that. 2. The edge detection circuit receives a change of a level value at an external terminal and outputs a first latch circuit which outputs in synchronization with a predetermined clock, and an output of the first latch circuit, A first flip-flop circuit that holds the level value of the external terminal one clock before via the clock is compared with the output of the first latch circuit and the output of the first flip-flop circuit, and they do not match. And an EXOR circuit for detecting an edge detection signal and outputting an edge detection signal, wherein the control signal generation circuit reduces the edge detection signal to 1/2.
It is configured by a second latch circuit that delays by a clock and outputs as a control signal, and the control circuit delays the mode control signal by 1/2 clock through the clock to prohibit the output of the external control signal. A third latch circuit for outputting a signal, a fourth latch circuit for outputting the output of the external control signal by delaying the signal for inhibiting via the clock by 1/2 clock, and the edge detection signal. And a first AND circuit that outputs a first timing signal that latches a signal that permits the output of the external control signal via the clock, and is reset by a signal that inhibits the output of the external control signal. A latch with reset for holding the signal output from the fourth latch circuit via the first timing signal and outputting a signal for permitting the output of the external control signal Circuit,
A logical product of a signal for inhibiting the output of the external control signal output from the third latch circuit and a signal for permitting the output of the external control signal output from the latch circuit with reset is output as a mask signal. A second AND circuit, and the mask circuit outputs a logical product of the control signal output from the control signal generation circuit and the mask signal.
And an AND circuit for receiving the output signal of the third AND circuit when the mask signal permits the output of the external control signal, and outputs the external control signal through the clock. 2. A latch circuit according to claim 1.
The external control signal input circuit described. 3. The edge detection circuit receives a change of a level value at an external terminal, outputs a first latch circuit which outputs in synchronization with a predetermined clock, and an output of the first latch circuit, A first flip-flop circuit that holds the level value of the external terminal one clock before via the clock is compared with the output of the first latch circuit and the output of the first flip-flop circuit, and they do not match. And a first EXOR circuit for detecting an edge detection signal and outputting an edge detection signal, wherein the control signal generation circuit receives the edge detection signal and outputs a predetermined time from the fall of the edge detection signal via the clock. A pulse generation circuit that later generates and outputs a first timing signal, and receives the first timing signal and generates a second timing signal via the clock. A first AND circuit that outputs the first level signal and a second latch circuit that holds the signal output from the first flip-flop circuit via the second timing signal and outputs a first level signal. Receiving the first level signal, delaying by one clock through the clock,
Second flip-flop circuit which outputs the level signal of the second EXOR and the second EXOR which compares the first level signal and the second level signal to detect a mismatch and outputs the mismatch as a control signal.
A third latch circuit for delaying the mode control signal by ½ clock via the clock and outputting a signal for inhibiting the output of the external control signal, and the external circuit. A fourth latch circuit that delays the output of the control signal by ½ clock of a signal that inhibits the output of the control signal, and outputs the external control signal through the clock in response to the edge detection signal. A second AND circuit that outputs a third timing signal that latches a signal that permits the output of the signal, and a fourth latch that is reset by a signal that inhibits the output of the external control signal. A latch circuit with a reset that holds a signal output from the circuit and outputs a signal that permits output of an external control signal,
A logical product of a signal for inhibiting the output of the external control signal output from the third latch circuit and a signal for permitting the output of the external control signal output from the latch circuit with reset is output as a mask signal. And an AND circuit of No. 3, and the mask circuit outputs a logical product of the control signal output from the control signal generation circuit and the mask signal.
And the mask signal permits the output of the external control signal, the fifth AND circuit receives the output signal of the fourth AND circuit and generates and outputs the external control signal via the clock. 2. A latch circuit according to claim 1.
The external control signal input circuit described.