JPH0451624A - Bit synchronizing circuit - Google Patents

Abstract

PURPOSE:To process high speed data by proving a phase detection circuit detecting a phase difference between a clock signal extracted from the output data of a voltage controlled delay circuit controlling the delay quantity given to input data and a system clock signal, and generating the controlled voltage of a level corresponding to the pase difference and a low pass filter. CONSTITUTION:When the phase of the clock signal DCK with respect to the system clock signal SCK, namely, input data DTI is proceeded or delayed the control voltage Vc whose level is lower or higher than the level of a period T2 is outputted from the low pass filter 4. Then, the voltage controlled delay circuit 1 operates by the control voltage Vc in such a manner that it enlarges or reduces the passing time of input data DTI, namely, delay quantity. Thus, since input data DTI can be bit-synchronized with the system clock signal SCK, high speed data can be processed without increasing the scale of the circuit even if the precision of bit synchronization is improved.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a bit synchronization circuit, and particularly to a bit synchronization circuit that adjusts the phase of a system clock signal and input data in order to reduce code errors in a received digital signal. Regarding.

[Conventional technology]

Conventionally, this type of bit synchronization circuit includes a plurality of cascade-connected delay elements DE, as shown in FIG.
A data delay circuit 11 that outputs a plurality of data with different delay amounts from a pressure end, a selector 12 that selects and outputs one of the pressure data of the data delay circuit 11 in response to a selection signal SL, and a plurality of cascade-connected a clock delay circuit 13, which is equipped with a delay element DE2, and applies a delayed system clock signal DCK, which is obtained by sequentially delaying the input system clock signal SCK by minute time intervals, from the input end and output end of each of the delay elements DE2; a sampling circuit I4 which sequentially latches and outputs the output signal of the selector 12 using a delayed system clock signal DCK delayed by minute time intervals; and a majority decision circuit which determines the majority level of the output data of the sampler circuit 14. A logic circuit 15 and a delay value determining circuit 1 that outputs a selection signal SL according to the pressure data of the majority logic circuit 15.
6.

[Problem that the invention attempts to solve]

The conventional bit synchronization circuit described above has a data delay circuit 11.
and the clock delay circuit 13 includes a plurality of delay elements DE, D
The sampling circuit 14 is formed of a plurality of flip-flops FF, and the sampling circuit 14 is formed of a plurality of flip-flops FF.
The delay amount of the input data DTI is determined by the majority logic circuit 15 and the delay amount determining circuit 16 according to the output signal of Therefore, it is necessary to increase the number of delay elements DE, DE2 and flip-flops FF, and the majority logic circuit 15. There is a disadvantage that the number of logic operation elements and the like that constitute the delay amount determination circuit 16 increases, and the circuit scale increases.
Flip-flop FFs, logic operation elements, and the like have a drawback in that they have a large amount of delay and are unsuitable for bit synchronization of high-speed data.

An object of the present invention is to provide a bit synchronization circuit that can process high-speed data without increasing the circuit scale even if the precision of bit synchronization is improved.

[Means to solve the problem]

The bit synchronization circuit of the present invention includes a voltage control delay circuit that outputs input data including a clock signal with a delay amount according to the level of a control voltage, and a clock signal is extracted from pressure data of the voltage control delay circuit. a clock extraction circuit; a phase detection circuit that compares the phases of the clock signal from the clock signal and the system clock signal; and outputs a phase difference signal corresponding to the phase difference between these signals; and a phase difference signal from the phase detection circuit. and a reduction filter that removes high frequency components of the control voltage and generates the control voltage.

Further, a scramble circuit that performs a scramble process on the output data of the voltage control delay circuit is provided, and the pressure data of the scramble circuit is used as input data of the clock extraction circuit.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention.

In this embodiment, the control voltage ■ is applied to input data DTI including a clock signal. A voltage-controlled delay circuit 1 outputs a delay amount according to the level of the voltage-controlled delay circuit 1, and a phase difference signal corresponding to the phase difference between these signals is obtained by comparing the phases of the clock signal DCK and the system clock signal SCK from the extraction circuit 2. Vp
The high frequency components of the phase detection circuit 3 which outputs the phase detection circuit 3 and the phase difference signal (2) from the phase detection circuit 3 are removed to generate the control voltage V. The structure includes a reduction filter 4 that generates .

Next, the operation of this embodiment will be explained.

FIG. 2 is a waveform diagram of various signals for explaining the operation of this embodiment.

In FIG. 2, in the range of period T2, the system clock signal SCK and the input data DTI clock signal DCK,
Therefore, it indicates a state in which the bits are synchronized with the input data DTI, and within the period T1, the system clock signal SCK
This shows a state in which the phase of the clock signal DCK is ahead of that, and a state in which the phase of the clock signal DCK is delayed in the period T3.

Clock signal DC for system clock signal SCK
K, therefore, when the phase of input data DTI is leading, the reduction filter 4 outputs a period T during which the bits are synchronized.
Control voltage at a level lower than level 2■. is output,
This control voltage■. Accordingly, the voltage controlled delay circuit l operates to increase the transit time of the input data DTI, that is, the amount of delay.

Furthermore, when the phase of the clock signal DCK, and thus the input data DTI, lags behind the system clock signal SCK, the reduction filter 4 outputs the control voltage (2) at a level higher than the level of E'r2. is output, and this control voltage V. Therefore, the voltage controlled delay circuit l receives the input data DTI
It operates to reduce the transit time, that is, the amount of delay.

By doing so, the input data DTI can be bit synchronized with the system clock signal SCK.

FIG. 3 is a block diagram showing a second embodiment of the invention.

In this embodiment, a scrambling circuit 5 is provided which performs scrambling processing on the output data of the voltage control delay circuit 10, and the output data of this scrambling circuit 5 is used as the input take of the clock extraction circuit 2.

The bit array of the input data DT may include a large number of consecutive '0's' or '1's.

In such a case, it becomes difficult to extract the clock signal DCK and bit synchronization becomes difficult.

Therefore, this embodiment performs preset scrambling processing on the input data DT to prevent a bit array with a large number of consecutive "0"s or "1"s, and to ensure extraction of the clock signal DCK. This ensures more reliable bit synchronization.

〔Effect of the invention〕

As explained above, the present invention provides a voltage-controlled delay circuit that controls the amount of delay given to input data using a control voltage, and a difference between a clock signal extracted from output data of this voltage-controlled delay circuit and a system clock signal. By adopting a configuration that includes a phase detection circuit that detects and generates the control voltage at a level corresponding to this phase difference and a reduction filter, each circuit can be analogized, so when improving the precision of bit synchronization. However, it only requires processing such as increasing the amplification of the circuit, and the effect is that the entire circuit can be made smaller than conventional digital circuits, regardless of the accuracy of bit synchronization. For example, with the same bit synchronization accuracy, the conventional
What used to require about 1 gate can be reduced to 8 by applying the present invention.
The circuit scale is equivalent to that of a 0 gate.

In addition, the entire circuit becomes smaller, and flip-flops and logical operation elements with large delays are not required, or even if they are used, only a small portion thereof are used, so high-speed data can also be processed.

Circuit, 3... Phase detection circuit, 4... Reduction filter, 5... Scramble circuit, 11.
...Data delay circuit, 12...Selector, 13...Clock delay circuit, 14...
・Sampler circuit, 15...Majority circuit, 1
6...Delay amount determination circuit, DE, DE2...
・Delay element, FF...Flip-flop.

Agent Patent Attorney Susumu Uchihara

[Brief explanation of the drawing]

1 and 2 are block diagrams of a first embodiment of the present invention and waveform diagrams of signals in each part for explaining the operation of this embodiment, respectively, and FIG. 3 is a block diagram of a second embodiment of the present invention. The block diagram in FIG. 4 is a circuit diagram showing an example of a conventional bit synchronization circuit. l... Voltage control delay circuit, 2... Clock extraction VP Figure 1 VP Figure 3

Claims (1)

[Claims] 1. A voltage-controlled delay circuit that outputs input data including a clock signal with a delay amount according to the level of a control voltage, and a clock signal is extracted from the output data of this voltage-controlled delay circuit. a clock extraction circuit, a phase detection circuit that compares the phases of the clock signal from the clock extraction circuit and the system clock signal, and outputs a phase difference signal corresponding to the phase difference between these signals; A bit synchronization circuit comprising: a reduction filter that removes high frequency components of a signal and generates the control voltage. 2. The bit synchronization circuit according to claim 1, further comprising a scrambling circuit that performs scrambling processing on the output data of the voltage-controlled delay circuit, and the output data of the scrambling circuit is used as input data of the clock extraction circuit.