JP2575221B2 - PLL circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to setting a dividing ratio of a programmable divider in a PLL (Phase Locked Loop) circuit.

[Conventional technology]

FIG. 3 is a block diagram of a conventional PLL circuit. In the figure, (1) indicates a comparison signal input terminal, and (2) indicates a division ratio N of a programmable divider (2) for dividing an input signal of the comparison signal input terminal (1) into 1 / N. A data input terminal and a clock input terminal, (5) a shift register to which data of the data input terminal (3) is input,
(6) is a data latch circuit of the shift register (5),
(7) is an enable terminal for generating a latch signal for transferring data of the data latch circuit (6) to the programmable divider (2), (8) is a reference signal input terminal, and (9) is an output of the programmable divider (2). A phase comparator for detecting a phase difference between the signal and a reference signal input from a reference signal input terminal (8); (10) an output signal of the programmable divider (2) and a reference signal input terminal (8) This is a phase comparator output terminal for outputting the phase difference of the input signal from the input terminal.

Next, the operation will be described. The value of the dividing ratio N of the programmable divider (2) is set by reading data input from the data input terminal (3) and the clock input terminal (4) to the shift register (5) into the data latch circuit (6), Further, by controlling the enable terminal (7),
This is set by transferring the data of the data latch circuit (6) to the programmable divider (2) of (2). Here, when the data is input to the shift register (5), when the clock of the clock input terminal (4) falls from "H" to "L", the value of "H" or "L" of the data is read. It is done by being done. The input signal from the comparison signal input terminal (1) is divided into 1 / N by the division ratio N set as described above, and is output from the programmable divider (2). The phase comparison between the output signal of the programmable divider (2) and the reference signal at the reference signal input terminal (8) is performed by the phase comparator (9), and the phase difference between the two signals is determined by the phase comparator output terminal (10). Output.

[Problems to be solved by the invention]

In the conventional PLL circuit, the division ratio N of the programmable divider is set by three terminals of the data input terminal, the clock terminal, and the enable terminal, and the division ratio N is set only by the two terminals of the data input terminal and the clock terminal. There was a problem that can not be.

SUMMARY OF THE INVENTION The present invention has been made to solve the above problems, and has as its object to provide a PLL circuit that can set a frequency division ratio N only by a data input terminal and a clock terminal.

[Means for solving the problem]

A PLL circuit according to the present invention includes a programmable divider that receives an input signal and divides the input signal based on division ratio data, a data input terminal that receives the input data,
A clock input terminal for receiving a clock composed of first and second voltages, and a shift register connected to the data terminal and the clock terminal;
At the time of a first state transition of the clock from the first voltage to the second voltage, the input data is sequentially taken in as stored data, and a first transition of the clock from the second voltage to the first voltage is performed. When the input data at the time of the state transition of No. 2 has a predetermined value, the stored data is transferred as the frequency division ratio data.

[Operation] The shift register of the PLL circuit according to the present invention transfers the stored data as the frequency division ratio data when the input data at the time of the second state transition of the clock has a predetermined value. The enable terminal can be omitted, the number of external terminals can be reduced by one pin, and the externally input data can be set to the division ratio by only two data inputs, which used to be three conventionally. And the number of data input lines can be reduced.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram of a PLL circuit according to an embodiment of the present invention. In the figure, the same reference numerals as those of the conventional circuit denote the same elements.

In the figure, data input from a data input terminal (3) and a clock input terminal (4) are set as shown in the waveform diagram of FIG. That is, at the rising edge of the clock input from the clock input terminal (4) (at the time of the first state transition), the input data of the clock input terminal (3) is set to "H" or "L". The data is read into the shift register (5). At the time of the falling edge of the clock input terminal (4) (at the time of the second state transition),
The input data of the normal data input terminal (3) is set to "L". When the input data of the data input terminal (3) is set to "H" at the falling edge of the clock input terminal (4), a latch signal is output by the latch signal generation circuit built in the shift register (5), Latch circuit (6)
Is entered. The data in the data latch circuit (6) is transferred to the programmable divider (2) by the latch signal. In this manner, by using both the rising and falling edges of the clock input terminal (4) for inputting data and generating the latch signal for the other, the conventional enable terminal (7) can be omitted, and at the same time, Data input to the shift register (5) is also possible.

〔The invention's effect〕

As described above, according to the present invention, when setting the frequency division ratio of the conventional programmable divider, three input terminals are required, but only two terminals can be used, and the number of external terminals can be reduced by one. There is.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a PLL circuit according to an embodiment of the present invention, FIG. 2 is a waveform diagram of data input to a data input terminal and a clock input terminal of the circuit of FIG. 1, and FIG. FIG. 3 is a block diagram illustrating a PLL circuit. In the figure, (1) is a comparison signal input terminal, (2) is a programmable divider, (3) is a data input terminal,
(4) is a clock input terminal, (5) is a shift register,
(6) is a data latch circuit, (8) is a reference signal input terminal, (9) is a phase comparator, and (10) is a phase comparator output terminal. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A programmable divider for receiving an input signal and dividing the input signal based on division ratio data, a data input terminal for receiving the input data, and a clock input for receiving a clock composed of first and second voltages. And a shift register connected to the data terminal and the clock terminal, wherein the shift register stores data as the stored data at a first state transition of the clock from the first voltage to the second voltage. When the input data has a predetermined value at the time of a second state transition from the second voltage to the first voltage of the clock, the stored data is divided into the frequency division ratio data. A PLL circuit, wherein the data is transferred as data.