JPH0812574B2 - Integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an integrated circuit device, and more particularly to an integrated circuit device incorporating a clock skew adjusting circuit.

[0002]

2. Description of the Related Art Generally, an information processing apparatus is usually composed of a large number of large scale integrated circuits, and a clock signal for synchronization is distributed and supplied to each of these large scale integrated circuits. Has been done.

Conventionally, this clock signal is time-adjusted at the entrance of each integrated circuit by a delay element, a cable, etc. Further, by unifying all the configurations of the clock distribution circuits in each integrated circuit, the clock skew between the integrated circuits is increased. Is designed to be as small as possible.

As described above, in the conventional integrated circuit device, the phase of the clock signal is adjusted at the entrance of each integrated circuit.
In the case of a large-scale integrated circuit, the number of registers is several hundreds to several thousands, and it is necessary to distribute the clock signal to a large number of these registers. Therefore, even if the clock distribution circuit is unified in all integrated circuits, the delay time of the clock distribution circuit itself varies due to variations in manufacturing of the integrated circuit, and thus clock skew occurs between the integrated circuits. become.

Particularly, at present, the clock cycle becomes smaller, and the integrated circuit has a large manufacturing variation due to high integration, and therefore the skew of the clock cycle becomes large, which is a problem.

Therefore, various techniques have been proposed for adjusting the clock skew in each integrated circuit to reduce the clock skew between all the integrated circuits. For example, Japanese Patent Laid-Open No. 1-219917 and Japanese Patent Laid-Open No. 1-3003
The technology disclosed in Japanese Patent Publication No. 20 is listed. In the former technique, as shown in the circuit diagram of FIG. 7, a plurality of delay circuits 21 to 2n having different delay times with respect to the input clock signal 100 and the delay circuits 21 to 2n are provided in the LSI chip. The selection circuit 40 for selecting one of them by the external control signal 300 is provided in the preceding stage of the clock distribution circuit 50 in advance. Further, there is provided a monitor terminal 700 capable of externally monitoring a predetermined one clock signal 60 of the many clock distribution outputs 600 of the clock distribution circuit 50.

In such a configuration, first, at the time of circuit design, the clock input signal 100 is given to the LSI chip 10, and the LS
The delay time estimate of the clock signal output from the monitor terminal 700 of the I-chip 10 is obtained in advance. Then L
When the SI chip 10 is completed, the clock input signal 100 is actually applied to the chip 10 and the external control signal 300 is controlled while measuring the delay time of the clock signal output from the monitor terminal 700. When the clock signal close to the estimated value is obtained at the monitor terminal 700, the external control signal 300 is set and fixed.

The latter Japanese Unexamined Patent Publication No. 1-300320 discloses a structure as shown in FIG. In this configuration, a plurality of bits (the signal for controlling the selection circuit for selecting one of the delay circuits) external control signal 300 in the configuration of FIG. 7, so as to generate a flip-flop 30, as an input of the flip-flop 30 The optimum control signal 300 value is set and stored in the flip-flop 30. The other structure is the same as that of FIG.

[0009]

In such a conventional configuration, in order to accurately adjust the clock skew, many delay circuits having different delay times must be incorporated in the LSI chip in advance. , And also requires a multi-input 1-output selector to select one of these delay circuits,
There are drawbacks that the circuit configuration becomes complicated and the integration degree is reduced. Furthermore, since only one of a large number of delay circuits is finally used, there is a drawback that the circuit has a lot of redundancy and is not practical.

An object of the present invention is to provide an integrated circuit having a built-in clock skew adjusting circuit capable of adjusting the clock skew with extremely high accuracy with a simple circuit configuration.

Another object of the present invention is to provide an integrated circuit having a built-in clock skew adjustment circuit which does not require a large number of delay circuits to be redundantly provided.

[0012]

According to the present invention, the first delay means for changing the delay time of the input clock signal according to the external control signal and the delayed clock signal are distributed to a plurality of registers. To this end, there is provided a clock distributing means composed of a plurality of gates, a ring oscillator means including a feedback loop, and a second delay means having a delay time variable in accordance with an external control signal, and the ring oscillator means. The feedback loop of the oscillator is opened at the input part of the second delay means, and instead the switching means inputs the input clock signal to the second delay means; Phase difference detecting means for detecting the phase difference between the output clock signal input to the delay means and the predetermined output clock signal of the clock distributing means. The feedback Le by said switching means
Of the ring oscillator means when a loop is formed
Including the observation terminal for observing the cycle,
The delay of the second delay means according to the observed result
Adjust the time, and then use the switching means
When the input clock is input to the second delay means
An integrated circuit device with a built-in clock skew adjusting circuit is obtained in which the delay time of the first delay means is set in accordance with the phase difference.

[0013]

Embodiments of the present invention will be described below in detail with reference to the drawings.

FIG. 1 is a block diagram showing a first embodiment of the present invention. The input clock signal e is input to the first delay circuit DL1 via the gate G1. This delay circuit DL
The delay time of 1 is freely changeable by the external control signal g. The output clock signal of the delay circuit is input to the clock distribution circuit and distributed to the distribution terminals 1 to 7 to be supplied to each register (not shown). This clock distribution circuit is composed of gates G2 to G7.

On the other hand, a second delay circuit DL2 is provided, and the delay circuit DL2 and the buffer G8 form a feedback loop via the selector SEL1 so that they can operate as a ring oscillator. An observation gate G9 and a terminal d are provided in order to observe the oscillation period during the operation of the ring oscillator.

The delay time of this delay circuit DL2 is also variable by the external control signal h, and the input to this delay circuit DL2 is controlled by the switching control of the selector SEL1 at the input part of this delay circuit DL2. Output control or input clock signal e is switched and controlled. Incidentally, f is a switching control signal of the selector SEL1.

A D-type flip-flop FF1 for inputting a clock (CK) clock signal a passing through the delay circuit DL2 and the gate G8 is provided, and its data (D) input is any one of the distribution clocks of the distribution circuit. One clock b is applied. The Q output of the flip-flop FF1 is also derived as an observation terminal c.

In such a configuration, first, the selector SEL
1 forms a feedback loop, and the delay circuit DL2 and the gate G8 form a ring oscillator. The oscillation period of the ring oscillator at this time is measured by observing the waveform at the terminal d, and the delay time from the selector SEL1 to the gate G8 is set to a predetermined constant value by adjusting the delay amount of the delay circuit DL2.

Next, the selector SEL1 is switched so that the input clock signal e is supplied to the delay circuit DL2. As a result, the clock signal a passing through the delay circuit DL2 and the gate G8 is applied to the clock input of the D type flip-flop FF1. At this time, the clock signal b obtained by passing the input clock signal e through the delay circuit DL1 and the distribution circuit is applied to the data input of the flip-flop FF1. Therefore, the delay time of the delay circuit DL1 is adjusted while observing the waveform of the terminal c, which is the Q output of the flip-flop FF1, so that the waveform of the Q output coincides with the timing of 0 → 1 or 1 → 0. By setting the delay time at this time, the delay from the input end of the input clock signal e to the output of the gate G7 becomes the above-mentioned constant value (value set by the cycle of the ring oscillator by the delay circuit DL2 and the gate G8). It becomes possible.

FIG. 2 shows an example of the signal waveform of each part when the constant value is adjusted using the flip-flop FF1.
In FIG. 2, the duty of the clock signal is 50%.
Although shown as below, this duty is for illustration only and for purposes of illustration only.

Now, it is assumed that the clock input a of the flip-flop FF1 is as shown in FIG. 2a (its phase has already been set by the second delay circuit DL2, and will be referred to as a reference clock signal hereinafter). Distribution clock signal b of distribution circuit
2b has a slight phase delay from the reference clock signal a as shown in FIG. 2b, the Q output of the flip-flop FF1 maintains the 0 level as shown in FIG. 2c. On the contrary, when the phase of the distributed clock signal b is slightly advanced from the reference clock signal a as shown in FIG. 2b ', the Q output maintains 1 level as 2c'.

Therefore, if the delay time of the first delay circuit DL1 is controlled by the control signal g in order to adjust the phase coincidence between the two clock signals a and b, as shown in FIG. Output is 0 to 1 or 1 to 0
There is always a timing t0 that changes to. Therefore, the delay circuit DL1 at the change timing t0 of the Q output
If the delay time is fixed as it is, the phase of the clock signal b matches that of the reference clock signal a, and the adjustment ends.

In all the other integrated circuits, if the delay time of the delay circuit DL1 is adjusted and fixed by the same procedure, the distribution clock signals of the clock distribution circuits in all the integrated circuits have the above-mentioned constant delay time. Therefore, the clock skew between the integrated circuits becomes substantially zero.

FIG. 3 is a block diagram of the second embodiment of the present invention, and the same portions as those in FIG. 1 are designated by the same reference numerals. A part different from the configuration of FIG. 1 will be described.
The circuit (D-type flip-flop FF1 in FIG. 1) that detects the phase relationship between the distribution clock signal b and the distributed clock signal b has two trigger flip-flops TFF1 and TFF2 and these two.
It is composed of an AND circuit A1 having two inputs of the outputs j and i of one flip-flop. Flip-flop TFF1,
The distributed clock signal b and the reference clock signal a are applied to the respective inputs of the TFF2, and the phase difference between the clocks a and b is determined by observing the duty of the pulse of the output c of the AND circuit A1. it can.

The other structure is the same as that of FIG. 1 and its explanation is omitted. Also, the phase of the reference clock signal a is
It is assumed that the constant value has already been set by adjusting the delay time of the delay circuit DL2 while observing the oscillation period by the ring oscillator operation.

FIG. 4 is a waveform chart of each part showing an example of the phase difference detection operation according to the phase difference between the clock signals a and b at this time. It is assumed that the input reference clock signal a of the trigger flip-flop TFF2 is as shown in FIG. 4a. When the distribution clock signal b of the distribution circuit has a slight phase delay from the reference clock signal a as shown in FIG. 4b, the outputs j and i of both trigger flip-flops TFF1 and TFF2 are j and j of FIG.
It becomes like i. Therefore, the output c of the AND circuit A1 is as shown in FIG. 4c, and its duty is 5 in proportion to the phase difference.
It is less than 0%.

On the contrary, the distribution clock signal b as shown in FIG.
If the phase of is slightly ahead of the reference clock signal a,
The output j of the trigger flip-flop TFF1 changes as shown in FIG. 4j ', and the output of the AND circuit A1 has a duty of less than 50% as shown in FIG. 4c'.

Therefore, if the delay time of the first delay circuit DL1 is controlled by the control signal g so that the phase difference between the two clock signals a and b becomes zero, the output of the AND circuit A1 as shown in FIG. 2c ". Has a duty of 50%, and if the delay time of the delay circuit DL1 at that time is fixed as it is, the phase of the distributed clock signal b matches that of the reference clock signal a, and the adjustment ends.

FIG. 5 is a block diagram showing a third embodiment of the present invention, and the same portions as those in FIGS. 1 and 3 are designated by the same reference numerals. In this embodiment, the phase difference between the clock signal a and the distributed clock signal b is detected by observing the phases of the clock signals a and b at the switching output terminal c of the selector SEL2.

That is, the selector SEL2 is controlled by using the switching signal k to select one of the clock signals a and b, and the delay circuit DL1 is configured so that the waveform delay of the observation terminal c is the same regardless of which is selected. Adjust the delay time of. In this way, the gate G7 is connected from the input end of the input clock signal e.
Can be made equal to the delay time from the selector SEL1 set to a constant value to the gate G8.

FIG. 6 is a block diagram showing a fourth embodiment of the present invention, and the same parts as those in FIGS. 1, 3 and 5 are designated by the same reference numerals. In this example, a phase difference detection circuit I1 for detecting the phase difference between the reference clock signal a and the distribution clock b is provided, and a delay control circuit SD1 for generating a delay control signal g according to the detected phase difference is further provided. With this delay control signal g, the delay time of the delay circuit DL1 is automatically controlled.

By doing so, the reference clock signal a
Is automatically controlled so that the phase of the distributed clock signal b automatically coincides with the phase of (1), and it is not necessary to intervene manually, and more accurate clock skew adjustment is possible. Further, there is also an advantage that a terminal (terminal c in FIGS. 1, 3 and 5) for observing the phase difference between the two clock signals a and b is unnecessary.

[0033]

As described above, according to the present invention, the delay time from the clock signal input terminal of each integrated circuit to each distribution terminal of the clock distribution circuit can be set to a constant value. There is an effect that the clock skew caused by the manufacturing variation of the clock distribution circuit can be substantially zero.

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a timing waveform chart illustrating an example of clock skew adjustment according to the first embodiment of this invention.

FIG. 3 is a block diagram of a second embodiment of the present invention.

FIG. 4 is a timing waveform diagram illustrating an example of clock skew adjustment according to the second embodiment of the present invention.

FIG. 5 is a block diagram of a third embodiment of the present invention.

FIG. 6 is a block diagram of a fourth embodiment of the present invention.

FIG. 7 is a block diagram showing an example of a conventional clock skew adjustment circuit.

FIG. 8 is a block diagram showing another example of a conventional clock skew adjustment circuit.

[Explanation of symbols]

 1 to 7 clock distribution terminal A1 AND circuit DL1, DL2 delay circuit FF1 type flip-flop G1 to G9 gate I1 phase difference detection circuit SD1 delay control signal generation circuit SEL1, SEL2 selector TFF1, TFF2 trigger flip-flop

Claims (4)

[Claims] 1. A first delay means capable of changing a delay time of an input clock signal according to an external control signal, and a plurality of gates for distributing the delayed clock signal to a plurality of registers. The ring oscillator means includes a clock distributing means, a second delay means having a feedback loop and having a delay time that is variable in accordance with an external control signal, and a feedback loop of the ring oscillator.
Switching means for opening the input portion of the delay means and inputting the input clock signal to the second delay means instead, and when the input clock signal is input to the second delay means by the switching means Phase difference detecting means for detecting a phase difference between its output clock signal and a predetermined output clock signal of the clock distributing means, and the switching
The ring when the feedback loop is formed by means
And an observation terminal for observing the oscillation period of the oscillator means.
According to the observation result observed by the observation terminal,
The delay time of the second delay means is adjusted and set before
The input clock is set to the second delay by the switching means.
According to the phase difference when input to the extending means, the first
An integrated circuit device with a built-in clock skew adjustment circuit, characterized in that the delay time of the delay means is set. 2. The phase difference detection means includes a D type flip-flop that receives the predetermined output clock signal as a data input and the output clock signal of the second delay means as a clock input, and the D type flip-flop. 2. The integrated circuit device according to claim 1, wherein the delay time of the first delay means is set in accordance with the output waveform of the amplifier. 3. The phase difference detecting means includes a first trigger flip-flop that receives the predetermined output clock signal and a second trigger flip-flop that receives the output clock signal of the second delay means. And a logical product means having two inputs of the outputs of these trigger flip-flops, and the delay time of the first delay means is set to the output of the logical product means in accordance with the waveform. The integrated circuit device according to claim 1, wherein: 4. The integrated circuit device according to claim 1, further comprising control signal generation means for generating a control signal for setting a delay time of the first delay means according to the phase difference.