JPS59144927A - Adjusting circuit of timing - Google Patents

Abstract

PURPOSE:To remove the variance of outputs from a delay means and to obtain clock skew reduced at its difference for a short time by forming oscillation circuit loops through the delay means and detecting the difference of frequency between respective oscillation circuit loops. CONSTITUTION:A clock outputted from the oscillation circuit 101 is inputted to a switching circuit 102. The clock is outputted as it is at the time of system operation, and at the time of timing regulation, inverted outputs are outputted from respective delay adjusting circuits 103, 105, 106 and sent to the switching circuit 102 through a coaxial line 104. The output frequency of the oscillation circuit consisting of the switching circuit 102, the delay circuit 103 and the coaxial line 104 is measured by a frequency counter 107 connected from the external. The oscillation circuits including the delay adjusting circuits 105, 106 are similarly measured and respective delay adjusting circuits are finely adjusted so that the outputs of respective oscillation circuits are made equal, so that the clock skew is reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Description of the technical field to which the invention pertains The present invention relates to a timing adjustment circuit for a system operated by a clock.

(2) Description of the prior art Conventionally, in systems that operate using a clock with a constant period as input, clock skew at multiple clock distribution destinations of the system is important in determining system performance, and the clock oscillator output Therefore, it is necessary to equalize the delay at each end of the clock distribution destination. For this reason, conventional methods have been used to reduce clock skew by aligning the number of stages of gate circuits that buffer the clock output to reduce variations in the inverter circuit configuration, or by making the wire lengths the same. . Furthermore, as the system is required to be faster, it is necessary to further reduce clock skew. In this case, conventionally, a delay adjustment circuit is inserted between the clock oscillation output and each clock distribution destination end trench.
Since the clock skew at each terminal was adjusted while observing the waveform, not only did it take a lot of time to adjust, but there was also measurement error and visual error of the waveform observation equipment.
The drawback was that it was not possible to increase the accuracy on a certain board.

(3) Detailed Description of the Invention The purpose of the present invention is to form an oscillation circuit loop for each delay adjustment circuit, measure the oscillation frequency, and reduce the difference between each frequency in order to reduce the clock skew of the system clock. The purpose of this adjustment is to further improve accuracy.

(4) Structure of the Invention The present invention provides a system that operates with a timing output having a constant period as a clock input, and a plurality of adjustable delay means having a clock input with a constant period for operating the system, and a switching means for switching between an input and an inverted output of the delay means and inputting it to the delay means; and a switching means for inputting the inverted output to the delay means by the switching means to adjust the clock skew of the system. It consists of an oscillation circuit formed through the delay means and a counter that measures the output frequency of the oscillation circuit, and when adjusting the clock skew of the system, the oscillation circuit is operated with the inverted output of the delay means and the output frequency is measured by the counter. The present invention is characterized in that the detection is performed to eliminate variations in the output of each delay means.

(5) Detailed Description of the Invention Next, embodiments of the invention will be described in detail with reference to the drawings.

FIG. 1 shows a first embodiment of the present invention.

In FIG. 1, a clock output from a highly stable oscillation circuit 101 is input to a switching circuit 102. The switching circuit 102 outputs a clock during system operation, and outputs each delay adjustment circuit 103 and 105 during timing adjustment.
, 106 are output. Each of the delay adjustment circuits 103, 105, and 106 is constituted by a delay means that can finely adjust the variation in the output of each delay adjustment circuit to within a certain error. The inverted outputs of each delay adjustment circuit 103 , 105 , 106 are sent to a switching circuit 102 via a coaxial line 104 .

The output frequency of the oscillation circuit composed of the switching circuit 102, the delay circuit 103, and the coaxial line 104 is measured by a frequency counter 107 connected from the outside. Similarly, each delay adjustment circuit 105, 106 is connected to the same coaxial line 10 as described above.
4 to form an oscillation circuit in the same manner as described above, and the output frequency of this circuit is measured by a counter 107. Each delay adjustment circuit 103, 105, 10 obtained in this way
Each delay adjustment circuit is finely adjusted so that the outputs of the oscillation circuits including 6 are the same, eliminating variations in the outputs of the circuits, and reducing clock skew. Therefore, according to the first embodiment, since no waveform observation equipment is used, visual errors etc. do not occur, and there is an advantage that error-free clock skew can be achieved in a short period of time.

FIG. 2 shows a second embodiment of the present invention. In FIG. 2, the clock output from the highly stable oscillation circuit 101 is transferred to the switching circuits 102a, 102b, 10.
Enter in 2c. Switching circuits 102a, 102b,
IU2c outputs a clock during system operation, and outputs each delay adjustment circuit 103 and 105 during timing adjustment.
, 106, respectively. Each delay adjustment circuit 103 , 105 , 106
is comprised of a delay means that can finely adjust variations in each output to within a certain error. Each delay adjustment circuit 1
Select two circuits from 03, 105, and 106, and connect the circuits to coaxial lines 104a and 104b having equal lengths.
Switching circuits 102a, 102b, 1 in the same circuit
02c, and an oscillation circuit is constructed by a switching circuit, a delay adjustment circuit, and a coaxial line. The outputs of these two oscillation circuit loops are sent to two counters 107a,
Coaxial lines 108a, 108b with length equal to 107b
The output frequency of each oscillation circuit loop is measured by counters 107a and 107b. The difference between the outputs of each counter 107a and 107b is detected by a detection circuit 109 and displayed. The delay adjustment circuit is finely adjusted based on the displayed position to eliminate variations in the output of the delay adjustment circuit and reduce errors. Similarly, using one oscillation circuit loop as a reference, delay adjustment circuits are successively connected to switching circuits in the same circuit using coaxial lines to form an oscillation circuit, and the output frequency thereof is measured and adjusted. Note that the two oscillation circuit loops formed by connecting each other with coaxial lines 108 and 109 having the same length start oscillation at the same time.

Therefore, according to the second embodiment, since the adjustment is made based on the numerical value displayed on the detection circuit 114, visual errors can be eliminated, unlike waveform observation, and clock skews with small errors can be detected in a single time. There are benefits that can be achieved.

FIG. 3 shows a third embodiment of the present invention. In FIG. In addition to the internal circuit of , there is a detection circuit 109 that detects the difference with the output of the counter 107 in delay block A, and an adjustment circuit 110 that adjusts the delay of the delay adjustment circuit in the same block step by step from the output of the detection circuit 109. The clock output from the highly stable oscillation circuit 101 is input to each delay block.

In this embodiment, when switching to the clock skew adjustment side, the detection circuit detects the difference in the output frequency of the oscillation circuit consisting of the switching circuit, delay adjustment circuit, and coaxial line in each block, and the difference is detected by the detection circuit. Accordingly, the adjustment circuit automatically adjusts the delay of the delay adjustment circuit to eliminate variations in the output of each delay adjustment circuit. Therefore, the third embodiment has the advantage that a clock skew with a small error can be automatically achieved in a short time. The coaxial lines in each delay block must be of equal length, and the lengths from the counter to the detection circuit must also all be equal.

(6) Detailed Description of the Invention As explained above, the present invention forms an oscillation circuit loop through each delay means, detects the difference in frequency of each oscillation circuit loop, and eliminates variations in the output of the delay means. Therefore, compared to the conventional method of adjusting by observing waveforms, it is possible to obtain a clock skew with a smaller error in a single time, and since visual errors can be eliminated, accuracy can be improved.

[Brief explanation of drawings]

1 to 3 are block diagrams showing each embodiment of the present invention. 101... System clock oscillation circuit, 102, 10
2a. 102b...Switching circuit, 103, 105, 1.0
6...Delay adjustment circuit, 104.104a, 104
b-=coaxial line, 107 ... frequency counter, 107
a, 107b... Counter, 1 (19... Detection circuit, 110... Adjustment circuit Patent applicant: NEC Co., Ltd. Patent attorney: Nakadai Kanno) Figure 2 Figure 3

Claims (1)

[Claims] (1) In a system that operates using a timing output with a constant period as a clock input, a plurality of adjustable delay means installed for each clock distribution output in the system, and a timing output with a constant period and the delay means are installed for each clock distribution output in the system. a switching means for inputting the inverted output to the delay means; and a switching means for inputting the inverted output to the delay means to adjust the clock skew of the system. and a counter that measures the output frequency of the oscillation circuit. When adjusting the clock skew of the system, the oscillation circuit is operated in the inverted output direction of the delay means, and the output frequency is detected by the counter. A timing adjustment circuit characterized by eliminating variations in the output of each delay means.