JPH1028110A - Phase difference measuring circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To measure phase difference with high precision by executing correction based on the proportion of respective pulse values held in a pulse value holding part with respect to the pulse value of a reference clock signal after the time for the position of one cycle elapses in a triangular wave output part. SOLUTION: When first and second input signals are inputted to a phase comparator 2, its phase difference signal is inputted to one of AND gates 3 and a reference clock signal is to the other so that the pulse rise is counted by a counter 4. In the respective outputs of integration equipments 6a and 7a, the pulse value is increased with fixed inclination for the portion of one cycle with the pulse rise timing of the reference clock signal as reference. Therefore, the output values of the integration equipments 6a and 7a in the pulse rise and fall timings of the phase difference signal are obtained. Then, a preceding stage correcting circuit 6 recognizes the time before the pulse rise of the phase signal and the time after the pulse fall of the phase signal so that the timings are correctly calculated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to the field of a phase difference measuring circuit for measuring a phase difference by comparing phases between two input signals.

[0002]

2. Description of the Related Art In recent years, for example, in a network synchronization device used in a digital communication device, the phase of a transmission line and a clock signal in the device need to match in order to correctly demodulate received data. Then, the DP is sent to the network synchronization device.
-PLL (Digital Processing- Phase Locked Loop)
In recent years, the use of the method has become common, and high synchronization accuracy is required, and it is necessary to monitor the phase difference between the transmission line and the clock in the device with high accuracy.

Conventionally, for such a purpose, there is a digital phase difference measuring circuit 10 as shown in FIG. 3 as a phase difference measuring circuit for measuring a phase difference. FIG. 3 is a block diagram showing a configuration of a main part of a conventional digital phase difference measuring circuit, and FIG. 4 is a waveform diagram showing an output waveform at each node in FIG.

The digital phase difference measuring circuit 10 comprises a high-frequency oscillator 11, a phase comparator 12, and an AND gate 13.
, A counter 14, and an arithmetic processing circuit 15, which are configured to perform highly accurate phase difference measurement by digitizing the circuit. Further, the counter 14 includes a counter 16 and a decoder 17.

The high-frequency oscillator 11 generates a reference clock signal, and the phase comparator 12 compares the phases by obtaining an exclusive OR between two input signals to indicate a phase difference. It outputs a phase difference signal. The AND gate 13 counts the logical product of the output from the high-frequency oscillator 11 and the output from the phase difference comparator 12 by a counter 14
The counter 14 counts the output from the AND gate 13 by the counter 16, decodes the count result by the decoder 17, and outputs the result to the arithmetic processing circuit 15. The arithmetic processing circuit 15 performs various arithmetic processes based on the output value from the decoder 17.

In the above configuration, the phase comparator 12
When input signals of various types are input, a phase difference signal indicating a phase difference between these input signals is input to one input terminal of the AND gate 13. Thus, the clock signal during which the phase difference signal is “H” is input to the counter 14 as phase data, and the number of clock pulses during this period is counted by the counter 14.

That is, the phase difference between the respective input signals input to the phase comparator 12 can be known from the magnitude of the count value counted by the counter 14, and when the count value is zero, the phase comparator 12 It can be determined that there is no phase difference between the two types of input signals input to.

[0008]

However, due to recent advances in semiconductor technology, the phase difference between input signals to be measured by the above-described phase difference measuring circuit has become small. High precision measurement capability is required. However, in such a conventional digital phase difference measuring circuit, due to its configuration, the only way to increase the measurement accuracy is to increase the oscillation frequency of the high-frequency oscillator 11.

That is, as described above, the digital phase difference measuring circuit 10 measures the phase difference by counting the number of clock pulses during the period when the phase difference signal is "H". Therefore, when the phase difference is shorter than the period of the clock signal, the phase difference cannot be measured.
Therefore, it is necessary to use a clock signal having a shorter cycle, that is, a high oscillation frequency, as a reference clock signal.

However, the phase comparator 12 and the AND gate 1
3. There is an upper limit to the clock frequency that can be used in the counter 14 and the like. If the clock frequency exceeds the upper limit, the operation is not guaranteed.
Further, the counter 16 in the counter 14 has a large number of flip-flops corresponding to the count number, and the number of flip-flops increases as the oscillating frequency increases, resulting in an increase in circuit scale. There was a problem.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems, and to provide a phase difference measuring circuit for measuring a phase difference with high accuracy without increasing the oscillation frequency of a reference clock signal. Is to do.

[0012]

A phase difference measuring circuit according to the present invention compares two input signals and outputs an exclusive OR of these two input signals as a phase difference signal; A counter that counts the number of pulses of the reference clock signal from the pulse rising / falling timing to the pulse falling / rising timing of the phase difference signal output from the comparator; and the phase based on the count value of the counter. A phase difference measuring circuit having a phase difference measuring unit for measuring a phase difference between input signals input to the comparator, wherein a triangular wave whose peak value increases or decreases by a fixed amount with time from a pulse rising timing of a reference clock signal. A first triangular wave output unit for outputting a signal,
A first peak value holding unit that holds a peak value of the triangular wave signal output from the first triangular wave output unit at a pulse rising timing of the phase difference signal output from the phase comparator, and a pulse falling timing of a reference clock signal A second triangular wave output unit that outputs a triangular wave signal whose peak value increases or decreases by a fixed amount with time, and an output from the second triangular wave output unit at a pulse falling timing of a phase difference signal output from the phase comparator. A second peak value holding unit for holding the peak value of the triangular wave signal to be processed, and the first peak value holding unit and the second peak value holding unit for the peak value of the triangular wave output unit after a lapse of one cycle of the reference clock signal. A correction unit that corrects a measurement result by the phase difference measurement unit based on a ratio of each peak value held in the peak value holding unit. It is configured to. At this time, it is effective that the triangular wave output unit is constituted by an integrator having an integration cycle having a maximum value at a time interval of two cycles or more of the reference clock signal.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, the present invention will be described in detail based on one illustrated embodiment. FIG. 1 is a block diagram illustrating a main configuration of a phase difference measurement circuit according to the present embodiment. The phase difference measuring circuit 1 of the present embodiment includes a phase comparator 2, an AND gate 3, a counter 4, and an arithmetic processing circuit 5 serving as a phase difference measuring unit, similarly to the conventional digital phase difference measuring circuit 10 shown in FIG. It has.

Further, the phase difference measuring circuit 1 of the present embodiment
As shown in FIG. 1, a first-stage correction circuit 6 and a second-stage correction circuit 7 each formed by an analog circuit are additionally provided. The phase comparator 2 compares two input signals and outputs an exclusive OR of these two input signals as a phase difference signal. The AND gate 3 outputs a logic value between the reference clock signal and the phase difference signal. The product is output to the counter 4.

The counter 4 counts the number of pulses of the reference clock signal input from the pulse rising timing to the pulse falling timing of the phase difference signal output from the phase comparator 2. The arithmetic processing circuit 5 is provided with a phase comparator 2 based on input information from a counter 4 and a pre-stage correction circuit 6 and a post-stage correction circuit 7 which will be described later.
Is to measure the phase difference of each input signal input to.

The pre-stage correction circuit 6 includes an integrator 6a serving as a triangular wave output unit and a sample hold unit 6 serving as a peak value holding unit.
b, an A / D converter 6c, and a correction value calculation unit 6d serving as a correction unit. Similarly, the post-stage correction circuit 7
An integrator 7a serving as a triangular wave output unit, a sample hold unit 7b serving as a peak value holding unit, an A / D converter 7c,
It comprises a correction value calculation unit 7d serving as a correction unit.

The integrators 6a and 7a output an output signal whose peak value increases by a certain amount with time from the rising timing of the pulse of the reference clock signal, and its integration cycle is two cycles of the reference clock signal. You have set. This is a measure to prevent the output signals of the integrators 6a and 7a from gradually approaching a peak value of a predetermined level with time as shown in FIG. 2, thereby providing a time corresponding to one cycle of the reference clock signal. In the interval, the characteristic of the output signal is made linear.

The sample-and-hold unit 6b includes the phase comparator 2
The sample hold unit 7b holds the peak value of the triangular wave signal output from the integrator 6a at the pulse rising timing of the phase difference signal output from the
It holds the peak value of the triangular wave signal output from the integrator 7a at the falling timing of the pulse of the phase difference signal output from the phase comparator 2. The A / D converters 6c and 7c convert peak value information, which is an analog signal held in the sample and hold units 6b and 7b, into a digital signal.

The correction value calculators 6d and 7d output correction information in the arithmetic processing circuit 5 based on the peak value information (digital signal) output from the A / D converters 6c and 7c. Specifically, each correction value calculation unit 6d,
In 7d, the peak value after a lapse of one cycle of the reference clock signal in the integrators 6a and 7a is known in advance,
By calculating the ratio of the peak value information output from the A / D converters 6c and 7c to the peak value, the phase difference represented by the number of clocks counted by the counter 4 is less than one cycle of the reference clock signal. Is corrected.

Next, the operation of the above embodiment will be described with reference to FIG. FIG. 2 is a waveform diagram showing output waveforms at each node in FIG. In FIG. 2, it is assumed that a first input signal to be measured and a reference second input signal are input to the phase comparator 2 as two input signals.

First, the first input signal and the second input signal are supplied to the phase comparator 2.
When the input signal is input, the phase difference signal is input to one input terminal of the AND gate 3. Since the reference clock signal is input to the other input terminal of the AND gate 3,
The output of the AND gate 3 has a waveform as shown by A in FIG. 2, and the pulse rise of this waveform is counted by the counter 4.

Here, in the actual phase difference signal and the waveform A, the hatched areas indicated by P and E in FIG. This measurement error decreases as the period of the reference clock signal becomes shorter. However, as described above, there is a limit to shortening the period of the reference clock signal. Therefore, in the present embodiment, the pre-stage correction circuit 6 corrects the shaded area P in FIG. 2 and the post-stage correction circuit 7
The correction is performed for the shaded area E.

That is, the outputs of the integrators 6a and 7a are:
In FIG. 2, the waveforms are as shown by B and C, and are set to 1 based on the pulse rising timing of the reference clock signal.
The peak value increases with a constant slope up to the period.
For this reason, when the output values of the integrator 6a and the integrator 7a at the pulse rising timing and the pulse falling timing of the phase difference signal are obtained, the pre-stage correction circuit 6 determines that before the pulse rising of the phase difference signal (shaded area P). The post-stage correction circuit 7 can know the time until the pulse after the pulse of the phase difference signal falls (shaded area E), and accurately calculates the pulse rising timing and the pulse falling timing of the phase difference signal. be able to.

As a result, the phase measuring circuit 1 according to the present embodiment additionally corrects the time of the portion indicated by the hatched area P, and also adds the time indicated by the hatched area E to the conventional example in which only the waveform A can be measured. The time of the part can be deleted and corrected. Therefore, it is possible to measure the phase difference with high accuracy without increasing the oscillation frequency of the reference clock signal, and it is possible to obtain a phase measurement circuit that is effective in the measurement of future semiconductor devices that require high accuracy. it can.

In the above-described embodiment, the case where the pulse rising timing is used as the operation reference point is described. However, when the pulse falling timing is used as the operation reference point in the system design, the operation of each circuit is considered. Only by changing the reference point, it is possible to respond. Further, in the above-described embodiment, the case where an integrator is used as an example of the triangular wave output unit is described as an example. However, the present invention is not limited to this.
It goes without saying that the output level can be changed as long as the output level increases or decreases in proportion to time.

[0026]

As is clear from the above description, according to the present invention, the switching timing at any position of less than one cycle in the reference clock signal can be measured, so that the oscillation frequency of the reference clock signal can be reduced. The phase difference can be measured with high accuracy without increasing the phase difference.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a main configuration of a phase difference measurement circuit according to an embodiment.

FIG. 2 is a waveform chart showing output waveforms at each node in FIG.

FIG. 3 is a block diagram showing a configuration of a main part of a conventional digital phase difference measuring circuit.

FIG. 4 is a waveform chart showing output waveforms at each node in FIG. 3;

[Explanation of symbols]

 Reference Signs List 1 phase difference measurement circuit 2 phase comparator 3 AND gate 4 counter 5 arithmetic processing circuit (phase difference measurement unit) 6 pre-stage correction circuit 6a integrator (triangular wave output unit) 6b sample hold unit (peak value holding unit) 6c A / D converter 6d Correction value calculation unit (correction unit) 7 Post-stage correction circuit 7a Integrator (triangular wave output unit) 7b Sample hold unit (peak value holding unit) 7c A / D converter 7d Correction value calculation unit (correction unit) 10 Digital position Phase difference measuring circuit 11 High frequency oscillator 12 Phase comparator 13 AND gate 14 Counter 15 Arithmetic processing circuit 16 Counter 17 Decoder

Claims (3)

[Claims] 1. A phase comparator for comparing two input signals and outputting an exclusive OR of these two input signals as a phase difference signal, and a pulse rising timing of the phase difference signal output from the phase comparator From the pulse falling timing to the pulse falling timing, or from the pulse falling timing to the pulse rising timing, a counter that counts the number of pulses of the reference clock signal, and each input to the phase comparator based on the count value of the counter. A phase difference measuring circuit for measuring a phase difference of the input signal, wherein a triangular wave signal whose peak value increases or decreases by a certain amount with time from the pulse rising timing or the pulse falling timing of the reference clock signal is obtained. A triangular wave output unit for outputting the phase difference signal output from the phase comparator. A peak value holding unit for holding a peak value of a triangular wave signal output from the triangular wave output unit at a rising edge timing and a pulse falling timing; a peak value after a lapse of one cycle of a reference clock signal in the triangular wave output unit A phase difference measurement circuit, comprising: a correction unit configured to correct a measurement result obtained by the phase difference measurement unit based on a ratio of each peak value held in the peak value holding unit. 2. The phase difference according to claim 1, wherein the triangular wave output section is an integrator that outputs an output signal whose peak value increases by a certain amount with time from the pulse rising timing of the reference clock signal. Measurement circuit. 3. The phase difference measuring circuit according to claim 2, wherein said integrator is set to an integration cycle having a maximum value at a time interval of two cycles or more of a reference clock signal.