JP2003273728A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device having a signal phase control function capable of easily controlling the delay of an output signal due to a deviation in process, a variation in temperature or voltage, or the like and securing stable operation. <P>SOLUTION: The semiconductor device having the signal phase control function between an input and an output for outputting an output signal in which phase is synchronized with that of an external input signal at the time of inputting the input signal is provided with a phase control means and an output signal delay means. The phase control means synchronizes the phase of a 1st signal to be an external input signal with that of a 2nd signal obtained by delaying the input signal by a prescribed delay value. The output signal delay means controls a delay value applied to an output signal on the basis of a control signal to be used when the phases of both the 1st and 2nd signals are synchronized. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having a signal phase adjusting function.

[0002]

2. Description of the Related Art In recent years, with the progress of lower voltage, higher speed and miniaturization of semiconductor devices, it has become more and more difficult to adjust the timing of output signals from the devices because they handle minute signals. For example, data transfer between semiconductor devices is normally performed in synchronization with a clock signal. However, when the clock signal is speeded up, the effective period width of the transfer data becomes narrow, and timing adjustment of the output signal becomes difficult. . To cope with this, in order to properly perform timing adjustment and ensure stable operation, normally in a semiconductor device, the alternating current (A
C) Strict specifications are set for the characteristics. However, the AC characteristics may be affected by fluctuations in the manufacturing process and fluctuations due to temperature and voltage, causing variations, which may hinder data transfer in some cases.

As a cause of malfunctions occurring when data is transferred in synchronization with the same clock signal, for example, defective hold timing between semiconductor devices is considered. In order to avoid such defects, it is necessary to adjust the internal clock of the semiconductor device and the delay of the data line, or to insert a delay element in the data line between the semiconductor devices on the system board.

[0004]

However, a semiconductor device that operates at high speed generally requires a PLL (Phase LockedL).
oop) circuit or DLL (Delay Locked Loop) circuit is used to generate an internal clock. Therefore, it is difficult to adjust the delay of the clock to a specific register inside the It is difficult to dynamically adjust to process fluctuations, temperature and voltage fluctuations, including line adjustments. On the other hand, when the delay element is inserted in the data line between the semiconductor devices on the system board, it can be expected that the system board will be damaged or that the delay other than the delay element will be an obstacle to the high speed operation. Furthermore, when there are many data lines, it is necessary to adjust the number of data lines, and it can be expected that the adjustment work will be complicated.

A conventionally known semiconductor device having a signal phase adjusting function will be described with reference to FIGS. The semiconductor device 80 compares the phase of the input signal with the phase of the output signal, and provides a predetermined delay amount to the input signal based on the comparison result, thereby changing the phase of the output signal. 1 has a variable delay line circuit 81, a phase comparator 82, and a variable delay line control circuit 83. Further, in the semiconductor device 80, the delay time from the input of the external input signal between the output side of the variable delay line circuit 81 and the input side of the phase comparator 82 to the input to the variable delay line circuit 81 ( T1) and the variable delay line circuit 81
It has an internal delay equivalent circuit 84 that provides a delay corresponding to the sum (T1 + T2) of the delay time (T2) from the output to the outside.

Such a circuit configuration for phase adjustment is generally called a DLL circuit. For the purpose of improving the data transfer rate of a semiconductor memory device, for example, DDR (input / output of data twice in one clock cycle) is performed. Double Data Rat
It is used to realize the operation of e) or to supply the same clock signal when supplying the clock signal to each semiconductor device on the system board.

FIG. 8 is a timing chart showing a signal waveform at each point (see FIG. 7) in the semiconductor device 80. The delay time T1 is a delay time generated between the point a and the point b, and the delay time T2 is a delay time generated between the point c and the point e. The delay time by the internal delay equivalent circuit 84 is set to T1 + T2. Here, as shown in FIG. 8, the delay times of T1 and T2 are set to be one graduation and two graduations, respectively. In addition, with respect to the clock signal supplied to the circuit, one clock corresponds to 10 divisions.

The alphabets or numbers attached to the respective waveforms correspond to the respective points in the semiconductor device 80 shown in FIG. 7, and the waveform marked with a is the signal waveform at the point a, and the waveform marked with b. The generated waveform is the signal waveform at point b. Further, the waveforms with d1 to d4 are all waveforms at the point d, and the delay time of the variable delay line circuit 81 is 0.
In the case of, the signal waveform at the point d becomes a waveform with d1 delayed from the point b by the internal delay equivalent circuit (T1 + T2).

In the semiconductor device 80, the phase comparator 82 is arranged so that the signal waveforms at the points b and d coincide with each other.
Sends the comparison result to the variable delay line control circuit 83, and the variable delay line control circuit 83 generates a control signal based on the comparison result and sends it to the variable delay line circuit 81. As a result, the delay time of the signal on the variable delay line changes. The waveforms with d2 to d4 respectively represent the waveforms at the point d that change with the passage of time. In the timing chart shown in FIG. 8, the waveform with d4 is b
Has the same phase as the waveform marked with, and the signal waveform at this point e (the waveform marked with e4) has the same phase as the waveform marked with a, that is, the waveform of the external input signal. It will be.

However, in this semiconductor device 80,
The sum of the delay T1 between the point a and the point b and the delay T2 between the point c and the point e becomes equal to the delay time of the internal delay equivalent circuit 84 due to process fluctuations, fluctuations in temperature, voltage, and the like. Otherwise, the phases of the external input signal and the output signal will not match. As described above, the phase shift between the external input signal and the output signal causes a malfunction of data transfer performed between semiconductor devices. In relation to this, conventionally, some proposals have been made in the internal delay equivalent circuit 84 in order to maintain the delay time at T1 + T2 with respect to fluctuations in the process, fluctuations in temperature and voltage, etc. Also, with additional elements, the circuit becomes complicated and large-scaled.

The following techniques have been proposed as techniques for adjusting the timing of output signals. For example, in Japanese Patent Laid-Open No. 10-269773, the output timing of output data from the data output circuit is controlled from the rising timing of the access clock (m / n) by controlling the variable delay circuit in the DLL circuit.
A semiconductor integrated circuit is disclosed which controls the output timing of output data by setting the timing delayed by the clock cycle time. Also, Japanese Patent Laid-Open No. 2000-1
In Japanese Patent No. 83172, the internal delay reproduction circuit in the DLL circuit is trimmed to optimize its delay amount, thereby making it possible to adjust the internal delay time even for process variations. , DL
A semiconductor device capable of improving the accuracy of an L circuit is disclosed. Further, in Japanese Unexamined Patent Publication No. 2001-60391, there is disclosed a semiconductor device in which a phase adjustment operation of an output data clock signal in a DLL circuit is stopped by a control circuit at the time of data output to suppress generated jitter and speed up data transfer. It is disclosed.

However, these prior arts adopt a configuration in which the timing of the output signal is adjusted by adjusting the phase of the internal clock signal generated in the DLL circuit in the device or adjusting the timing of the clock signal. Therefore, for process fluctuations, fluctuations in temperature, voltage, etc.,
It is not possible to avoid the inconvenience of deviation from the specified timing.

The present invention has been made in view of the above technical problems, and the timing is easily adjusted for the fluctuation of the hold time of the output data due to the fluctuation of the process and the fluctuation of temperature, voltage, etc. It is an object of the present invention to provide a semiconductor device having a signal phase adjusting function capable of ensuring the above operation.

[0014]

The invention according to claim 1 of the present application provides an input-output signal phase adjusting function for outputting an output signal phase-synchronized with the input of an external input signal. In a semiconductor device provided, phase adjusting means for synchronizing a phase between a first signal which is an input signal from the outside and a second signal obtained by delaying the input signal by a predetermined delay amount; An output signal delay means for delaying an output signal to the outside, which is given to the output signal based on a control signal used when the phase adjustment means synchronizes the phases of both signals. And an output signal delay means for adjusting the delay amount.

The invention according to claim 2 of the present application is the invention according to claim 1, wherein the phase adjusting means delays the input signal by a delay amount determined based on the control signal. The first signal and the second signal that has passed through the delay means are input, and based on the comparison result by the phase comparison means for comparing the phases between the two signals, the phase comparison means,
And a control signal generation means for generating a control signal to be supplied to the delay means, the output signal delay means, based on the control signal generated by the control signal generation means,
It is characterized in that the delay amount given to the output signal from the inside of the device to the outside is adjusted.

Further, the invention according to claim 3 of the present application is, in the invention according to claim 2, in respect of a signal input between the output side of the delay means and the input side of the phase comparison means. A delay element that gives a predetermined delay amount is replaceably attached, and the delay amount given to the second signal is variable.

Furthermore, the invention according to claim 4 of the present application is the invention according to claim 2 or 3, wherein the output signal delay means has the same configuration as the delay means in the phase adjusting means. The delay means is characterized by adjusting the delay amount to be added to the output signal to the outside based on the control signal generated by the control signal generating means.

Further, the invention according to claim 5 of the present application is the input signal delay means for delaying an input signal from the outside to the inside of the device according to any one of the inventions according to claims 1 to 4. And an input signal delay means for adjusting a delay amount given to the input signal based on a control signal used when the phase adjustment means synchronizes the phases of the two signals. It is characterized by.

[0019]

DETAILED DESCRIPTION OF THE INVENTION Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram showing a circuit configuration for phase adjustment incorporated in a semiconductor device according to an embodiment of the present invention and a delay setting element added outside the device. This semiconductor device 10 has a variable delay line circuit 3, a phase comparator 4, a variable delay line control as a typical configuration of a signal phase adjusting function for receiving an input signal from the outside and generating an output signal in synchronization with the signal. The circuit 5 is provided. As these configurations, the configuration for phase adjustment in the semiconductor device 80 (see FIG. 8) described above as a conventional technique can be used, but in order to clearly show the present embodiment in detail, FIGS. Specific configurations of the variable delay line circuit 3 and the variable delay line control circuit 5 are shown respectively. The "variable delay line circuit", "phase comparator", and "variable delay line control circuit" are the "delay means", "phase comparison means", and "control signal generation means" described in the claims, respectively. It corresponds to.

As can be seen from FIG. 2, the variable delay line circuit 3
Has a basic configuration in which a plurality of delay lines 3a that cause different delay times for input signals and a plurality of delay elements 3b provided in series for each delay line 3a are provided.
And a selector 3 for selecting one from the plurality of delay lines 3a
c and. By providing a different number of delay elements 3b in series for each delay line 3a, a different delay time is provided for an input signal for each delay line. For example, the delay line 3a corresponding to the terminal D2 of the selector 3c is provided with two delay elements 3b, and the delay line 3a corresponding to the terminal D4 of the selector 3c is provided with four delay elements 3b. To be Therefore, the delay line 3a corresponding to the terminal D4 provides the input signal with a delay time twice as long as that of the delay line 3a corresponding to the terminal D2. The delay element 3b is not provided in the delay line 3a corresponding to the terminal D0 of the selector 3c,
When this delay line 3b is selected, the input signal is output from the variable delay line circuit 3 without being delayed. The selector 3c selects one of the delay lines based on the control signal sent from the variable delay line control circuit 5, and outputs the signal without delaying it or delaying it for a predetermined time. To do.

On the other hand, as can be seen from FIG. 3, the variable delay line control circuit 5 includes an up / down counter (UP / down counter in the figure).
DOWN counter), each receives an up / down signal representing the comparison result by the phase comparator 4, and based on this up / down signal,
A control signal to be sent to the variable delay line circuit 3 is generated. That is, the delay line 3a selected on the variable delay line circuit 3 side is determined by the control signal generated here.

Further, as shown in FIG. 1, the semiconductor device 10
Is an external terminal related to the circuit configuration for position adjustment,
External terminal a1 which is an input terminal for a clock signal from the outside
And an external terminal k1 which is a terminal for outputting data to the outside,
It has an external terminal c1 electrically connected to the output side of the variable delay line circuit 3 and an external terminal d1 electrically connected to the input side of the phase comparator 4 via a line e1. In this embodiment, with respect to the semiconductor device 10, the delay setting element 20 which is connected between the external terminals c1 and d1 and provides a predetermined delay time to a signal passing from the terminals c1 to d1.
Is attached.

In the semiconductor device 10 having the above structure,
Signal (clock signal) input through the external terminal a1
After passing through the line b1 via the buffer 2, it is input to the variable delay line circuit 3 and the phase comparator 4. The signal input to the variable delay line circuit 3 is output without being delayed or after being delayed by a predetermined time based on the control signal from the variable delay line control circuit 5. Further, the phase comparator 4 has lines b1 and e1 connected to the input side thereof, and in operation, after being output from the variable delay line circuit 3 together with the signal (first signal) passing through the line b1. , The signal (second signal) via the line e1 is input. The phase comparator 4 compares the first signal and the second signal, and sends an up / down signal representing the comparison result to the variable delay line control circuit 5 via the line g1.

Hereinafter, the clock cycle time of the first signal is "10", the delay time of the buffer 2 is "1", and the count values (S2, S1, S0) of the variable delay line control circuit 5 are (0,
0, 0), one delay element 3b in the variable delay line circuit 3
Assuming a condition that the delay time by (assuming that all delay elements 3b bring the same delay time) is “1” and the delay time by the external delay setting element 20 is “7”,
The operation of the device will be described.

FIG. 4 shows a signal waveform at each line or point (see FIG. 1) of the semiconductor device 10 when the position is adjusted under the above-mentioned conditions. The clock signal input from the outside is delayed by the delay time “1” in the buffer 2, and the signal waveform on the line b1 becomes a waveform with b1. On the other hand, regarding the signal input to the variable delay line circuit 3 after passing through the buffer 2, first, the count value (S2, S1,
Since S0) is (0, 0, 0), the selector 3c of the variable delay line circuit 3 selects the delay line 3a having the delay time “0” corresponding to the terminal D0. Further, the signal is delayed by the delay time “7” by passing through the delay setting element 20 after the output from the variable delay line circuit 3. In this case, since the total delay time relative to the signal represented by the signal waveform with b1 is "7", the signal waveform with line e1 is the waveform with e1-0.

The phase comparator 4 detects that the phases of the signals input from the respective lines do not match, and sends a count-up signal to the variable delay line control circuit 5. The variable delay line control circuit 5 counts up and resets the count value to (0, 0, 1). In response to this, the selector 3c of the variable delay line circuit 3 selects the delay line 3a having the delay time "1" corresponding to the terminal D1. Further, after the output from the variable delay line circuit 3, the signal is delayed by the delay setting element 20 by the delay time “7”. In this case, since the total delay time relative to the signal represented by the signal waveform with b1 is "8", the signal waveform with line e1 is the waveform with e1-1.

Subsequently, the phase comparator 4 detects that the phases of the signals input from the respective lines do not match, and sends a count-up signal to the variable delay line control circuit 5. The variable delay line control circuit 5 counts up and resets the count value to (0, 1, 0). In response to this, the selector 3c of the variable delay line circuit 3 selects the delay line 3a having the delay time “2” corresponding to the terminal D2. Further, after the output from the variable delay line circuit 3, the signal is delayed by the delay setting element 20 by the delay time “7”. In this case, since the total delay time relative to the signal represented by the signal waveform with b1 is “9”, the signal waveform with line e1 is the waveform with e1-2.

Further, subsequently, the phase comparator 4 detects that the phases of the signals input from the respective lines do not match, and sends a count-up signal to the variable delay line control circuit 5. The variable delay line control circuit 5 counts up and resets the count value to (0, 1, 1).
In response to this, the selector 3c of the variable delay line circuit 3 selects the delay line 3a having the delay time “3” corresponding to the terminal D3. Further, after the output from the variable delay line circuit 3, the signal is delayed by the delay setting element 20 by the delay time “7”.
In this case, since the total delay time relative to the signal represented by the signal waveform with b1 is "10", the line e
As the signal waveform in 1, a waveform with e1-3 is obtained. The waveform marked with e1-3 has the same phase as the waveform marked with b1. In response, the phase comparator 4 detects that the phases match and stops the up / down signal.

Next, consider a case where there is a process fluctuation, a change in temperature, a voltage, etc., and the delay time by one delay element 3b in the variable delay line circuit 3 is "1.5". FIG. 5 is a timing chart showing the signal waveform at each line or point of the semiconductor device 10 in this case. The clock signal input from the outside is delayed by the delay time “1” in the buffer 2, and the signal waveform in the line b1 becomes a waveform with b1 added, as in the case shown in FIG. On the other hand, regarding the signal input to the variable delay line circuit 3 after passing through the buffer 2, first, the count value (S2, S1, S0) of the variable delay line control circuit 5
Is (0,0,0), the selector 3c of the variable delay line circuit 3 selects the delay line 3a having the delay time "0" corresponding to the terminal D0. Further, the signal is delayed by the delay time “7” by passing through the delay setting element 20 after the output from the variable delay line circuit 3. In this case, as the signal waveform on the line e1, a waveform with e1-0 is obtained.

The phase comparator 4 detects that the phases do not match and sends a count-up signal to the variable delay line control circuit 5. The variable delay line control circuit 5 counts up and resets the count value to (0, 0, 1). In response to this, the selector 3c of the variable delay line circuit 3 has the terminal D
The delay line 3a corresponding to 1 is selected. In this delay line 3a, delay time "1.5" is brought about by one delay element 3b. At this time, as the signal waveform on the line e1, a waveform with e1-1 is obtained.

Subsequently, the phase comparator 4 detects that the phases do not match and sends a count-up signal to the variable delay line control circuit 5. The variable delay line control circuit 5 counts up and resets the count value to (0, 1, 0). In response to this, the selector 3c of the variable delay line circuit 3 is
The delay line 3a corresponding to the terminal D2 is selected. In this delay line 3a, the delay time "3" is brought about by the two delay elements 3b. At this time, as the signal waveform on the line e1, a waveform with e1-2 is obtained. This e
The waveform labeled with 1-2 will have the same phase as the waveform labeled with b1. In response to this, the phase comparator 4
Detects that the phases match and stops the up / down signals. Further, in this case, the count value of the variable delay line control circuit 5 is also held at (0, 1, 0).

As can be seen from the above, the delay time in the variable delay line circuit 3 in the case where the input signal and the output signal have the same phase is subject to process fluctuations, fluctuations in temperature, voltage, etc. Without being affected, “clock cycle time−delay time by the external delay setting element 20 (1
0-7 = 3) ". On the other hand, the count values (S2, S1, S0) of the variable delay line control circuit 5 that realizes the delay time change with respect to process fluctuations and changes in temperature, voltage, and the like. That is, when the delay time by the delay element 3b of the variable delay line circuit 3 is set to X under a predetermined condition, the delay time by the external delay setting element 20 is set to "clock cycle time-X". Of course, this is the same as that the count value of the variable delay line circuit 3 under that condition represents the delay time X.

A more detailed description will be given. The delay time from the input of the external input signal to the semiconductor device 10 through the external terminal a1 to the input of the variable delay line circuit 3 is T1, and the delay time by the external delay setting element 20 is T1. Further, the clock cycle time of the input signal is R. In this case, the signal waveform on line b1 and line e
The delay time by the variable delay line circuit 3 at the time when the phases of the signal waveforms in 1 are the same is R-T1. The state of the control signal transmitted from the variable delay line control circuit 5 to the variable delay line circuit 3 at this time is S [R-T1].

Next, when the delay time by the external delay setting element 20 is changed to T2, the delay time by the variable delay line circuit 3 at the time when the phases of the external input signal and the output signal match is R-. T2, and the state of the control signal transmitted from the variable delay line control circuit 5 to the variable delay line circuit 3 at this time is S [R-T2]. Similarly, if the delay time by the external delay setting element 20 is changed to T3, the delay time by the variable delay line circuit 3 at the time when the phases of the external input signal and the output signal match is R-T3,
The state of the control signal transmitted from the variable delay line control circuit 5 to the variable delay line circuit 3 at this time is S [R-T3].

As described above, by changing the delay time by the external delay setting element 20, the delay time by the variable delay line circuit 3 at the time when the phases of the external input signal and the output signal match each other is changed. The Rukoto. For example, when the clock cycle time is 10 [ns] and the delay time of 1 [ns] is to be set in the variable delay line circuit 3, the delay time by the external delay setting element 20 is 1 [ns].
Set to. As a result, the delay time of 1 [ns] can be reliably realized in the variable delay line circuit 3 even when process fluctuations, temperature or voltage fluctuations occur. In other words, under any condition, the variable delay line control circuit 5 can generate a control signal that allows the variable delay line circuit 3 to provide a desired delay time. That is,
This control signal is synonymous with the absolute value of the delay time by the variable delay line circuit 3.

As shown in FIG. 1, the semiconductor device 10 includes:
In addition to the above-mentioned configuration, an internal circuit 11 and an output data variable delay line circuit 12 are included. The internal circuit 6 acts as an output section in the semiconductor device 10, and the “h” shown in FIG.
“1” represents one output signal line connected to the internal circuit 6. As a conventionally known configuration, it is general that the output signal line is guided to the outside and the output signal that has passed therethrough becomes the output data as it is. However, in the semiconductor device 10, the output from the internal circuit 11 is output. The signal is further input to the output data variable delay line circuit 12. The output data variable delay line circuit 12 may be the same as the variable delay line circuit 3 shown in FIG. This "variable delay line circuit for output data"
Corresponds to "output signal delay means" described in the claims.

During operation, the output data variable delay line circuit 12 receives the output signal from the internal circuit 11 and
The control signal sent from the variable delay line control circuit 5 via the line f1 (that is, the count value (S2, S1, S
0)) is input. This makes it possible to select the delay time provided by the variable delay line circuit 3.
As a result, the signal input to the output data variable delay line circuit 12 through the line h1 is delayed by the same time as the delay time of the variable delay line circuit 3 and then output.

According to such a configuration, for example, when the output signal to the outside is delayed by the delay time “3”, the delay time by the external delay setting element 20 is set to “7”, Even under the conditions, the output signal to the outside can be delayed by the delay time “3”.

Further, regarding the plurality of delay elements (not shown) included in the output data variable delay line circuit 12, if the delay time by each delay element is set to all "0.1", the delay time is 1/10 of the delay time by the variable delay line circuit 3 even for fluctuations, fluctuations in temperature or voltage, etc.
(That is, the delay value changes proportionally). That is, when the output signal to the outside is delayed by the delay time "3", the delay time by the output data variable delay line circuit 12 becomes "0.3", and it is possible to perform finer delay adjustment. . As a result, the output data variable delay line circuit 12 can be adjusted more precisely than the delay time realized by the variable delay line circuit 3. Note that FIG.
In the above, only one output signal line connected to the external terminal k1 is shown on the output side of the output data variable delay line circuit 12, but the present invention is not limited to this, and if necessary,
A variable delay line circuit for output data having a plurality of output signal lines may be used.

As described above, in the semiconductor device 10,
Even when the conditions change due to fluctuations in the process, temperature, voltage, etc., the delay time of the output data can be adjusted based on the result obtained from the internal phase adjusting structure. This will be described in more detail. For example, assuming that the delay time by the variable delay line circuit 3 is T at the time when the first signal and the second signal are synchronized under two conditions A and B in which the process, temperature, voltage, etc. are different, As a matter of course, the delay element 3b passing through in the variable delay line circuit 3
The number of is different. As an example, even if each delay element 3b in the variable delay line circuit 3 causes a delay time of T / 10 under the condition A, it does not exceed T / T under the condition B.
In this case, in order to realize the delay time T, 10 stages of delay elements 3b are required under the condition A, while under the condition B, 9 stages of the delay elements are required. 3b is required. This means that the control signal generated from the variable delay line control circuit 5 detects the difference between the condition A and the condition B in the form of the number of passage stages of the delay element 3b that causes a predetermined delay time. That is, by using this control signal as a signal for controlling the delay time of the output data to the outside in the output data variable delay line circuit 12, the control by the absolute value amount set for the delay amount under a predetermined condition can be performed. It will be possible. As a result, the semiconductor device 10 can easily adjust the delay with respect to the output signal and secure a stable operation even when a process fluctuation or a change in temperature, voltage, or the like occurs.

Next, FIG. 6 is a block diagram showing a semiconductor device having a signal phase adjusting function according to another embodiment of the present invention. In the following, the same components as those in the above-described embodiment are designated by the same reference numerals, and further description will be omitted. In the above-described embodiment, the control signal from the variable delay line control circuit 5 is input to the output data variable delay line circuit 12 via the line f1 (see FIG. 1), but in this embodiment, the semiconductor is used. Device 30
However, as shown in FIG. 6, the input data variable delay line circuit 32 receives the external input data input from the external terminal a2 and the control signal from the variable delay line control circuit 5.
have. This input data variable delay line circuit 32
Has the same configuration as the output data variable delay line circuit 12. The "input data variable delay line circuit" corresponds to the "input signal delay means" described in the claims.

In this semiconductor device 30, the input data variable delay line circuit 32 performs delay adjustment on the external input data, so that the line i1 is transferred to the internal circuit 11.
It is possible to perform phase adjustment by controlling the delay time with respect to the signal input via the same as in the case of performing the output signal in the above-described embodiment. This makes it possible to adjust the setup / hold time of the input signal. Although only one input data line connected to the external terminal a2 is shown on the input side of the input data variable delay line circuit 32 in FIG. 6, the input data line is not limited to this and may be provided as necessary. Alternatively, an input data variable delay line circuit having a plurality of input data lines may be used.

Needless to say, the present invention is not limited to the illustrated embodiments, and various improvements and design changes can be made without departing from the gist of the present invention.

[0044]

As is apparent from the above description, according to the invention of claim 1 of the present application, the first signal which is an external input signal and the input signal are delayed by a predetermined delay amount. The amount of delay given to the output signal from the inside of the device to the outside based on the control signal used at the time when the phase is synchronized between the two signals while the phase is synchronized with the second signal. Therefore, even when process fluctuations, temperature or voltage fluctuations, etc. occur, delay adjustment for the output signal can be easily performed, and stable operation of the device can be ensured.

According to the invention of claim 2 of the present application, the delay means for delaying the input signal by the delay amount determined based on the control signal, and the second signal passing through the first signal and the delay means. Is provided, and phase comparison means for comparing the phases of both signals and control signal generation means for generating a control signal to be supplied to the delay means based on the comparison result by the phase comparison means are provided. Based on the control signal generated by the generation means, in order to adjust the delay amount given to the output signal from the inside of the device to the outside, by using the control signal representing the delay amount set by the delay means,
The delay adjustment for the output signal can be performed easily and accurately.

Further, according to the invention of claim 3 of the present application, a delay for giving a predetermined delay amount to an input signal between the output side of the delay means and the input side of the phase comparison means. Since the elements are replaceably attached and the delay amount given to the second signal is variable, the delay amount set by the delay means can be arbitrarily set by the delay setting element.

Further, according to the invention of claim 4 of the present application, the delay means having the same structure as the above-mentioned delay means is used for delay adjustment for the output signal, and the delay means is
Since the delay amount added to the output signal to the outside is adjusted based on the control signal generated by the control signal generating means, the delay adjustment for the output signal can be easily performed.

Further, according to the invention of claim 5 of the present application, the input signal delay means for delaying the input signal from the outside to the inside of the apparatus is provided, and the phase adjustment means synchronizes the phases of both signals. The amount of delay given to the input signal is adjusted based on the control signal used at the time taken, so that the delay with respect to the input signal even when process fluctuations, fluctuations in temperature, voltage, etc. occur. Easy adjustment amount,
It is possible to ensure stable operation of the device.

[Brief description of drawings]

FIG. 1 is a block diagram showing a semiconductor device having a signal phase adjusting function according to an embodiment of the present invention.

FIG. 2 is a diagram showing a specific configuration of a variable delay line circuit.

FIG. 3 is a diagram showing a specific configuration of a variable delay line control circuit.

FIG. 4 is a timing chart showing a signal waveform in each line or point in the semiconductor device when the delay time by one delay element in the variable delay line circuit is “1”.

FIG. 5 is a timing chart showing a signal waveform in each line or point in the semiconductor device when the delay time by one delay element in the variable delay line circuit is “1.5”.

FIG. 6 is a block diagram showing a semiconductor device having a signal phase adjusting function according to another embodiment of the present invention.

FIG. 7 is a block diagram showing a conventionally known semiconductor device having a signal phase adjusting function.

FIG. 8 is a timing chart showing a signal waveform at each point in a conventional semiconductor device.

[Explanation of symbols]

3 ... Variable delay line circuit 3a ... delay line 3b ... delay element 3c ... selector 4 ... Phase comparator 5 ... Variable delay line control circuit 10, 30 ... Semiconductor device 11 ... Internal circuit 12 ... Variable delay line circuit for output data 20 ... Delay setting element 32 ... Variable delay line circuit for input data

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) H03K 5/13 F term (reference) 5B079 BC03 CC02 CC16 DD08 DD13 5F038 CD09 DF01 DT12 EZ20 5J001 AA11 BB00 BB14 BB22 CC03 DD02 DD03 DD09 5J106 AA04 CC21 CC59 DD09 DD19 DD24 DD31 DD46 KK12 5M024 AA24 AA40 AA92 AA93 BB04 BB27 BB33 BB34 DD40 DD60 DD83 GG01 GG06 JJ03 JJ34 JJ38 PP01 PP07

Claims (5)

[Claims] 1. A semiconductor device having an input-output signal phase adjusting function for outputting an output signal phase-synchronized with an input signal of an external input signal, wherein the input signal is an external input signal. Phase adjustment means for synchronizing the phase between one signal and a second signal obtained by delaying the input signal by a predetermined delay amount; and output signal delay means for delaying the output signal from the inside of the device to the outside. And an output signal delay means for adjusting the delay amount given to the output signal based on a control signal used at the time when the two signals are synchronized in phase in the phase adjustment means. A semiconductor device characterized in that 2. The phase adjusting means receives a delay means for delaying an input signal by a delay amount determined on the basis of the control signal, and a first signal and a second signal passing through the delay means. The output signal delay means includes a phase comparison means for comparing the phases of the signals and a control signal generation means for generating a control signal to be supplied to the delay means based on a comparison result by the phase comparison means. 2. The semiconductor device according to claim 1, wherein the delay amount given to the output signal from the inside of the device to the outside is adjusted based on the control signal generated by the control signal generating means. 3. A delay element, which gives a predetermined delay amount to an input signal, is replaceably mounted between the output side of the delay means and the input side of the phase comparison means. The semiconductor device according to claim 2, wherein a delay amount given to the second signal is variable. 4. The output signal delay means has a delay means having the same configuration as the delay means in the phase adjusting means, and the delay means applies the control signal generated by the control signal generating means. The amount of delay added to the output signal to the outside is adjusted based on the above.
Or the semiconductor device according to 3. 5. An input signal delay means for delaying an input signal from the outside to the inside of the apparatus, wherein the phase adjusting means is based on a control signal used when the phases of both signals are synchronized by the phase adjusting means. 5. The semiconductor device according to claim 1, further comprising an input signal delay unit that adjusts a delay amount given to the input signal.