JPH06232699A - Pulse generator - Google Patents

Abstract

PURPOSE:To generate a pulse whose minimum pulse width is decided with a simpler hardware configuration. CONSTITUTION:An adder 1 adds a fixed value (d) corresponding to a minimum pulse width and a prescribed setting value (n) given externally and gives the sum to a coincidence detection circuit 3. A trigger pulse being a trigger signal is used to reset a counter 2 and to set an RS flip-flop 4. The counter 2 counts up pulses of clock signals starting from a count value zero by the resetting. When the count of the counter 2 is coincident with the sum (d+n) by the adder 1, the coincidence detection circuit 3 outputs a signal to reset the flip-flop 4. The flip-flop 4 outputs a pulse rising at the point of time when a trigger pulse is received and a falling pulse at the point of time when the coincidence is detected.

Description

Detailed Description of the Invention

[0001]

FIELD OF THE INVENTION This invention relates to pulse generators, and in particular to
The present invention relates to a device for generating a pulse having a minimum pulse width.

[0002]

2. Description of the Related Art When electronically controlling a fuel injection system of an engine, it is necessary to generate a pulse having a predetermined width based on a predetermined digital value. For example, Japanese Patent Publication No. 62-4307
Japanese Unexamined Patent Publication 0 discloses a pulse generator for controlling fuel injection of an engine. A minimum pulse width is often set for the pulse used for such engine control. However, in order to generate a pulse having a defined minimum pulse width, hardware such as a register that stores a digital value corresponding to the minimum pulse width is required. In engine fuel injection control and the like, it is desired to reduce the number of external terminals and the number of bits of a counter as much as possible to reduce the scale of hardware. So, in the conventional general pulse generator for engine control,
A circuit in which two counters are prepared, the first counter counts up to a digital value corresponding to the minimum pulse width, and then the second counter starts counting to reach a predetermined set value. The composition is adopted.

[0003]

However, in order to operate the counter, various circuits that operate in a linked manner are required, and if two counters are used, the hardware becomes complicated accordingly. In particular, when a timer device incorporating a single-chip microcomputer is used as a counter, two chips must be used, and existing counter resources cannot be effectively used.

Therefore, an object of the present invention is to provide a pulse generator capable of generating a pulse having a minimum pulse width defined by a simpler hardware configuration.

[0005]

According to the present invention, in a pulse generator which outputs a pulse having a pulse width corresponding to a given set value at a timing corresponding to a given trigger signal, a minimum pulse width is set. An adder that adds the corresponding predetermined fixed value and the given set value, a counter that starts counting for a predetermined clock signal in synchronization with the trigger signal, and the count value of the counter is the addition result by the adder. A match detection circuit that outputs a match detection signal indicating a match, and a pulse output circuit that outputs a pulse having a leading edge synchronized with the trigger signal and a trailing edge synchronized with the match detection signal are provided. is there.

[0006]

[Operation] The basic idea of the present invention is that an adder is used in place of one of the counters in a pulse generator which has conventionally been configured using two counters. For example, when a pulse having a defined minimum pulse width d is generated, in the conventional pulse generator, as described above, the first counter counts up to the digital value d corresponding to the minimum pulse width. , The operation of starting the counting of the second counter and counting up to a predetermined set value n has been performed. On the other hand, in the present invention, an adder is provided instead of the first counter, the digital value d corresponding to the minimum pulse width and the predetermined set value n are added, and the added value (d + n ) Is performed. Compared to the counter, the adder has a relatively simple hardware configuration. Therefore, the hardware configuration of the device of the present invention is simplified as compared with the conventional device using two counters.

[0007]

The present invention will be described below based on illustrated embodiments. FIG. 1 is a block diagram showing the basic configuration of a pulse generator according to an embodiment of the present invention. This device adds a predetermined fixed value d corresponding to the minimum pulse width with a given set value n, and starts counting for a given clock signal in synchronization with a given trigger signal. The counter 2, the coincidence detection circuit 3 that outputs a coincidence detection signal indicating that the count value of the counter 2 coincides with the addition result (d + n) by the adder 1, the front edge synchronized with the trigger signal, and the coincidence detection signal A pulse output circuit 4 for outputting a pulse having a synchronized trailing edge.

Here, more specifically, an example in which an arbitrary 6-bit value is prepared as the set value n and the fixed value d = 8 will be described. The adder 1 adds the given 6-bit set value n and the fixed value d (= 8), and outputs the addition result (d + n) as 7-bit (6-bit set value and fixed value “8”). The signal is set to 7 bits in consideration of the carry due to the addition of 1) and is given to one input terminal of the coincidence detection circuit 3. On the other hand, the counter 2 is a 7-bit counter,
When the pulse input of the trigger signal is received, the count value is reset to 0 and the counting operation (count up operation) of the pulse number of the clock signal is started. Then, the coincidence detection circuit 3 uses the count value as a 7-bit signal.
To the other input terminal of. The match detection circuit 3 is 2
When the signal values given to the two input terminals match, a match detection signal is output. The pulse output circuit 4 is composed of an RS flip-flop in this embodiment,
A trigger signal is given to the set terminal S, and a coincidence detection signal is given to the reset terminal R. Therefore, the pulse output circuit 4 outputs a pulse having a front edge synchronized with the trigger signal and a rear edge synchronized with the coincidence detection signal. In other words, the pulse width of the output pulse from the pulse output circuit 4 corresponds to the time from the time when the trigger signal is given to the time when the match detection circuit 3 detects the match.

The set value n is, for example, as shown in FIG.
It is prepared by the circuit shown in (b). Figure 2 (a)
Is a setting circuit that clamps the signal line. By selectively connecting either + 5V or GND to each of the six signal lines, a 6-bit setting value n
Can be prepared. In FIG. 2B, digital data output to a data bus of an external microcomputer or the like is written in a register as it is, and the data in this register is set as a set value n. The setting value n may be prepared by any other method.

Next, the operation of this device will be described with reference to the block diagram shown in FIG. 1 and the time chart shown in FIG. Here, the operation when the set value n = 4 is given will be described as an example. Now, consider a case where a set value of n = 4 is given at time t0. The adder 1 adds the given set value n and the fixed value d. If the fixed value d = 8, the addition result of (d + n) = 12 is obtained as the output of the adder 1. Here, it is assumed that the trigger signal rises at time t1. This trigger signal causes the 7-bit counter 2 to start counting and sets the pulse output circuit (RS flip-flop) 4. Therefore, the counter 2 has the time t
The counting of the clock signal is started from 1 and the pulse output circuit 4 outputs a pulse rising at time t1. Since the addition result “12” output from the adder 1 is given to one input terminal of the match detection circuit 3, a match occurs at the time when the count value of the 7-bit counter 2 matches “12”, that is, at time t3. The detection circuit 3 outputs a coincidence detection signal. Since this coincidence detection signal resets the pulse output circuit 4, the output of the pulse output circuit 4 falls at time t3. In this way, the pulse output circuit 4 outputs a pulse having a pulse width corresponding to (d + n) = 12. Then, at time t4, when the trigger signal rises again, the same operation is repeated to output the next pulse.

The minimum pulse width of the pulse output from this circuit is determined by the fixed value d. That is, when the set value n = 0 is given, the addition result output of the adder 1 becomes the fixed value "8", and the pulse output falls at the time t2 when the counter 2 counts to 8. As described above, in this circuit, the time width corresponding to the fixed value d is set as the minimum pulse width, and the pulse having the pulse width according to the arbitrary set value n that can be represented by 6 bits is synchronized with the trigger signal. It can be generated at timing. Moreover, the counter used is only the 7-bit counter 2,
The hardware structure is simplified as compared with the conventional pulse generator using two counters. Further, the signal line for supplying the set value n requires only 6 bits as in the conventional device.

The present invention has been described above based on the illustrated embodiment, but the present invention is not limited to this embodiment and can be implemented in various modes other than this. In particular, the specific number of bits in the illustrated embodiment is an example, and the number of bits to be set for each can be appropriately determined by design. Moreover, although the RS flip-flop is used as the pulse output circuit 4 in the above-described embodiment, another element may be used as long as it has an equivalent function.

[0013]

As described above, according to the pulse generator of the present invention, the fixed value corresponding to the minimum pulse width is added to the predetermined set value given from the outside, and the addition result and the count value of the counter are added. Since the pulse is generated by comparing the above, it is possible to generate the pulse having the minimum pulse width determined by a simple hardware configuration.

[Brief description of drawings]

FIG. 1 is a block diagram showing a basic configuration of a pulse generator according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a circuit example for preparing a set value n to be given to the pulse generator shown in FIG.

FIG. 3 is a time chart explaining the operation of the pulse generator shown in FIG.

[Explanation of symbols]

 1 ... Adder 2 ... 7-bit counter 3 ... Match detection circuit 4 ... Pulse output circuit (RS flip-flop) d ... Fixed value (minimum pulse width) n ... Set value

Claims (1)

[Claims] 1. A pulse generator for outputting a pulse having a pulse width according to a given set value at a timing according to a given trigger signal, and a predetermined fixed value corresponding to a minimum pulse width and the above-mentioned fixed value. An adder that performs addition with a set value, a counter that starts counting for a predetermined clock signal in synchronization with the trigger signal, and a match detection that indicates that the count value of the counter matches the addition result of the adder. A pulse generator, comprising: a coincidence detection circuit that outputs a signal; and a pulse output circuit that outputs a pulse having a leading edge synchronized with the trigger signal and a trailing edge synchronized with the coincidence detection signal. .