JP3637510B2 - Fault monitoring method and circuit - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
Even if a transient failure is detected in various communication devices, etc., the present invention does not immediately consider it as a failure occurrence, but only when the failure detection frequency reaches a predetermined frequency. The present invention relates to a failure monitoring method and a circuit thereof which are determined as occurrences.
[0002]
[Prior art]
In various communication systems and communication devices in general, even if any failure is detected from a signal from the outside of the communication device, or if any failure is detected inside the communication device, the entire system or communication In order to ensure the reliability as a device, the redundant configuration is adopted for the configuration of each signal transmission system and communication device. When a failure occurs, the active system configuration is switched to the standby system configuration and The standby system configuration that has been in the standby state is switched to a new active system configuration.
[0003]
Here, taking a specific example as an example, the system switching operation will be described in detail. For example, in FIG. 4 of Japanese Patent Laid-Open No. 3-66240, the prior art used in a synchronous terminal device or the like is used. The configuration of the clock switching circuit according to FIG. 3 is shown. The system switching operation when a clock failure occurs will be described with reference to FIG.
That is, the N system (working system) clock input from the outside of the apparatus is branched in two directions, and is input to a well-known phase locked loop (PLL) circuit and a clock break detection circuit, respectively. Similarly, the E system (standby system) clock input is branched in two directions, and is input to the phase-locked loop circuit and the clock disconnection detection circuit, respectively. Now, as long as the N system clock input is normally in the normal state and the N system corresponding clock loss detection circuit determines that the N system clock input is in the normal state, the N system clock input is under the control of the control circuit CONT. A clock f (N) generated in the system-corresponding phase-locked loop circuit and synchronized with the N-system input clock is selectively output from the selection circuit SEL. However, assuming that there is some failure in the N-system clock input, for example, a clock loss failure in such a state, that fact is detected by the N-system compatible clock loss detection circuit, and the system switching signal Is notified to the control circuit CONT, and the selection circuit SEL synchronizes with the E-system input clock generated by the E-system compatible phase-locked loop circuit instead of the clock f (N). The clock f (E) is selected and output from the selection circuit SEL.
[0004]
As can be seen from the above, when a clock disconnection failure occurs in the N-system clock input, the system is switched to the E-system clock input, thereby affecting each subsequent communication device due to the clock disconnection failure. The ripples are minimized.
[0005]
[Problems to be solved by the invention]
However, depending on various types of failures (clock failure is one of them), for example, taking a clock failure as an example, the clock failure state is a fixed failure in which the clock-off state continues semi-fixedly. In some cases, it is essential that system switching be performed because of the need to supply an operating clock to each subsequent communication device, but so far system switching in the event of a transient failure has occurred. As for the situation, it is not considered necessary and sufficient. In other words, every time a transient failure such as a temporary interruption or a signal rule violation occurs, system switching is performed in response to the temporary failure. On the other hand, when the transient failure occurs frequently, such a mode of occurrence cannot be ignored.
[0006]
Even if a transient failure is detected, the object of the present invention is determined to be a failure for the first time when the failure detection frequency reaches a predetermined frequency without immediately considering it as a failure occurrence. In addition, a fault monitoring method and a circuit for enabling system switching are provided.
[0007]
[Means for Solving the Problems]
The above-mentioned purpose is the first time a transient failure is detected when the number of transient failures detected within a certain period of time from the time of detection of the transient failure reaches a predetermined number of times. This is achieved by determining the occurrence. Also, the fault monitoring circuit counts the fault detection signal that generates a fault detection signal every time a transient fault is detected, and the fault detection signal from the fault detection means in n-ary, and then decodes the count value N parallel selection units that are activated by a failure detection signal from the failure detection unit and generate a timer up signal after a predetermined time while any one is selected by the timer selection unit. The timer means provided in the counter and the fault detection signal from the fault detection means are counted up, while being counted down by the time-up signal from each of the timer means, a certain time from the detection time of each transient fault A fault detection frequency detecting means for detecting the number of transient fault detections within the previous period as a fault detection frequency, and the fault detection frequency detection; When the failure detection frequency from the means has reached a predetermined number n, it is accomplished by being composed of a determined failure existence judging means as the first failure.
[0008]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment of the present invention will be described with reference to FIGS.
First, a fault monitoring circuit according to the present invention will be described with reference to FIG. 1 showing the configuration of an example thereof, and FIG. As shown in FIG. 1, the failure monitoring circuit is roughly divided into a failure detection unit 1 that generates a failure detection signal each time a transient failure is detected, and a failure detection signal from the failure detection unit 1. A fault selection from the fault detection unit 1 in a state where the timer selection unit which counts with the n-adic free-run counter 6 and decodes the count value with the decoder 7 and any one is selected by the timer selection unit N timer circuits 3 to 5 provided in parallel which generate a timer up signal after a predetermined time after being started by a signal, and count up the fault detection signal from the fault detection unit 1, while the timer circuit By detecting the time-up signal from each of 3 to 5 times, the transient failure detection times within a period of time from the time of detection of each transient failure to a certain time before Up / down counter 2 as failure detection frequency detection means for detecting failure as the failure detection frequency, failure presence / absence determination means for determining failure occurrence for the first time when the failure detection frequency from the failure detection frequency detection means reaches a predetermined number n It is comprised from the comparison part 15 as. In FIG. 1, reference numerals 11 to 13 denote 2-input OR gates, reference numerals 8 to 10 denote D-type flip-flops, and reference numeral 14 denotes a multi-input OR gate.
[0009]
As can be seen from FIG. 1, the failure detection signal from the failure detection unit 1 is counted by the n-ary free-run counter 6, and the count value is decoded by the decoder 7. Each of the timer circuits 3 to 5 is selected sequentially and cyclically. By the way, when each of these timer circuits 3 to 5 is once activated by a failure detection signal, the subsequent restart is impossible, and the time from the activation time to the time-up is set to be the same. It has become. Taking the example of the timer circuit 3, the D-type flip-flop 8 in the reset state receives the fault detection signal as the set signal in a state where the timer selection signal from the decoder 7 is input as the D input via the OR gate 11. The timer circuit 3 is started for the first time at the time of transition to the set state. Once the timer circuit 3 is activated, the Q output of the D-type flip-flop 8 (corresponding to timer 3 enable described later) is fed back to the OR gate 11 as another input, so that the timer circuit 3 times out (time up). Until the signal is obtained as a reset signal to the D-type flip-flop 8, the failure detection signal and the timer selection signal are irrelevant. Such a situation is the same in each of the other timer circuits 4 and 5. By the way, in the up / down counter 2, the failure detection signal is counted up, but the count-up value is down-counted via the OR gate 14 by the timeout signal from each of the timer circuits 3 to 5, thereby causing a transient failure. Is detected as the failure detection frequency within the time from the detection time to a certain time before the failure detection frequency, and when the failure detection frequency reaches the predetermined number n Thus, the comparison unit 15 obtains a determination result indicating that a failure has occurred for the first time as the determination result.
[0010]
Now, finally, assuming that the value of n is 3, and as shown in FIG. 2, a transient fault is detected in time series, the circuit operation in this case will be described with reference to FIG. It is as follows.
That is, in the initial state in which the free-run counter 6 and the D-type flip-flops 8 to 10 are reset, including the up / down counter 2, the timer selection signal from the decoder 7 is selected so that the timer circuit 3 is selected. If the first failure detection signal is generated from the failure detection unit 1 in this state, it is input to the D input of the D flip-flop 8 through the OR gate 11 as an “H” state. When the D-type flip-flop 8 is shifted to the set state by the signal and the timer circuit 3 is started, each of the free-run counter 6 and the up / down counter 2 is counted up by the failure detection signal. Both values are set to “1”. In this state, in order to select the timer circuit 4, the timer selection signal from the decoder 7 is inputted to the D input of the D-type flip-flop 9 as the "H" state via the OR gate 12, and in this state, eventually, When the second failure detection signal is generated from the failure detection unit 1, the D-type flip-flop 9 is shifted to the set state by this failure detection signal, and at the same time the timer circuit 4 is started, the free run Each of the counter 6 and the up / down counter 2 is counted up by the failure detection signal, and both count values are set to “2”. However, if the timer circuit 3 subsequently times out, the timer circuit 3 and the D-type flip-flop 8 are reset, and the up / down counter 2 is counted down through the OR gate 14, whereby the count value is "1". It is something that will be placed in. In this state, since the count value of the free-run counter 6 is “2”, the timer circuit 5 is selected, but when the third failure detection signal is generated, the timer circuit 5 is activated. At the same time, the count values of the free-run counter 6 and the up / down counter 2 are set to “0” and “2”, respectively, but if the timer circuit 4 subsequently times out, the count value of the up / down counter 2 is “1”. ""
[0011]
Further, if the fourth fault detection signal is generated in a state where the timer circuit 3 is selected, the timer circuit 3 is started and at the same time the count values of the free-run counter 6 and the up / down counter 2 are respectively “1” and “2”. After that, if the timer circuit 5 times out, the count value of the up / down counter 2 is set to “1”. After that, if the sixth signal is continuously generated after the fifth failure detection signal before the timer circuit 3 times out, the up / down counter 2 counts up continuously twice. When the count value is set to “3”, the comparison unit 15 obtains a determination result (abnormal signal) indicating that a failure has occurred for the first time as the determination result.
[0012]
【The invention's effect】
As described above, according to claims 1 and 2, even if a transient fault is detected, the fault detection frequency reaches a predetermined frequency without immediately considering it as a fault occurrence. In this case, a fault monitoring method and a circuit thereof capable of system switching can be obtained after being determined as the occurrence of a fault for the first time. Therefore, in the case where a transient fault occurs in the entire system and each communication device. Even if it exists, stable operation is expected.
[Brief description of the drawings]
FIG. 1 is a diagram showing a configuration of an example of a fault monitoring circuit according to the present invention. FIG. 2 is a diagram for explaining circuit operation in the example of the circuit. Fig. 2 is a diagram showing a configuration of a clock switching circuit according to the prior art used in a synchronous terminal device or the like.
DESCRIPTION OF SYMBOLS 1 ... Fault detection part, 2 ... Up / down counter, 3-5 ... Timer circuit, 6 ... Free run counter, 7 ... Decoder, 8-10 ... D-type flip-flop, 11-13 ... 2 input OR gate, 14 ... Multiple inputs OR gate, 15 ... comparison part

Claims (2)

Each time a transient failure is detected, it is determined that a failure has occurred for the first time when the number of transient failures detected within a certain period of time from the time of detection of the transient failure reaches a predetermined number of times. Fault monitoring method. Each time a transient failure is detected, it is determined that a failure has occurred for the first time when the number of transient failures detected within a certain period of time from the time of detection of the transient failure reaches a predetermined number of times. A fault monitoring circuit configured to generate a fault detection signal each time a transient fault is detected; and n (n: generally two or more). The timer selection unit that counts in decimal and decodes the count value, and is activated by a failure detection signal from the failure detection unit in a state where any one is selected by the timer selection unit In addition, n timer means provided in parallel for generating a timer up signal after a certain time, and a fault detection signal from the fault detection means are counted up. A fault detection frequency detecting means for detecting the number of transient fault detections within a period of time from the detection time of each transient fault as a fault detection frequency by being counted down by a time-up signal from A fault monitoring circuit comprising fault presence / absence judgment means that judges that a fault has occurred for the first time when the fault detection frequency from the fault detection frequency detection means reaches a predetermined number n.

Images