JPH1011324A - Signal sending-out circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speedily and securely detect a fault occurring to a remote device. SOLUTION: The signal sending-out circuit is provided in the remote device 1 which has a control circuit part such as a CPU 3. The signal sending-out circuit has a ROM 7 wherein a 1st or 2nd storage area can be selected according to input to an address input terminal A3 , a binary counter 8 which counts a clock signal and has its output terminals Q0 -Q2 connected to address input terminals A0 -A2 of the ROM 7 respectively, a D type flip-flop 6 whose output Q is inverted corresponding to the signal from the CPU 3, a reset circuit 4 which outputs a reset signal, and a delay circuit 5 which delays and supplies the rest signal to the binary counter 8. In the ROM 7, bit patterns showing signals to be sent out to a monitor device 2 at normal start time and in the case of abnormality occurrence are written previously in the 1st and 2nd storage areas, one of which is selected according to the Q output of the D type flip-flop 6.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal transmission circuit used for monitoring a failure of a remotely located device by a monitoring device, and more particularly, to a remote device using a CPU (Central Processing Unit) or the like. It relates to a signal sending circuit provided in the remote device for monitoring.

[0002]

2. Description of the Related Art A general method for detecting the occurrence of a fault in a device to be monitored, which is located remote from a monitoring device, that is, a remote device, is to start up the remote device or restart the power supply. When the remote device starts operating normally after being turned on, a signal is sent to the monitoring device at regular intervals due to the operation of software on the remote device, and if this signal cannot be received by the monitoring device for a fixed time or more There is a method for determining that a remote device is abnormal.

For example, Japanese Patent Laid-Open Publication No. 1-114137 discloses a failure monitoring method in a data transmission system.
It is disclosed that each of the relay nodes transmits a specific pattern on a transmission line at a fixed period, and the terminal side indicates that a failure has occurred by not detecting the specific pattern at a fixed period. In addition, for example, JP-A-4-45854 discloses an in-band signal device used in a dedicated line, and a transmission side transmits a failure only during a fixed time immediately after a call is activated. There is disclosed a device which outputs a signal in a predetermined pattern and issues a warning signal when the predetermined pattern is not detected on the receiving side.

[0004]

However, in the technology described in each of the above publications, a device to be monitored (remote device)
Can start up normally and the monitoring device can receive signals when the transmission path between the remote device and the monitoring device is normal, so if the signal from the remote device cannot be received, the monitoring device There is a problem in that it cannot be determined whether the device itself has failed or the transmission path has failed. Further, in the case of a method in which a signal is sent from the remote device to the monitoring device at a fixed period, the main purpose of this method is to detect the occurrence of a failure in the operating remote device. Failure monitoring cannot be performed until the failure monitoring function itself starts operating.Therefore, after restarting the power supply by remote operation or starting up the target device, it takes time to determine whether the remote device has started normally. Is required.

An object of the present invention is a signal transmission circuit used in a system in which a monitoring device monitors a remote device at a remote place, and enables a prompt determination of whether or not the remote device has started normally. And a signal transmission circuit for isolating the failure from the transmission path and allowing the monitoring device to know the occurrence of the failure even when the failure of the remote device prevents the remote device from starting. It is in.

[0006]

A signal transmission circuit according to the present invention is a signal transmission circuit provided in a remote device for remotely monitoring the occurrence of a fault in the remote device having a control circuit section, the first signal transmission circuit comprising: (A read-only memory) having a different storage area and a second storage area in which different bit patterns are written in advance in each of these storage areas, a clock signal is supplied to execute a counting operation, and a ROM address is read. A counter having an input terminal connected to an output terminal, a flip-flop having an output inverted according to a signal input from the control circuit portion, a reset circuit outputting a reset signal to at least the control circuit portion and the flip-flop, And a delay circuit for delaying a reset signal and resetting the reset signal to a counter. Any storage area and the second memory area is selected, the signal from the data output terminal of the ROM is outputted to the outside as a signal for fault monitoring.

In the present invention, the control circuit unit is, for example, a CPU for realizing the function of the remote device itself. As the counter, a counter that stops operating when the count value reaches a predetermined number after resetting is preferably used.

[0008] When monitoring a remote device provided with the signal transmission circuit of the present invention by a monitoring device, R
It is preferable that a signal from the data output terminal of the OM is input to the monitoring device, and a signal for operating the reset circuit is transmitted from the monitoring device via the transmission path.

According to the present invention, a signal pattern indicating a normal start and a signal pattern indicating a fault occurrence are previously written in the first storage area and the second storage area of the ROM, respectively, and the clock is counted. ROM by doing
A counter for sequentially generating an address for is prepared. With this configuration, the pattern written in the ROM can be output to the outside in synchronization with the clock. In the present invention, however, the pattern stored in the first storage area is further output by the control circuit unit. It is arranged that the second storage area is selected. As a result, the storage area to be selected differs when the remote device starts up normally and when it does not, and the signal pattern sent to the monitoring device differs depending on whether the remote device is normal or not. The status of the remote device can be grasped on the monitoring device side. At this time, if there is a fault in the transmission path, the signal itself does not reach the monitoring device, and it can be isolated from a fault in the remote device.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing a configuration of a monitoring system using a signal transmission circuit according to one embodiment of the present invention.

In this monitoring system, it is assumed that the monitoring device 2 monitors and controls a device located at a remote place. Here, a device located at a remote location is referred to as a remote device 1. The remote device 1 and the monitoring device 2 are connected via a transmission line 12.

The remote device 1 is provided with a CPU 3 for performing various operations for realizing the original functions of the remote device 1. Here, it is assumed that the CPU 3 includes peripheral circuits such as a RAM (random access memory), a program ROM, and an I / O port in addition to the microprocessor. It is assumed that a signal is being generated.

Further, the time width of the remote device 1 is t.
, A delay circuit 5 for delaying the reset signal by a predetermined time T, and an output from one of the I / O ports of the CPU 3 input to a clock input terminal CK. D-type flip-flop (F / F) 6, a ROM 7 in which a predetermined bit pattern is written in advance, a binary counter 8 that performs a counting operation according to a clock signal, and a counter 8 based on the output of the delay circuit 5. Reset input terminal

[0014]

[Outside 1] A pulse generating circuit 9 for generating a pulse signal for
An AND gate 10 and an inverter 11 are provided. Here, the reset circuit 4 generates a reset signal based on a signal input from the monitoring device 2 via the transmission line 12, and the reset signal, that is, the output of the reset circuit 4 is supplied to the delay circuit 5. Besides CPU
3 and the reset input terminal R of the D-type flip-flop 6.

The delay circuit 5 is supplied with a clock signal in addition to the reset signal. The delay circuit 5 delays the reset signal by a predetermined time T with respect to the clock signal and outputs it. The pulse generating circuit 9 normally outputs “H” (“
1 "), and outputs" L "(" 0 ") with a predetermined pulse width upon detecting the falling edge of the output of the delay circuit 5. The D input terminal of the D-type flip-flop 6 Is "
H "is supplied.

The ROM 7 has four address input terminals A _0.
ＡA ₃ to store data from address 0 to address 15. Further, the least significant bit (LSB)
Has a data output terminal D _0, the output from the data output terminal D ₀ is adapted to be transmitted to the monitoring apparatus 2 through the transmission path 12. The highest-order address input terminal A ₃ is connected to the non-inverted output terminal Q of the D-type flip-flop 6.
Connected to A bit pattern of a signal indicating the occurrence of a failure is previously written in the D ₀ bits (LSB) from address 0 to address 7 of the ROM 7, and the normal start is written in the D ₀ bit from address 8 to address 15. The bit pattern of the indicated signal is written in advance. On the other hand, the binary counter 8 has four output terminals Q _{0 to} Q ₃ , of which three output terminals Q _{0 to} Q ₂ are connected to the address input terminals A _{0 to} A ₂ of the ROM 7, respectively. doing. The signal from the output terminal Q ₃ of the binary counter 8 is inverted by the inverter 11 and input to the NAND gate 10, and a clock signal is input to the NAND gate 10. The output of the NAND gate 10 is the clock input terminal CK of the binary counter 8. Connected to

With the above construction, the output of the D-type flip-flop 6 selects the addresses 0 to 7 or the addresses 8 to 15 of the ROM 7 and allows the binary counter 8 to count up. Correspondingly,
So that the bit pattern in the ROM7 in selected areas is outputted from the data output terminal D ₀ to the monitoring apparatus 2 side.

Next, the operation of the monitoring system will be described. FIG. 2 is a timing chart for explaining the operation of this monitoring system.

When a signal for instructing reset is sent from the monitoring device 2 to activate the remote device 1, this signal is received by the reset circuit 4, and the reset circuit 4 becomes "H" for a certain time width t. Generates a reset signal (reset pulse). With this reset signal, the entire remote device 1 including the CPU 3 is reset, the D-type flip-flop 6 is also reset, and the non-inverted output Q of the D-type flip-flop becomes "L".

When the reset signal disappears (transits to "L"), the CPU 3 starts operating. At this time, in the initial processing of the software program for the CPU 3, I
Software for the CPU 3 is set in advance so that a pulse is output from the / O port to the D-type flip-flop 6. As a result, when the CPU 3 is started normally, the D-type flip-flop 6 is connected to the I / O port.
Is the output pulse to the clock input terminal CK, thereby inverts the state of the D-type flip-flop, the non-inverting output terminal Q state, namely the state of the address input terminal A ₃ of ROM7 transits to "H", the 15 from address 8 of ROM7
The address area will be selected. When the CPU3 did not start normally, the state of the address input terminal A ₃ of ROM7 are remained "L", so that the region to address 7 from address 0 ROM7 is selected.

At the same time, the output of the reset circuit 4 is
, And is also input to the binary counter 8 via the pulse generating circuit 9. After reset, the time until the CPU 3 generates a pulse for inverting the D-type flip-flop 6 is defined as τ, and the delay time T in the delay circuit 5 is τ <T + t
It is set so that As described above, when the output of the delay circuit 5 transitions from “H” to “L”,
L "pulse is outputted from the pulse generating circuit 9 to the binary counter 8, the binary counter 8 .2 binary counter 8 is reset to 0, when it is reset, its Q ₃ outputs" L "
, The counting of the clock signal is started, and the output terminals Q _{0 to} Q ₂ sequentially change from “000” to “111” in binary notation, which is the address input terminals A _{0 to} A _{2 of the} ROM 7.
Is output to As a result, the bit pattern being previously written in the ROM 7, are output to the monitor device 2 from the data output terminal D _0. As described above, either the area from address 0 to address 7 or the area from address 8 to address 15 of the ROM 7 is selected by the output of the D-type flip-flop 6, so that this area is selected. A bit pattern corresponding to the area is output. In the example described here, when the CPU 3 starts normally, the bit pattern written to the addresses 8 to 15 of the ROM 7 is output to the monitoring device 2, and when the CPU 3 does not start normally. Outputs a bit pattern written at addresses 0 to 7 of the ROM 7.

After the above operation, the CPU 3
Is activated when the output of the delay circuit 5 falls, regardless of whether it has started normally or not.
The hexadecimal counter 8 operates, and a signal pattern reporting the result of the fault monitoring is sent to the monitoring device 2. Incidentally, the binary output terminals Q ₀ to Q ₂ output terminal Q ₃ are at the next clock cycle becomes "111" in the binary representation of the counter 8 "H" next to which the output of the NAND gate 10 is always "
H ", and the binary counter 8 stops counting until resetting is performed again.

FIG. 3 is a block diagram showing a configuration of a monitoring system using a signal transmission circuit according to another embodiment of the present invention. , Shown in Figure 1 while previously used a single ROM, here, using two ROM 7 _1, 7 ₂ having a storage area from each 0 through address 7. Address input terminals A _{0 to} A ₂ of the ROMs 7 ₁ and 7 _{2 have} output terminals Q ₀ to Q 2 of the binary counter 8 as in the case of FIG.
Q ₂ is connected. Further, the D-type flip-flop 6
Is the output enable terminal of _one ROM 71

[0024]

[Outside 2] Connected to the inverted output terminal

[0025]

[Outside 3] There other ROM 7 ₂ output enable terminal

[0026]

[Outside 4] And the data output terminals D _{0 of} both ROMs 7 ₁ and 7 ₂ are connected to each other and to the monitoring device 2.
Here one bit pattern in the event of a failure in ROM 7 _1, by previously written bit pattern of the normal startup in the other ROM 7 _2, the switching of the ROM are performed by the output of D-type flip-flop 6, Figure 1 and the monitoring system described with reference to FIG.

[0027]

As described above, according to the present invention, in the first storage area and the second storage area of the ROM, a signal pattern indicating normality and a signal pattern indicating failure are written in advance, respectively. By selecting these storage areas using flip-flops whose output is inverted by a signal from the control circuit unit and outputting the signals to the monitoring device side, the following effects are obtained.

First, even if the start-up process of the remote device as a whole is not completed, a signal may be sent to the monitoring device in response to a signal from the control circuit unit when only the signal sending circuit is started. As a result, fault detection after the start-up of the remote device can be performed quickly.

Second, since the time from when the remote device is reset to when the signal sending circuit sends a signal depends only on the hardware, whether the remote device starts normally or a failure occurs, A report is sent to the monitoring device a fixed time after the reset, and the status of the remote device can be reliably grasped after the fixed time. On the other hand, when a signal indicating that the device has been started is reported by software, it is difficult to strictly specify the time at which the report is made due to variations in software processing time.

Third, the signal transmission circuit of the present invention is composed of simple hardware. If the signal transmission circuit operates even if a trouble occurs in, for example, the CPU or software of the control circuit section, Because it can send out signals,
Even when a failure has occurred in the remote device, the information can be reported to the monitoring device with a high probability.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a monitoring system using a signal transmission circuit according to an embodiment of the present invention.

FIG. 2 is a time chart illustrating an operation of the monitoring system of FIG. 1;

FIG. 3 is a block diagram illustrating a configuration of a monitoring system using a signal transmission circuit according to another embodiment of the present invention.

[Explanation of symbols]

1 remote device 2 monitor 3 CPU 4 reset circuit 5 delay circuit 6 D-type flip-flop 7, 7 _1, 7 ₂ ROM 8 2 binary counter 9 pulse generating circuit 10 NAND gate 11 inverter 12 transmission line

Claims (3)

[Claims] 1. A signal transmission circuit provided in a remote device for remotely monitoring the occurrence of a fault in a remote device having a control circuit unit, the signal transmission circuit comprising a first storage area and a second storage area. Having different bit patterns written in advance in the respective storage areas.
OM and a clock signal are supplied to perform a counting operation,
A counter having an output terminal connected to the address input terminal of M, a flip-flop whose output is inverted according to a signal input from the control circuit unit, and a reset signal output to at least the control circuit unit and the flip-flop And a delay circuit that delays the reset signal to reset the counter and provides the delayed signal to the counter. The first storage area and the second storage according to an output of the flip-flop One of the regions is selected and the R
A signal transmission circuit that outputs a signal from a data output terminal of the OM to a device as a failure monitoring signal. 2. The signal transmission circuit according to claim 1, wherein after the counter is reset, the operation stops when a count value reaches a predetermined number. 3. The signal transmission circuit according to claim 1, wherein a signal from a data output terminal of the ROM is transmitted to a monitoring device, and a signal for operating the reset circuit is input from the monitoring device. .