JP2004326405A - State monitoring system for watchdog timer circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To correctly notify a failure due to a clock anomaly by preventing an erroneous determination indicating an anomaly in software on a processor according to a watchdog timer alarm, when a clock anomaly causes a malfunction of the processor. <P>SOLUTION: When a watchdog timer circuit 2 operated at a second clock 24 to detect a malfunction of a processor 1 operated at a first clock 22 is timed out, a first clock anomaly detection circuit 5 for detecting an anomaly in the first clock upon the lapse of a predetermined time checks whether a first clock anomaly is detected or not; and if finding a first clock anomaly, outputs a first failure notification signal 21 indicating a malfunctioning state of the processor due to the first clock anomaly, and if finding no first clock anomaly, outputs a second failure notification signal 21 indicating an anomaly in software on the processor 1. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a state monitoring method of a watchdog timer circuit, and particularly to a failure caused by a clock abnormality supplied to a processor without erroneously outputting a watchdog timer / alarm when a clock abnormality is supplied to a processor. The present invention relates to a state monitoring method for a watchdog timer circuit that can correctly notify the failure monitoring circuit of the state.
[0002]
[Prior art]
Conventionally, a watchdog timer circuit has been used to detect an abnormality such as a stoppage or runaway of a processor. As a technique for monitoring the operation state of the watchdog timer circuit, for example, Japanese Patent Application Laid-Open No. 62-233854 There is a technique disclosed in Japanese Patent Application Laid-Open Publication No. H10-26095.
[0003]
The technique disclosed in Japanese Patent Application Laid-Open No. 62-233854 is capable of discriminating between an abnormality of a clock signal supplied to a processor and an abnormal operation of a clock signal abnormality detection circuit itself for detecting the abnormality of the clock signal. In addition, if the clock signal is abnormal, a technology that can recognize that it is a serious failure that may cause the processor operation to become abnormal due to the clock signal abnormality and affect the entire system using the processor. Has been described.
[0004]
On the other hand, the state monitoring method of the conventional watchdog timer circuit shown in FIG. 4 also uses a clock abnormality detection circuit for detecting a clock abnormality, similarly to the technique disclosed in Japanese Patent Application Laid-Open No. 62-233854.
[0005]
Hereinafter, the configuration and operation of the state monitoring method of the watchdog timer circuit shown in FIG. 4 will be described.
[0006]
The state monitoring method of the watchdog timer circuit shown in FIG. 4 monitors the processor 1 in the apparatus, which operates by receiving a clock, and abnormal operation such as runaway or stop of software on the processor 1, and performs abnormal operation. Is detected, the software on the processor 1 determines that the processor 1 is in an abnormal state, and outputs a watchdog timer / alarm 21. The watchdog timer circuit 2 outputs a first clock 22 as a clock for operating the processor 1. And a first clock alarm 23 is output when the first clock 22 becomes abnormal due to a failure of the clock generation circuit 3 and the first clock 22 becomes abnormal. The clock abnormality detection circuit 5 and the second clock 24 for operating the watchdog timer circuit 2 are watched. A clock generation circuit 4 to be supplied to the timer circuit 2 and a second clock alarm detecting a clock abnormality of the second clock 24 when the second clock 24 becomes abnormal due to a failure of the clock generation circuit 4. 25, a watchdog timer / alarm 21 output from the watchdog timer circuit 2, a first clock alarm 23 output from the clock abnormality detection circuit 5, and a clock abnormality detection circuit 6. Monitoring of the occurrence of each of the second clock alarms 25 output from the CPU and monitoring of a fault occurring in the clock generating circuit 3, a fault occurring in the clock generating circuit 4, or a malfunction of the software occurring in the processor 1. And the monitoring result requires the watchdog timer circuit related status monitoring information Constructed and a fault monitoring circuit 8c for outputting the to equipment.
[0007]
The watchdog timer circuit 2 has a watchdog timer function, is controlled by a second clock 24 output from the clock generation circuit 4, and advances by a counter (not shown) before the counter times out. That is, a watchdog timer clear control signal 20 from the processor 1 for periodically resetting the increment of the counter within the cycle of the counter and clearing the increment value of the counter is received, and the increment of the counter is performed. When a watchdog timer clear control signal is not output periodically and the counter is not reset during a period of the counter, it is determined that the software of the processor 1 is abnormal. And a control unit (not shown) for outputting a watchdog timer / alarm 21. .
[0008]
Next, the operation will be described.
[0009]
In FIG. 4, a processor 1 operates by inputting a first clock 22 output from a clock generation circuit 3.
[0010]
In the watchdog timer circuit 2, a built-in counter (not shown) is controlled by the second clock 24 output from the clock generation circuit 4 to advance and output periodically within the counter period. The register receives a watchdog timer clear control signal 20 from the processor 1 which is set in advance from the processor 1, and the register resets the increment of the counter. The counter whose step is reset restarts the step again after the step reset. The repetitive operation of the step and the reset is continued as long as the operation of the processor 1 is normal.
[0011]
That is, when the processor 1 is operating normally, the watchdog timer / clear control signal 20 is periodically output within the counter cycle to reset the counter, and the counter repeats the step and reset operations. To be continued.
[0012]
In the state where the above operation is continued, the state where the processor 1 outputs the watchdog timer clear control signal 20 to the watchdog timer circuit 2 periodically within a counter cycle at a preset timing continues. However, when the operation of the processor 1 becomes abnormal and the access to the register becomes impossible, the register receives the watchdog timer clear control signal 20 from the processor 1 within the counter period. Cannot be performed, the step of the counter is continued without being reset, the step proceeds, and the step cannot be reset within the cycle of the counter, and a timeout occurs.
[0013]
The control unit of the watchdog timer circuit 2 detects this timeout and determines that the software of the processor 1 is abnormal, that is, the operation of the processor 1 is abnormal, and outputs a watchdog timer / alarm 21 to the fault monitoring circuit 8c.
[0014]
The fault monitoring circuit 8c notifies other devices that need the watchdog timer circuit-related status monitoring information that the watchdog timer / alarm 21 has occurred as the watchdog timer circuit-related status monitoring information.
[0015]
When the first clock 22 is in an abnormal state due to a failure of the clock generation circuit 3, the clock abnormality detection circuit 5 detects a clock abnormality of the first clock 22 and outputs a first clock alarm 23. The first clock alarm 23 is input to the fault monitoring circuit 8c.
[0016]
Further, the clock abnormality detection circuit 6 also detects a clock abnormality of the second clock 24 and outputs a second clock alarm 25 when the second clock 24 becomes abnormal due to the failure of the clock generation circuit 4. The second clock alarm 25 is input to the fault monitoring circuit 8c.
[0017]
The failure monitoring circuit 8c monitors the operation abnormality of the processor 1, the failure of the clock generation circuit 3, and the failure of the clock generation circuit 4 by the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25. I do.
[0018]
As described above, the failure monitoring circuit 8c outputs the first clock alarm 23 from the clock abnormality detection circuit 5 when a failure occurs in the clock generation circuit 3, and outputs the clock abnormality when the failure occurs in the clock generation circuit 4. The detection circuit 6 outputs a second clock alarm 25. Alternatively, when a software abnormality occurs in the processor 1, the watchdog timer / alarm 21 output from the watchdog timer circuit 2 is input to the fault monitoring circuit 8c. Note that the first clock alarm 23, the second clock alarm 25, and the watchdog timer / alarm 21 do not normally occur synchronously.
[0019]
Regarding the watchdog timer / alarm, when the clock generation circuit 3 that outputs the first clock 22 fails, the clock abnormality detection circuit 5 detects the abnormality of the first clock 22 and performs the first operation. Due to the abnormality of the clock 22, the processor 1 operated by the first clock 22 becomes inoperable, and the watchdog timer / alarm 21 is output. At this time, depending on the operation timing of the clock abnormality detection circuit 5 and the operation timing of the watchdog timer circuit 2, while the clock abnormality detection circuit 5 is still detecting the abnormality of the first clock 22, the watchdog In the timer circuit 2, the processor 1 does not access the internal register in the watchdog timer circuit 2, so that the counter keeps incrementing without being reset, and resets the increment within the counter period. When the operation times out, the watchdog timer times out, and the watchdog timer circuit outputs a watchdog timer / alarm. Therefore, the fault monitoring circuit 8c outputs the watchdog timer / alarm output from the watchdog timer circuit. Fault monitoring circuit based on the software on the processor There is a possibility that made the wrong decision and has always been.
[0020]
As described above, the watchdog timer / alarm 21 is input to the fault monitoring circuit 8c before the detection of the abnormality of the first clock 22 by the clock abnormality detection circuit 5 is completed, and If it is determined that the software is abnormal, the actual cause is the abnormality of the first clock 22 due to the failure of the clock generation circuit 3, and even if there is no abnormality of the software on the processor 1, Regardless, there is a problem that an erroneous determination that a software abnormality on the processor 1 has occurred is made.
[0021]
When the clock generation circuit 3 fails and the first clock 22 supplied to the processor 1 is in an abnormal state such as a stop, the abnormal state is detected by the clock abnormality detection circuit 5 and the watch Since the watch dog timer / alarm 21 is output from the dog timer circuit 2, it can be determined that the clock generation circuit 3 has failed. However, at this time, when the watchdog timer / alarm 21 is not output from the watchdog timer circuit 2, the reason why the watchdog timer / alarm 21 is not output is that the watchdog timer circuit 2 is out of order. Or the clock generation circuit 4 has failed and the second clock 24 supplied to the watchdog timer circuit 2 has stopped.
[0022]
[Patent Document 1]
JP-A-62-233854 (page 2, FIG. 1)
[0023]
[Problems to be solved by the invention]
In the above-described conventional state monitoring method of the watchdog timer circuit, the operation timing of the first clock abnormality detection circuit for detecting abnormality of the first clock supplied to the processor and the operation timing of the watchdog timer circuit are described. In some cases, while the first clock abnormality detection circuit is still performing an operation of detecting an abnormality of the first clock supplied to the processor, the watchdog timer circuit uses the watchdog timer of the watchdog timer circuit by the processor. Is timed out, a watchdog timer / alarm is output from the watchdog timer circuit, and the fault monitoring circuit 8c detects that the software on the processor is abnormal based on the watchdog timer / alarm output from the watchdog timer circuit. False judgment that it has become It has the disadvantage that there is a possibility that put away.
[0024]
When the clock generation circuit 3 fails and the first clock 22 supplied to the processor 1 is in an abnormal state such as a stop, the abnormal state is detected by the clock abnormality detection circuit 5 and the watch Since the watch dog timer / alarm 21 is output from the dog timer circuit 2, it can be determined that the clock generation circuit 3 has failed. However, at this time, when the watchdog timer / alarm 21 to be output from the watchdog timer circuit 2 is not output, the reason why the watchdog timer / alarm 21 is not output is because the watchdog timer circuit 2 is out of order. Or the clock generation circuit 4 is out of order and the second clock 24 supplied to the watchdog timer circuit 2 is stopped.
[0025]
It is an object of the present invention to provide a system in which when the operation of a processor becomes abnormal due to a clock abnormality supplied to the processor, software on the processor is abnormal based on a watchdog timer alarm output from the watchdog timer circuit. It is an object of the present invention to provide a state monitoring method of a watchdog timer circuit which can prevent such an erroneous determination as being made and can correctly report a failure due to a clock abnormality supplied to a processor. .
[0026]
Another object of the present invention is to provide a watchdog timer that can easily determine the cause when a clock supplied to a processor is in an abnormal state and a watchdog timer / alarm to be output is not output. An object of the present invention is to provide a circuit state monitoring method.
[0027]
[Means for Solving the Problems]
According to a first aspect of the present invention, there is provided a state monitoring method for a watchdog timer circuit which operates on a second clock and detects an abnormal operation of a processor, and detects an abnormality of a first clock for operating the processor. A first clock abnormality detecting circuit; and a second clock abnormality detecting circuit for detecting an abnormality of the second clock, wherein when the watchdog timer circuit outputs a watchdog timer / alarm, it is determined in advance. It is confirmed whether the first clock abnormality has been detected when the time has elapsed, and if it is confirmed that there is no abnormality in the first clock, it indicates an abnormality in the software on the processor. A first failure notification signal is output, and when the abnormality of the first clock is confirmed by the confirmation, the abnormality of the first clock is detected. Operation of the processor is configured as characterized by outputting a second fault notification signal indicating that the abnormal state.
[0028]
According to a second aspect of the present invention, there is provided a watchdog timer circuit status monitoring method, wherein the watchdog timer circuit operates on a second clock and detects an abnormal operation of a processor. A first clock abnormality detection circuit for detecting an abnormality of the second clock; and a second clock abnormality detection circuit for detecting an abnormality of the second clock, wherein the first clock abnormality detection circuit detects an abnormality of the first clock. Outputs a first clock alarm when the second clock abnormality detection circuit detects an abnormality of the second clock, and outputs a second clock alarm when the second clock abnormality detection circuit detects an abnormality of the second clock. A watchdog timer circuit that outputs a watchdog timer alarm when an abnormality is detected. When a watchdog timer / alarm is output from the watchdog timer circuit, it is checked whether or not the first clock abnormality has been detected when a predetermined time has elapsed, and the first clock alarm is output by the watchdog timer / alarm. When it is confirmed that there is no abnormality in the first clock without being output from the first clock abnormality detection circuit, software on the processor becomes abnormal and the operation of the processor becomes abnormal, and the watchdog When it is determined that a timer / alarm has been output, a first failure notification signal indicating an abnormality of the software on the processor is output, and when the abnormality of the first clock is confirmed by the confirmation, The operation of the processor becomes abnormal due to the abnormality of the first clock, and the watchdog timer circuit outputs the error from the watchdog timer circuit. And a second failure notification signal indicating that the operation of the processor is in an abnormal state due to the abnormality of the first clock. You.
[0029]
A third aspect of the present invention is the watchdog timer circuit according to the first or second aspect, wherein the predetermined time is equal to the first clock. It is characterized in that it is a time corresponding to one cycle of a detection cycle of the abnormality of the first clock performed by the abnormality detection circuit.
[0030]
Further, a state monitoring method of a watchdog timer circuit according to a fourth invention is as follows.
(A) a watchdog timer circuit that monitors an abnormality of software on the processor and outputs a watchdog timer / alarm when it is determined that the software is abnormal on the processor;
(B) a first clock generation circuit that generates a first clock for operating the processor and outputs the generated clock to the processor;
(C) detecting an abnormality of the first clock when the first clock output from the first clock generation circuit is in an abnormal state due to a failure of the first clock generation circuit; A first clock abnormality detection circuit that outputs a clock alarm,
(D) a second clock generation circuit for generating a second clock for operating the watchdog timer circuit and outputting the generated second clock to the watchdog timer circuit, and the second clock generation circuit due to a failure of the second clock generation circuit A second clock abnormality detection circuit for detecting the second clock abnormality when the second clock output from the second clock enters an abnormal state, and outputting a second clock alarm; In a state monitoring method of a watchdog timer circuit for monitoring occurrence of a timer alarm, the first clock alarm, and the second clock alarm,
(E) The watchdog timer alarm output from the watchdog timer circuit, the first clock alarm output from the first clock abnormality detection circuit, and the output from the second clock abnormality detection circuit When the watchdog timer / alarm is first output from the watchdog timer circuit in a state where no alarm of the second clock alarm has occurred, the watchdog timer / alarm is held, and Whether or not the first clock abnormality from the first clock generation circuit is detected when a period of one cycle of the abnormality detection period of the first clock performed by the first clock abnormality detection circuit has elapsed. Whether the first clock alarm is generated by the first clock abnormality detection circuit. If it is confirmed that there is no abnormality in the first clock without being output, it is determined that the watchdog timer / alarm has been output due to a software abnormality on the processor, and the Outputting a first failure notification signal indicating an abnormality of the software, and confirming the first clock alarm from the first clock abnormality detection circuit and outputting the first clock alarm signal from the first clock generation circuit; If an abnormality of the clock is confirmed, the operation of the processor becomes abnormal due to the abnormality of the first clock from the first clock generation circuit, and the watch dog timer circuit -It is determined that an alarm has been output, and the operation of the processor is abnormal due to an abnormality of the first clock of the first clock generation circuit. Configured with a fault condition determination circuit for outputting a second fault notification signal indicating that it is now state.
[0031]
A fifth aspect of the present invention relates to the state monitoring method of the watchdog timer circuit according to the fourth aspect, wherein the first failure notification signal and the second failure notification signal are inputted. And a failure monitoring circuit for monitoring a failure occurring in the first clock generation circuit and a software abnormality occurring in the processor.
[0032]
In a sixth aspect of the present invention, in the state monitoring method of the watchdog timer circuit according to the fourth aspect, the fault state determination circuit generates any of the above alarms. When the first clock alarm is first output from the first clock abnormality detection circuit in the absence state, the first clock alarm is held and the second clock alarm performed by the second clock abnormality detection circuit is held. The second clock generation circuit confirms whether or not the abnormality of the second clock has been detected when the time corresponding to one cycle of the abnormality detection cycle of the second clock has elapsed. When it is confirmed that the second clock alarm is not output from the second clock abnormality detection circuit, the second clock alarm of the second clock generation circuit is output. The watchdog timer circuit should be in an operating state because there is no clock abnormality, but the processor operation is in an abnormal state due to the abnormality of the first clock from the first clock generation circuit. Since the watchdog timer / alarm is not output, it is determined that the watchdog timer circuit has failed, and the operation of the processor is in an abnormal state due to the abnormality of the first clock. Output a third failure notification signal indicating that the watchdog timer circuit is not operating due to a failure, and the second clock alarm is output from the second clock abnormality detection circuit in the confirmation. When the abnormality of the second clock of the second clock generation circuit is confirmed, the second clock from the first clock generation circuit is output. The operation of the processor is in an abnormal state due to the abnormality of the clock, and the operation of the watchdog timer circuit is in the normal operation state due to the abnormality of the second clock of the second clock generation circuit. It is determined that there is no operation, and the operation of the processor is abnormal due to the abnormality of the first clock, and the operation of the watchdog timer circuit is normal due to the abnormality of the second clock. It is configured to output a fourth failure notification signal indicating that it is not in the state.
[0033]
The state monitoring method of the watchdog timer circuit according to a seventh invention is the state monitoring method of the watchdog timer circuit according to the sixth invention, wherein the first failure notification signal, the second failure notification signal, 3 and the fourth failure notification signal are input, the failure occurring in the first clock generation circuit, the failure occurring in the second clock generation circuit, and the software abnormality occurring in the processor. A fault monitoring circuit for monitoring is provided.
[0034]
An eighth aspect of the present invention is the watchdog timer circuit state monitoring system according to the fourth aspect, wherein the watchdog timer circuit includes a first processor and a second processor as the processors. A first watchdog timer circuit and a second watchdog timer circuit as a dog timer circuit; and a first failure state determination circuit and a second failure state determination circuit as the failure state determination circuit. A third clock abnormality detection circuit and a fourth clock generation circuit are provided as one clock abnormality detection circuit, and a fifth clock abnormality detection circuit and a sixth clock generation circuit are provided as the second clock abnormality detection circuit. Wherein the first clock generation circuit includes the first processor, the second processor, and the third clock abnormality detection circuit. Outputting the first clock to the fourth clock generation circuit, wherein the second clock generation circuit outputs the first watchdog timer circuit, the second watchdog timer circuit, and the fifth clock abnormality. Outputting the second clock to a detection circuit and the sixth clock generation circuit, wherein the first watchdog timer circuit is connected to the first processor, and wherein the second watchdog timer circuit is 2 processor, the first failure state determination circuit is connected to the first watchdog timer circuit, and the second failure state determination circuit is connected to the second watchdog timer circuit. The third clock abnormality detection circuit and the fifth clock abnormality detection circuit are connected to the first failure state determination circuit, and the second failure state determination circuit The path is connected to the fourth clock abnormality detection circuit and the sixth clock abnormality detection circuit, and the failure monitoring circuit is connected to the first failure state determination circuit and the second failure state determination circuit. And outputting the first failure notification signal and the second failure notification signal output from the first failure state determination circuit and the second failure state determination circuit, respectively. .
[0035]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a first embodiment of the present invention will be described with reference to the drawings.
[0036]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a state monitoring method of a watchdog timer circuit according to the present invention.
[0037]
The state monitoring method of the watchdog timer circuit according to the present embodiment shown in FIG. 1 monitors the processor 1 which operates upon receiving the first clock 22 and abnormal operation such as runaway or stop of software on the processor 1. When an abnormal operation is detected, the operation state of the software on the processor 1 is determined to be in an abnormal state, and a watchdog timer circuit 2 for outputting a watchdog timer / alarm 21 and a first clock as a clock for operating the processor 1 A clock generation circuit 3 (first clock generation circuit) for outputting the clock 22 to the processor 1 and a clock of the first clock 22 when the first clock 22 becomes abnormal due to a failure of the clock generation circuit 3. A clock abnormality detection circuit 5 (a first clock abnormality detection circuit) that detects an abnormality and outputs a first clock alarm 23 A clock generation circuit 4 (second clock generation circuit) for outputting a second clock 24 for operating the watchdog timer circuit 2 to the watchdog timer circuit 2, and a second clock 24 for the failure of the clock generation circuit 4. A clock abnormality detection circuit 6 (second clock abnormality detection circuit) for detecting a clock abnormality of the second clock 24 and outputting a second clock alarm 25 when the clock signal becomes abnormal, and a watchdog timer circuit 2, the watchdog timer / alarm 21 output from the clock abnormality detection circuit 5, the first clock alarm 23 output from the clock abnormality detection circuit 5, and the second clock alarm 25 output from the clock abnormality detection circuit 6 When a failure occurs, a predetermined failure state determination operation is performed to determine the failure state at that time, and And a failure state determination circuit 7 that outputs a first failure notification signal, a second failure notification signal, a third failure notification signal, or a fourth failure notification signal, which will be described later. By inputting each of the above-mentioned fault notification signals that are output, monitoring of a hardware fault occurring in the clock generating circuit 3 and the clock generating circuit 4 or a software operation error occurring in the processor 1 is performed. A fault monitoring circuit 8a for reporting the monitoring result to another device that needs the related status monitoring information.
[0038]
Note that the processor 1, the watchdog timer circuit 2, the clock generation circuit 3, the clock abnormality detection circuit 5, the clock generation circuit 4, and the clock abnormality detection circuit of the state monitoring method of the watch dog timer circuit of the present embodiment shown in FIG. 6 is the same as the state monitoring system of the watchdog timer circuit shown in FIG. 4, but the state monitoring system of the watchdog timer circuit shown in FIG. The state monitoring method of the watchdog timer circuit of the present embodiment shown in FIG. 1 is different in that a failure state determination circuit 7 and a failure monitoring and monitoring circuit 8a are provided instead of the failure monitoring circuit 8c.
[0039]
As shown in FIG. 2, the failure state determination circuit 7 detects the watchdog timer / alarm 21 output from the watchdog timer circuit 2 and indicates that a watchdog timer / alarm has occurred. An alarm detecting means 41 for outputting a timer / alarm signal 26, and a first clock alarm 23 for detecting the first clock alarm 23 output from the clock abnormality detection circuit 5 and indicating that the first clock alarm has occurred. The alarm detecting means 42 that outputs the signal 28 and the second clock alarm 25 that is output from the clock abnormality detection circuit 6 detect the second clock alarm signal 30 indicating that the second clock alarm has occurred. An alarm detecting means 43 for outputting, and a watchdog timer from the alarm detecting means 41 When the alarm signal 26 is input, the input watchdog timer / alarm signal 26 is output during a period of one cycle of the clock abnormality detection cycle of the first clock 22 performed by the clock abnormality detection circuit 5. After being held, it is output as a watchdog timer / alarm signal 27. When the first clock alarm signal 28 is input from the alarm detecting means 42, the input first clock alarm signal 28 State holding means 44 for holding for a period of one cycle of a clock abnormality detection cycle of the second clock 24 performed by the abnormality detection circuit 6 and then outputting it as a first clock alarm signal 29; A watchdog timer / alarm signal 26 output from the alarm detection means 42; Clock alarm signal 28, second clock alarm signal 30 output from alarm detection means 43, watchdog timer / alarm signal 27 output from state holding means 44, and first clock output from state holding means 44 A failure state determination unit 45 that receives the alarm signal 29, performs a predetermined failure state determination operation, determines the failure state at that time, and outputs the determination result as a failure notification signal 31 to the failure monitoring circuit 8a. .
[0040]
Next, the operation will be described.
[0041]
The processor 1, the watchdog timer circuit 2, the clock generation circuit 3, the clock abnormality detection circuit 5, the clock generation circuit 4, the clock abnormality detection circuit 6, etc. of the state monitoring system of the watchdog timer circuit of the present embodiment shown in FIG. The description of the operation related to this is the same as that in the case of the state monitoring method of the watchdog timer circuit shown in FIG.
[0042]
The operation when the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 are generated will be described with reference to FIG.
[0043]
First, the watchdog timer / alarm 21 is input to the fault state determination circuit 7 in a state where none of the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 have occurred. The operation in the case where it is performed will be described.
[0044]
The watchdog timer / alarm 21 output from the watchdog timer circuit 2 in FIG. 1, the first clock alarm 23 output from the clock abnormality detection circuit 5, and the second clock output from the clock abnormality detection circuit 6 When the watchdog timer / alarm 21 is output from the watchdog timer circuit 2 in a state in which none of the alarms 25 has occurred, the fault state determination circuit 7 holds the watchdog timer / alarm 21, When one cycle of the detection cycle of the abnormality of the first clock 22 performed by the clock abnormality detection circuit 5 has elapsed, it is confirmed whether or not the clock abnormality of the clock generation circuit 3 has been detected. The first clock alarm 23 is not output from the clock abnormality detection circuit 5 and the first clock When it is confirmed that there is no abnormality in the software 22, it is determined that the watchdog timer / alarm 21 has been output due to an abnormality in the software on the processor 1. A first failure notification signal indicating an abnormality is output to the failure monitoring circuit 8a.
[0045]
That is, when the watchdog timer / alarm 21 is output, the failure state determination circuit 7 confirms whether or not the first clock 22 of the clock generation circuit 3 is normal when a predetermined time has elapsed. When the first clock 22 of the generating circuit 3 is normal, the first failure notifying signal indicating the abnormality of the software on the processor 1 is output.
[0046]
At this time, the failure monitoring circuit 8a, which has received the first failure notification signal from the failure state determination circuit 7, sends the watchdog timer circuit-related state monitoring information to another device that needs the watchdog timer circuit-related state monitoring information. As the information, it is reported that the software on the processor 1 is abnormal.
[0047]
In addition, when the first clock alarm 23 is output from the clock abnormality detection circuit 5 and the abnormality of the first clock 22 is confirmed by the above confirmation, the failure state determination circuit 7 It is determined that the operation of the processor 1 is in an abnormal state due to the abnormality of the clock 22 and the watchdog timer / alarm 21 is output from the watchdog timer circuit 2, and the first clock of the clock generation circuit 3 is determined. The second failure notification signal indicating that the operation of the processor 1 is in an abnormal state due to the abnormality of the processor 22 is output.
[0048]
That is, when the watchdog timer / alarm 21 is output, the failure state determination circuit 7 confirms whether or not the first clock 22 of the clock generation circuit 3 is normal when a predetermined time has elapsed. If the first clock 22 of the generation circuit 3 is abnormal, a second failure notification signal indicating that the operation of the processor 1 is abnormal due to the abnormality of the first clock 22 of the clock generation circuit 3 Is output.
[0049]
Further, the fault monitoring circuit 8a, which has received the second fault notification signal from the fault status determination circuit 7, sends the watchdog timer circuit related status monitoring information to another device that needs the watchdog timer circuit related status monitoring information. Then, it is notified that the operation of the processor 1 has become abnormal due to the abnormality of the first clock 22 of the clock generation circuit 3.
[0050]
Next, in a state where none of the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 have occurred, the first clock alarm 23 from the clock abnormality detection circuit 5 is activated. The operation when the signal is input to the failure state determination circuit 7 will be described.
[0051]
The failure state determination circuit 7 holds the first clock alarm 23 when the first clock alarm 23 is output from the clock abnormality detection circuit 5 in a state where none of the above alarms has occurred. It is checked whether an abnormality of the second clock 24 of the clock generation circuit 4 has been detected when a period of one cycle of the abnormality detection period of the second clock 24 performed by the clock abnormality detection circuit 6 has elapsed. If it is confirmed that the second clock alarm 25 is not output from the clock abnormality detection circuit 6 and that the watchdog timer / alarm 21 is not output, the clock generation circuit 4. Since there is no abnormality in the second clock 24 of FIG. 4, the watchdog timer circuit 2 should be in the operating state. It is determined that the watchdog timer circuit 2 is faulty because the watchdog timer / alarm 21 is not output even though the operation of the processor 1 is in an abnormal state due to the abnormality of the first clock 22. Then, a third failure notification signal indicating that the operation of the processor 1 is in an abnormal state due to the abnormality of the first clock 22 and the watchdog timer circuit 2 is not operating due to a failure is output. .
[0052]
That is, when the first clock alarm 23 is output due to the abnormality of the first clock 22 of the clock generation circuit 3, the failure state determination circuit 7 outputs the second clock of the clock generation circuit 4 when a predetermined time has elapsed. It is checked whether or not the clock 24 is normal. If the second clock 24 of the clock generation circuit 4 is normal and the watchdog timer / alarm 21 is not output, the cause is an abnormality of the first clock 22. Output a third failure notification signal indicating that the operation of the processor 1 is abnormal and the watchdog timer circuit 2 is not operating due to a failure.
[0053]
The fault monitoring circuit 8a, which has received the third fault notification signal from the fault status determination circuit 7, sends the watchdog timer circuit related status monitoring information to other devices that need the watchdog timer circuit related status monitoring information. It reports that the operation of the processor 1 is abnormal due to the abnormality of the first clock 22, and that the watchdog timer circuit 2 is not operating due to a failure.
[0054]
If it is confirmed by the above confirmation that the watchdog timer / alarm 21 has been output, the second signal indicating that the operation of the processor 1 is in an abnormal state due to the abnormality of the first clock 22 is indicated. Is output.
[0055]
When the second clock alarm 25 is output from the clock abnormality detection circuit 6 and the abnormality of the second clock 24 of the clock generation circuit 4 is confirmed, the failure state determination circuit 7 The operation of the processor 1 is abnormal due to the abnormality of the first clock 22, and the operation of the watchdog timer circuit 2 is normal due to the abnormality of the second clock 24 of the clock generation circuit 4. The operation of the processor 1 is abnormal due to the abnormality of the first clock 22 of the clock generation circuit 3 and the abnormality of the second clock 24 of the clock generation circuit 4 It outputs a fourth failure notification signal indicating that the operation of the watchdog timer circuit 2 is not in a normal operation state.
[0056]
That is, when the first clock alarm 23 is output due to the abnormality of the first clock 22 of the clock generation circuit 3, the failure state determination circuit 7 outputs the second clock of the clock generation circuit 4 when a predetermined time has elapsed. It is confirmed whether or not the clock 24 is normal. If the first clock 24 of the clock generation circuit 4 is abnormal, the operation of the processor 1 is abnormal due to the abnormality of the first clock 22 of the clock generation circuit 3. And outputs a fourth failure notification signal indicating that the operation of the watchdog timer circuit 2 is not in a normal operation state due to an abnormality of the second clock 24.
[0057]
The failure monitoring circuit 8a, which has received the fourth failure notification signal from the failure state determination circuit 7, sends the fourth monitoring request signal to the other devices that require the watchdog timer circuit-related state monitoring information as the watchdog timer circuit-related state monitoring information. The operation of the processor 1 is in an abnormal state due to the abnormality of the first clock 22 of the clock generation circuit 3, and the operation of the watchdog timer circuit 2 is abnormal due to the abnormality of the second clock 24 of the clock generation circuit 4. It reports that it is not in the normal operation state.
[0058]
Next, the internal operation of the fault condition determination circuit 7 when an alarm such as the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 occurs will be described with reference to FIG. Do.
[0059]
First, the watchdog timer / alarm 21 is input to the fault state determination circuit 7 in a state where none of the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 have occurred. The operation in the case where it is performed will be described.
[0060]
When the watchdog timer / alarm 21 is input to the fault state determination circuit 7 in a state where none of the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 have occurred. In the fault state determination circuit 7, the alarm detection means 41 detects the watchdog timer / alarm 21 and the alarm detection means 41 inputs the watchdog timer / alarm 21 to the state holding means 44 as the watchdog timer / alarm 26. After being held for a period of one cycle of the clock abnormality detection period of the first clock 22 performed by the clock abnormality detection circuit 5, the failure is output to the failure state determination means 45 as the watchdog timer / alarm 27, The state determination means 45 controls the watchdog timer / alarm 27. As well as the force, the first clock alarm signal 28 to verify whether or not input, determines a fault occurrence state by the presence or absence of input of the first clock alarm signal 28.
[0061]
That is, as a result of the above-described confirmation of whether or not the first clock alarm signal 28 has been input by the failure state determination means 45, the first clock alarm 23 from the clock abnormality detection circuit 5 is transmitted to the failure state determination circuit 7. If not, the failure state determination means 45 determines that the watchdog timer / alarm 21 has been output due to the software abnormality on the processor 1 and outputs a first error indicating the software abnormality on the processor 1. Is output to the fault monitoring circuit 8a as the fault notification signal 31.
[0062]
Further, if the first clock alarm 23 is input from the clock abnormality detection circuit 5 to the failure state determination circuit 7 due to the clock abnormality of the first clock 22 of the clock generation circuit 3, the failure state determination means 45 The operation of the processor 1 becomes abnormal due to the abnormality of the first clock 22 of the circuit 3, and it is determined that the watchdog timer / alarm 21 is output from the watchdog timer circuit 2, and the clock generation circuit The second failure notification signal indicating that the operation of the processor 1 is in an abnormal state due to the abnormality of the first clock 22 is output to the failure monitoring circuit 8a as the failure notification signal 31.
[0063]
Next, in a state where none of the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 have occurred, the first clock alarm 23 from the clock abnormality detection circuit 5 is activated. The operation when the signal is input to the failure state determination circuit 7 will be described.
[0064]
In a state where none of the watchdog timer / alarm 21, the first clock alarm 23, and the second clock alarm 25 have occurred, the first clock alarm 23 from the clock abnormality detection circuit 5 determines a failure state. When the signal is input to the circuit 7, in the fault state determination circuit 7, the first clock alarm 23 is detected by the alarm detection means 42 and is input to the state holding means 44 as the first clock alarm signal 28 from the alarm detection means 42. After that, in the state holding means 44, it is held for a period of one cycle of the clock abnormality detection cycle of the second clock 24, and then output to the fault state determination means 45 as the first clock alarm signal 29, The failure state determination means 45 receives the first clock alarm signal 29 and outputs the second clock alarm signal. Beam signal 30 to verify whether or not input, determines a fault occurrence state by the presence or absence of input of the second clock alarm signal 30.
[0065]
That is, as a result of the above-described confirmation of whether or not the second clock alarm signal 30 has been input by the failure state determination means 45, the second clock alarm 25 from the clock abnormality detection circuit 6 is sent to the failure state determination circuit 7. If not, the fault state determination means 45 determines that the watchdog timer circuit 2 is in the operating state because the second clock 24 of the clock generating circuit 4 has no abnormality, Since the watchdog timer / alarm 21 is not output even though the operation of the processor 1 is in an abnormal state due to the abnormality of 22, it is determined that the watchdog timer circuit 2 has failed. The operation of the processor 1 is abnormal due to the abnormality of the first clock 22, and the watchdog timer circuit 2 has failed. And outputs to the fault monitoring circuit 8a as a fault notification signal 31 to the third fault notification signal indicating that no work for.
[0066]
If the second clock alarm 23 is input from the clock abnormality detection circuit 6 to the failure state determination circuit 7 due to the clock abnormality of the second clock 24 of the clock generation circuit 4, the failure state determination means 45 The operation of the watchdog timer circuit 2 is not in a normal operation state due to the abnormality of the second clock 24 of the circuit 4, and the operation of the processor 1 is abnormal due to the abnormality of the first clock 22 of the clock generation circuit 3. It is determined that the operation of the watchdog timer circuit 2 is not in the normal operation state due to the abnormality of the second clock 24 and the abnormality of the first clock 22 of the clock generation circuit 3 is determined. A fourth failure notification signal indicating that the operation of the processor 1 is in an abnormal state due to the cause is output to the failure monitoring circuit 8a as a failure notification signal 31.
[0067]
Next, a second embodiment of the present invention will be described with reference to the drawings.
[0068]
FIG. 3 is a block diagram showing a configuration of a second embodiment of the state monitoring method of the watchdog timer circuit according to the present invention.
[0069]
The state monitoring method of the watchdog timer circuit shown in FIG. 3 is a clock generation that is connected to two processors, a processor 1a and a processor 1b, and that outputs a first clock 22 to each of the processors 1a and 1b. The circuit 3 is connected to the clock generating circuit 4 for outputting the second clock 24, and the clock generating circuit 3, the clock generating circuit 4, and the processor 1a. As a result of the determination, similarly to the failure state determination circuit 7 shown in FIG. 1, each failure notification signal from the first failure notification signal to the fourth failure notification signal for the system of the processor 1a is output as a failure notification signal 31a. The failure state detection unit 9a and the clock generation circuit 3 and the clock generation circuit 4 similarly to the failure state detection unit 9a Connected to the processor 1b and detects an alarm that occurs in each of them, and determines a failure state. As a determination result, each failure from the first failure notification signal to the fourth failure notification signal for the system of the processor 1b is determined. A failure state detection unit 9b that outputs a notification signal as a failure notification signal 31b; and a clock signal that is connected to the failure state detection units 9a and 9b and that receives the failure notification signals output from the failure state detection units 9a and 9b. It monitors a hardware failure occurring in the generation circuit 3 and the clock generation circuit 4 or a software operation abnormality occurring in the processors 1a and 1b, and monitors the status monitoring information of the watchdog timer circuit 2 to other devices that need it. And a failure monitoring circuit 8b for reporting the result.
[0070]
The failure state detection unit 9a includes a watchdog timer circuit 2, a clock abnormality detection circuit 5, a clock abnormality detection circuit 6, and a failure state determination circuit 7. Similarly, the failure state detection unit 9b also includes a failure state detection unit. A watchdog timer circuit 2, a clock abnormality detection circuit 5, a clock abnormality detection circuit 6, and a failure state determination circuit 7, each of which includes a watchdog timer circuit (not shown), two clock abnormality detection circuits, and a failure state determination circuit, respectively Is done.
[0071]
As described above, the state monitoring system of the watchdog timer circuit shown in FIG. 3 differs from the configuration of the state monitoring system of the watchdog timer circuit shown in FIG. 1 in the following points.
[0072]
That is, this is a state monitoring method of a watchdog timer circuit for the two processors 1a and 1b. Each of the processors 1a and 1b has a common clock generation circuit 3 and a clock generation circuit 4, and FIG. Instead of the fault monitoring circuit 8a shown, a clock generating circuit 3, a clock generating circuit 4, and a fault monitoring circuit 8b for monitoring a fault occurrence state of the processors 1a and 1b are provided.
[0073]
The operation of each unit in the state monitoring method of the watchdog timer circuit shown in FIG. 3 is the same as that of the state monitoring method of the watchdog timer circuit shown in FIG.
[0074]
As described above, in the state monitoring method of the watchdog timer circuit of the present invention, when a failure occurs in the clock generation circuit 3 and the clock 22 for processor operation becomes abnormal, the processor operating with the clock 22 1 becomes abnormal. As a result, even if the watchdog timer / alarm 21 is output from the watchdog timer circuit 2 to the fault state determination circuit 7, it is determined that the clock 22 for processor operation is abnormal. By notifying the failure state determination circuit 7 by the abnormality detection circuit 5, the failure state determination circuit 7 may determine whether the operation of the processor 1 is a software failure or an abnormal clock output due to the failure of the clock generation circuit 3. Is determined to be a hardware failure, and as a result of the determination, the watchdog timer The arm 21 is output to output as a second fault notification signal to the fault monitoring circuit 8a or fault monitoring circuit 8b that disorders of the above clock generating circuit 3 is caused. As a result, information indicating that the watchdog timer / alarm 21 is output from the fault monitoring circuit 8a or the fault monitoring circuit 8b is due to a fault in the clock generation circuit 3 is output to another device. The monitoring circuit 8a or the fault monitoring circuit 8b correctly notifies other devices that need the status monitoring information related to the watchdog timer circuit that the fault is caused by the clock generation circuit 3.
[0075]
That is, in the state monitoring method of the watchdog timer circuit of the present invention, when the clock 22 for processor operation becomes abnormal due to the failure of the clock generation circuit 3, the watchdog timer circuit 2 outputs a watchdog timer / alarm. However, the output of the watchdog timer / alarm is not reported to other devices that require the status monitoring information related to the watchdog timer circuit, and the alarm indicating that the clock 22 for processor operation is abnormal is output. Only output correctly.
[0076]
Further, in the state monitoring method of the watchdog timer circuit of the present invention, when the clock abnormality detection circuit 5 outputs the first clock alarm 23, it confirms whether or not the second clock 24 abnormality is detected. If it is confirmed that there is no abnormality in the second clock 24, the operation of the processor is in an abnormal state due to the abnormality in the first clock 22, and the watchdog timer circuit 2 is not operating due to a failure. If a third failure notification signal indicating that the second clock 22 is abnormal is confirmed by the above confirmation, the operation of the processor is abnormal due to the abnormality of the first clock 22, and By outputting a fourth failure notification signal indicating that the operation of the watchdog timer circuit 2 is not in a normal operation state due to the abnormality of the second clock 24, In a first clock 22 is an abnormal state is supplied, when the watchdog timer alarm 21 to be outputted is not outputted, it is possible to determine the cause easily.
[0077]
【The invention's effect】
As described above, the state monitoring method of the watchdog timer circuit according to the present invention is configured such that when the watchdog timer circuit outputs the watchdog timer / alarm, when the predetermined time elapses, the first clock becomes abnormal. Is confirmed, and if it is confirmed that there is no abnormality in the first clock, a first failure notification signal indicating abnormality of software on the processor is output. When an abnormality of the clock is confirmed, a second failure notification signal indicating that the operation of the processor is abnormal due to the abnormality of the first clock is output to the processor. The watchdog timer / alarm output from the watchdog timer circuit when the operation of the processor becomes abnormal due to the abnormal clock This prevents the erroneous determination that the software on the processor is abnormal on the basis of this, and has the effect of correctly reporting that the error is due to a clock abnormality supplied to the processor. I have.
[0078]
Further, when the first clock abnormality detection circuit outputs the first clock alarm, it is confirmed whether or not the second clock abnormality has been detected when a predetermined time has elapsed, and the second clock abnormality is detected. If it is confirmed that there is no abnormality, the third operation indicates that the operation of the processor is abnormal due to the abnormality of the first clock, and that the watchdog timer circuit is not operating due to the failure. If a failure notification signal is output and the above-mentioned check confirms that the second clock is abnormal, the operation of the processor is abnormal due to the abnormality of the first clock, and the abnormality of the second clock is detected. By configuring so as to output the fourth failure notification signal indicating that the operation of the watchdog timer circuit is not in the normal operation state due to the cause, the clock supplied to the processor becomes abnormal. Located state, when the watchdog timer alarm to be outputted is not outputted, has the effect that it is possible to determine the cause easily.
[Brief description of the drawings]
FIG. 1 is a block diagram showing a configuration of a first embodiment of a state monitoring method of a watchdog timer circuit according to the present invention.
FIG. 2 is a block diagram showing a configuration of a fault state determination circuit in the state monitoring method of the watchdog timer circuit shown in FIG.
FIG. 3 is a block diagram showing a configuration of a second embodiment of a state monitoring method of a watchdog timer circuit according to the present invention.
FIG. 4 is a block diagram showing a configuration of a state monitoring method of a conventional watchdog timer circuit.
[Explanation of symbols]
1 processor
1a, 1b processor
2 Watchdog timer circuit
3 Clock generation circuit
4 Clock generation circuit
5 Clock abnormality detection circuit
6 Clock abnormality detection circuit
7 Failure state judgment circuit
8a-8c fault monitoring circuit
9a, 9b Failure state detection unit
20 Watchdog timer clear control signal
21 Watchdog timer / alarm
22 First clock
23 1st clock alarm
24 Second clock
25 Second clock alarm
26, 27 Watchdog timer / alarm signal
28, 29 1st clock alarm signal
30 Second clock alarm signal
31 Failure notification signal
31a, 31b failure notification signal
41 Alarm detection means
42 Alarm detection means
43 Alarm detection means
44 state holding means
45 Failure state determination means

Claims (8)

A watchdog timer circuit that operates on the second clock and detects an abnormal operation of the processor; a first clock abnormal detection circuit that detects an abnormality of the first clock operating the processor; A second clock abnormality detection circuit for detecting an abnormality, wherein when the watchdog timer circuit outputs a watchdog timer alarm, the first clock abnormality is detected when a predetermined time has elapsed. And if it is confirmed that there is no abnormality in the first clock, a first failure notification signal indicating an abnormality in the software on the processor is output. When an abnormality of the first clock is confirmed, a second signal indicating that the operation of the processor is abnormal due to the abnormality of the first clock. Condition monitoring system of the watchdog timer circuit and outputting a fault notification signal. A watchdog timer circuit that operates on the second clock and detects an abnormal operation of the processor; a first clock abnormal detection circuit that detects an abnormality of the first clock operating the processor; A second clock abnormality detection circuit for detecting an abnormality, wherein the first clock abnormality detection circuit outputs a first clock alarm when the first clock abnormality detection circuit detects an abnormality of the first clock; A watchdog timer circuit that outputs a second clock alarm when the detection circuit detects an abnormality of the second clock, and outputs a watchdog timer alarm when the watchdog timer circuit detects an operation abnormality of the processor. Wherein the watchdog timer alarm is sent from the watchdog timer circuit. When the power is input, it is confirmed whether or not the first clock abnormality has been detected when a predetermined time has elapsed, and the first clock alarm is output from the first clock abnormality detection circuit. However, if it is confirmed that there is no abnormality in the first clock, it is determined that the software on the processor becomes abnormal, the operation of the processor becomes abnormal, and the watchdog timer / alarm is output. And outputting a first failure notification signal indicating an abnormality of the software on the processor, and when the confirmation confirms that the first clock is abnormal, the first clock is notified due to the abnormality of the first clock. When the operation of the processor is in an abnormal state, it is determined that the watchdog timer / alarm is output from the watchdog timer circuit, Condition monitoring system of the watchdog timer circuit operation of the processor for one clock abnormality and outputs a second fault notification signal indicating that the abnormal state. 3. The state monitoring method of the watchdog timer circuit according to claim 1, wherein the predetermined time is equal to one cycle of the first clock abnormality detection cycle performed by the first clock abnormality detection circuit. A state monitoring method for a watchdog timer circuit, characterized in that the period is a period of time. (A) a watchdog timer circuit that monitors an abnormality of software on the processor and outputs a watchdog timer / alarm when it is determined that the software is abnormal on the processor;
(B) a first clock generation circuit that generates a first clock for operating the processor and outputs the generated clock to the processor;
(C) detecting an abnormality of the first clock when the first clock output from the first clock generation circuit is in an abnormal state due to a failure of the first clock generation circuit; A first clock abnormality detection circuit that outputs a clock alarm,
(D) a second clock generation circuit for generating a second clock for operating the watchdog timer circuit and outputting the generated second clock to the watchdog timer circuit, and the second clock generation circuit due to a failure of the second clock generation circuit A second clock abnormality detection circuit for detecting the second clock abnormality when the second clock output from the second clock enters an abnormal state, and outputting a second clock alarm; In a state monitoring method of a watchdog timer circuit for monitoring occurrence of a timer alarm, the first clock alarm, and the second clock alarm,
(E) The watchdog timer alarm output from the watchdog timer circuit, the first clock alarm output from the first clock abnormality detection circuit, and the output from the second clock abnormality detection circuit When the watchdog timer / alarm is first output from the watchdog timer circuit in a state where no alarm of the second clock alarm has occurred, the watchdog timer / alarm is held, and Whether or not the first clock abnormality from the first clock generation circuit is detected when a period of one cycle of the abnormality detection period of the first clock performed by the first clock abnormality detection circuit has elapsed. Whether the first clock alarm is generated by the first clock abnormality detection circuit. If it is confirmed that there is no abnormality in the first clock without being output, it is determined that the watchdog timer / alarm has been output due to a software abnormality on the processor, and the Outputting a first failure notification signal indicating an abnormality of the software, and confirming the first clock alarm from the first clock abnormality detection circuit and outputting the first clock alarm signal from the first clock generation circuit; If an abnormality of the clock is confirmed, the operation of the processor becomes abnormal due to the abnormality of the first clock from the first clock generation circuit, and the watch dog timer circuit -It is determined that an alarm has been output, and the operation of the processor is abnormal due to an abnormality of the first clock of the first clock generation circuit. Condition monitoring system of the watchdog timer circuit comprising the fault condition determination circuit for outputting a second fault notification signal indicating that it is now state. 5. The state monitoring method for a watchdog timer circuit according to claim 4, wherein the first failure notification signal and the second failure notification signal are input, and a failure occurring in the first clock generation circuit and a failure occurring in the processor. A state monitoring method for a watchdog timer circuit, comprising: a failure monitoring circuit that monitors an abnormality of software to be executed. 5. The state monitoring method for a watchdog timer circuit according to claim 4, wherein said fault state determination circuit first sets said first clock alarm to said first clock alarm in a state where none of said alarms has occurred. When output from the clock abnormality detection circuit, the first clock alarm is held, and the time corresponding to one cycle of the second clock abnormality detection cycle performed by the second clock abnormality detection circuit has elapsed. Sometimes it is confirmed whether or not the abnormality of the second clock from the second clock generation circuit is detected, and the second clock alarm is not output from the second clock abnormality detection circuit in the confirmation. If it is confirmed that there is no abnormality in the second clock of the second clock generation circuit, the watchdog timer circuit operates. The watchdog timer / alarm is not output even though the operation of the processor is abnormal due to the abnormality of the first clock from the first clock generation circuit. Judging that the watchdog timer circuit has failed, the operation of the processor is in an abnormal state due to the abnormality of the first clock, and the watchdog timer circuit operates due to the failure. A third failure notification signal indicating that the second clock alarm is not output, and the second clock alarm is output from the second clock abnormality detection circuit in the confirmation, and the second clock alarm is output from the second clock generation circuit. If an abnormality is confirmed, the operation of the processor becomes abnormal due to the abnormality of the first clock from the first clock generation circuit. And, it is determined that the operation of the watchdog timer circuit is not in a normal operation state due to the abnormality of the second clock of the second clock generation circuit, and the abnormality of the first clock is determined. A fourth failure notification signal is output indicating that the operation of the processor is abnormal due to the cause, and the operation of the watchdog timer circuit is not normal due to the abnormality of the second clock. A state monitoring method for a watchdog timer circuit. 7. The state monitoring method for a watchdog timer circuit according to claim 6, wherein the first failure notification signal, the second failure notification signal, the third failure notification signal, and the fourth failure notification signal are inputted. A watchdog timer provided with a fault monitoring circuit for monitoring a fault occurring in the first clock generating circuit, a fault occurring in the second clock generating circuit, and a software abnormality occurring in the processor. Circuit status monitoring method. 5. The state monitoring system of a watchdog timer circuit according to claim 4, further comprising a first processor and a second processor as said processor, wherein said watchdog timer circuit is a first watchdog timer circuit and a second watchdog. A first failure state determination circuit and a second failure state determination circuit as the failure state determination circuit; and a third clock failure detection circuit and a fourth failure state detection circuit as the first clock failure detection circuit. A fifth clock abnormality detection circuit and a sixth clock generation circuit as the second clock abnormality detection circuit, wherein the first clock generation circuit has the first processor and the second processor. Outputting the first clock to a second processor, the third clock abnormality detection circuit, and the fourth clock generation circuit; The second clock generation circuit supplies the second clock to the first watchdog timer circuit, the second watchdog timer circuit, the fifth clock abnormality detection circuit, and the sixth clock generation circuit. Output, the first watchdog timer circuit is connected to the first processor, the second watchdog timer circuit is connected to the second processor, and the first fault condition determination circuit includes A first watchdog timer circuit is connected, the second failure state determination circuit is connected to the second watchdog timer circuit, and the first failure state determination circuit is connected to the third clock abnormality detection. Circuit and the fifth clock abnormality detection circuit are connected, and the second failure state determination circuit includes the fourth clock abnormality detection circuit and the sixth clock A normal detection circuit is connected, and the failure monitoring circuit is connected to the first failure state determination circuit and the second failure state determination circuit, and the first failure state determination circuit and the second failure state are connected. A state monitoring method for a watchdog timer circuit, wherein the first failure notification signal and the second failure notification signal output from a state determination circuit are output.

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