JP2004086520A - Monitoring control device and its method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a monitoring control device comprising a control panel including a processor and a monitoring panel for monitoring it and its method, facilitating processing when a processor is in failure. <P>SOLUTION: The monitoring control device comprises the control panel 1 including the processor 10 for controlling parts and the monitoring panel 2 for monitoring the normality of the processor 10, and its method uses the same. The monitoring panel 2 has a detecting circuit 22 for detecting a time-out using a watch dog timer 21, a factor register 23 for storing a detection signal for the time-out detected by the detecting circuit 22 and sending an interruption signal IRQ to the processor, a time-out flag 24 to be set concurrently with the detection signal for the time-out and cleared when the processor 10 is in normal operation, a resetting circuit 25 for resetting and restarting up the processor 10 when the time-out flag 24 is continuously set for a preset time, and a failure notifying circuit 26 for sending an alarm when it is restarted up but not reset normal. <P>COPYRIGHT: (C)2004,JPO

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a monitoring control device including a control panel having a processor for controlling each unit, a monitoring panel monitoring the normality of the processor, and a monitoring control method including a restart process of the processor.
[0002]
[Prior art]
A processor that performs control processing in various devices may cause a program runaway or a hang-up state in which control processing stops for some reason. Therefore, monitoring means using a watchdog timer for monitoring the operation state of the processor at predetermined time intervals is applied. This watchdog timer is also called a keepalive or a heartbeat. When the occurrence of an abnormal state of the processor is detected due to a timeout by the watchdog timer, the processor is reset and reset to the initial state. become.
[0003]
A communication control device or the like is known as a device for controlling each unit by the processor. For example, as shown in FIG. 4, a control panel 51 including a processor (CPU) 54 and a watchdog timer (WDT) 55, A single or a plurality of communication processing panels 53 having an interface function and a communication control function for the communication processing panel 53. The communication processing panel 53 is controlled by the processor 54 of the control panel 51 to control connection of a line via a network and various types of communication processing. It controls the transmission of information.
[0004]
The watchdog timer 55 monitors the processor 54 periodically. When a response from the processor 54 is not obtained periodically, the watchdog timer 55 times out. It is determined that an abnormality has occurred, and in order to prevent erroneous control of the communication processing panel 53 by the processor 54 in an abnormal state, the processor 54 is set in a fault state and an alarm is sent to a higher-level device. In accordance with the alarm, the maintenance staff searches for the cause of the abnormality, and performs a recovery operation by restarting the processor 54 or the like.
[0005]
Also, a pulse for monitoring runaway is sent from the processor at a predetermined time interval, and the pulse is monitored by a watchdog timer. When a pulse cannot be detected, a transmission control device that determines that the processor has become abnormal, resets the processor, and restarts the processor is known (for example, JP-A-2002-77750). reference).
There is also known an abnormality monitoring device in which the monitoring time monitored by the watchdog timer is made different depending on the type of the control task processed by the processor without fixing the monitoring time by the watchdog timer (for example, see Japanese Patent Application Laid-Open No. -244923).
[0006]
[Problems to be solved by the invention]
The processor is periodically monitored for normality using a watchdog timer.If the processor does not respond periodically, if the watchdog timer times out, it is determined that an error has occurred in the processor. In general, the processor is reset and restarted. However, in a communication control device or the like, when a processor that performs communication control is reset, each of the units that are controlled by the processor is also reset. All connection states are disconnected and return to the initial state. Therefore, there is a problem of service degradation.
[0007]
Therefore, it is possible to apply a means for preventing the network from being disrupted by detecting the timeout by the watchdog timer, causing the processor to be in a fault state, maintaining a connection state of a line controlled by the processor, and sending an alarm. Then, the maintenance staff searches for the location where the failure has occurred in accordance with the alarm transmission, performs a recovery operation, resets the processor based on the result, and returns to the original state by restarting.
[0008]
In this case, if a communication control device or the like controlled by the processor is installed in the station where the maintenance staff is located, it is possible to quickly start the recovery work according to the occurrence of the failure. However, when the network is distributed and connected to the network, such as a wireless base station in a wireless network, the maintenance staff is away from the management center where the maintenance staff is located. It will be difficult to get started. Therefore, there is a problem that the time required for the recovery from the failure becomes longer and the service is reduced.
[0009]
Also, if there is a timeout due to the watchdog timer based on a temporary malfunction of the processor due to lightning, etc., an alarm will also be sent out in that case, and if lightning strikes frequently, alarms will be issued frequently And there is a problem that the recovery work needs to be performed frequently.
[0010]
SUMMARY OF THE INVENTION It is an object of the present invention to perform processing such as restarting a processor when a timeout is detected by a watchdog timer that monitors the normality of the processor and after checking the possibility of self-recovery of the processor.
[0011]
[Means for Solving the Problems]
The monitoring control device of the present invention, which will be described with reference to FIG. 1, is a monitoring control device including a control panel 1 including a processor 10 for controlling each unit and a monitoring panel 2 for monitoring the normality of the processor 10. The monitoring panel 2 stores a detection circuit 22 for detecting a timeout by the watchdog timer 21 for periodically monitoring the normality of the processor 10, and a detection signal of the timeout by the detection circuit 22, and And a time-out flag 24 that is set by a time-out detection signal and is cleared when the processor 10 operates normally. When the time-out flag 24 is continuously set for a predetermined time, the processor 10 And a reset circuit 25 for resetting and restarting.
[0012]
The reset circuit 25 counts the number of times a timeout detection signal is repeatedly output from the detection circuit 22 while the timeout flag 24 is being set, and resets the processor when the number reaches a preset number. Can be prepared. Further, the processor 10 of the control panel 1 performs a restart process by a reset signal from the reset circuit 25 of the monitoring panel 2 and clears the timeout flag 24 of the monitoring panel 2 when the application is normally started. It is. Further, the monitoring panel 2 causes the processor 10 of the control panel 1 to perform a restarting process in response to a reset signal from the reset circuit 25, and sends a warning signal to an external device when normal startup is not performed. A circuit 26 can be provided.
[0013]
The monitoring control method according to the present invention includes a control panel 1 including a processor 10 for controlling each unit, and a monitoring panel 2 for monitoring the normality of the processor 10. When a timeout is detected by the watchdog timer 21 of the monitoring panel 2, The time-out flag 24 is set, an interrupt signal IRQ is sent to the processor 10, and the time-out flag 24 is cleared by the normal operation of the processor 10. When the time-out flag 24 is continuously set for a predetermined time, the processor 10 And a step of sending a reset signal from the reset circuit 25 to restart. A process of causing the processor 10 to restart, clearing the timeout flag 24 by normal startup, and sending an alarm signal from the fault occurrence notifying circuit 26 to an external device when normal startup is not performed. Can be included.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
FIG. 1 is an explanatory view of an embodiment of the present invention, wherein 1 is a control panel, 2 is a monitoring panel, 10 is a processor (CPU), 11 to 13 show the states and functions of the processor, 11 is an infinite state, 12 Denotes a clear processing unit, and 13 denotes a restart processing unit. 21 is a watchdog timer (WDT), 22 is a timeout detection circuit, 23 is a factor register, 24 is a timeout flag, 25 is a reset circuit, and 26 is a failure occurrence notification circuit. IRQ indicates an interrupt signal, WDTINT indicates a timeout detection signal, and RFL indicates a reset notice signal.
[0015]
The monitoring panel 2 stores a detection circuit 22 for detecting a timeout of the watchdog timer 21 for periodically monitoring the normality of the processor 10, and a detection signal of the timeout by the detection circuit 22, and stores the timeout signal for the processor 10. A factor register 23 for sending out an input signal IRQ, a time-out flag 24 set by a time-out detection signal from the detection circuit 22 to indicate that a time-out is occurring, A reset signal that sends a reset signal to the processor to perform a restart process, and a fault occurrence notification circuit that notifies an external device of a fault occurrence when the processor does not recover to a normal state even after the restart process. 26.
[0016]
Further, the timeout detection signal is repeatedly generated within a predetermined time while the timeout flag 24 is being set. Accordingly, the time-out detection signal is counted by the counter, and the time when the count content indicates the predetermined number of times can be set as the predetermined time. The counter in this case can be provided in the factor register 23, the timeout flag 24, or the reset circuit 25. Further, a comparison circuit or the like for comparing the number of times of detection of the count content of this counter with the number of times set in advance can be provided in the factor register 23 or the reset circuit 25. Then, a configuration can be provided in which the counter is reset when a reset signal to the processor 10 is transmitted from the reset circuit 25.
[0017]
The fault occurrence notifying circuit 26 outputs a ground fault circuit output for notifying the occurrence of a fault by sending ground, an overhead lamp output for lighting an overhead lamp, It has a function of transmitting a FAIL lamp output or the like that indicates a function stop by lighting as an alarm signal to an external device. For example, a failure occurrence notification can be made to a device or the like where a maintenance staff is present.
[0018]
The processor 10 of the control panel 1 performs normal access to the detection circuit 22 of the monitoring panel 2 to indicate the normality. Is detected and the timeout detection signal WDTINT is input from the detection circuit 22 to the factor register 23 to notify the occurrence of timeout.
[0019]
The factor register 23 sets the timeout flag 24 in response to the timeout detection signal WDTINT, and then sends an interrupt signal IRQ to the processor 10, and if the processor 10 does not recover by itself, that is, after a predetermined time has elapsed, or The detection signal WDTINT is counted up a predetermined number of times, and when the timeout flag 24 is set, a reset notice signal RFL is sent to the reset circuit 25. The reset circuit 25 sends a reset signal to the processor 10 a predetermined time after the reset notice signal RFL.
[0020]
The software of the processor 10 of the control panel 1 sets the infinite loop state 11 by the interrupt signal IRQ. If the processor 10 does not self-heal after this state or after the first timeout detection, the next timeout detection signal WDTINT is input from the detection circuit 22 to the factor register 23. When a counter for counting the timeout detection signal WDTINT is provided in, for example, the factor register 23, when the first timeout detection signal WDTINT is counted up and the next timeout detection signal WDTINT is counted up, the count becomes 2. In this case, for example, assuming that the set number is 2, the reset notice signal RFL is transmitted from the factor register 23 to the reset circuit 25. The reset circuit 25 sends out a reset signal to the processor 10 according to the reset notice signal RFL.
[0021]
In the processor 10, the re-startup processing unit 13 performs the internal re-startup by the reset signal, and when the application is normally started up by the re-startup, the clear processing unit 12 clears the timeout flag 24. At this time, the counter for counting the timeout detection signal is also cleared. If the processor 10 does not start up normally even after this restart, the failure occurrence notifying circuit 26 may output a failure to an external device (not shown) due to a ground circuit output, overhead lamp output, FAIL lamp output, or the like. Perform occurrence notification.
[0022]
FIG. 2 is a sequence explanatory diagram of the embodiment of the present invention. FIG. 2 shows an interrupt signal IRQ input from the factor register 23 to the processor 10, a time-out signal WDTINT from the detection circuit 22, and an input to the reset circuit 25 from the detection circuit 22. The reset notice signal RFL to be executed, the reset signal inputted from the reset circuit 25 to the processor 10, the outputs of the ground, overhead lamp and FAIL lamp from the failure occurrence notifying circuit 26, and the state of the processor 10 are shown. This state indicates a normal state, a processor CPU fault state, a processor CPU reset state, and a restart state.
[0023]
In the normal state of the processor 10, the interrupt signal IRQ, the timeout detection signal WDTINT, the reset notice signal RFL, and the reset signal are set to "1" (high level H). Is "0" (low level L). When the timeout detection signal WDTINT from the detection circuit 22 becomes "0" due to the occurrence of an abnormality in the processor 10, the timeout flag FLAG is set to "1". Then, after a predetermined time, for example, 1 to 2 seconds, the interrupt signal IRQ (“0”) is transmitted from the factor register 23 to the processor 10. At this time, the processor 10 enters a fault state.
[0024]
Further, the software of the processor 10 enters an infinite loop state by the interrupt signal IRQ, and after a lapse of a predetermined time t1 from the setting of the timeout flag FLAG, or when the timeout detection signal WDTINT is output from the detection circuit 22 again as described above, The reset notice signal RFL (“0”) is sent from the factor register 23 to the reset circuit 25. Therefore, the preset predetermined time t1 or the preset number of timeout detections can be set to a value optimized in response to a case where timeout detection occurs relatively frequently due to lightning strike or the like. The reset circuit 25 sends a reset signal (“0”) to the processor 10 after a predetermined time t2 from the reset advance signal RFL (“0”) according to the reset advance signal RFL. In this case, the predetermined time t1 can be set to, for example, 1-2 s, and t2 can be set to 4 ms.
[0025]
The processor 10 enters a reset state in response to a reset signal from the reset circuit 25, and the re-startup processing unit 13 starts a re-startup process and enters a re-startup state. When the application starts up normally, the clear processing unit 12 clears the timeout flag 24 and returns to the normal state.
[0026]
When the processor 10 does not start up normally due to the reset signal, the processor 10 is in a fault state. In this state, the fault occurrence notifying circuit 26 outputs the ground circuit output ("1") and the overhead lamp. The output ("1") and the FAIL lamp output ("1") are sent to an external device. Thereby, the overhead lamp of the device such as the communication processing panel is turned on, the FAIL lamp of the device such as the control panel is turned on, the buzzer sounds or the lamp is turned on at the place where the maintenance staff is located, and the occurrence of the failure of the processor 10 is notified can do.
[0027]
Further, when the reset CR of the processor 10 is performed by manual or remote control, that is, the reset signal is set to “0”, the processor 10 is reset, and the processor 10 is restarted. The circuit 26 sends the ground circuit output ("1"), the overhead lamp output ("1"), and the FAIL lamp output ("1") to external devices.
[0028]
The processor 10 may be self-recovered by the interrupt signal IRQ, or may be returned to the normal state by the restart process by the reset signal. In this case, no alarm is sent, and the maintenance personnel are dispatched. There is no need to do so. That is, even if a timeout occurs due to a temporary watchdog timer, it is possible to immediately perform a process of determining whether self-recovery is possible without causing a failure of the processor 10.
[0029]
FIG. 3 shows a flowchart of the embodiment of the present invention, and shows an outline of the operation when a timeout flag is set by timeout detection by a watchdog timer and a reset signal is sent to the processor after a predetermined time has elapsed. First, it is determined whether or not timeout is detected by the watchdog timer (A1). If timeout detection is not performed in the normal state of the processor, it is determined whether or not the number of times of timeout occurrence is greater than 0 (A2). If the value is larger than 0, the number of occurrences is cleared (A3), and the process proceeds to step (A1) as in the case where the value is not larger than 0.
[0030]
In the case of timeout detection, it is determined whether the timeout occurrence count is a value greater than 0 (A4). If the timeout occurrence count is not greater than 0, that is, if the timeout occurrence count has not been counted up in the past, the occurrence count is counted. (A5), a timeout by the watchdog timer is set in the factor register 23, a timeout flag FLAG is set, an interrupt signal IRQ is transmitted to the processor CPU, and a reset notice signal RFL is transmitted after a predetermined time ( A6).
[0031]
It is determined whether or not the reset notice signal RFL has been cleared (A7). If there is a clear process due to self-recovery of the processor CPU, the process proceeds to step (A1). A reset signal is sent to the CPU to perform a restart process (A8). Then, the process proceeds to step (A1) to determine whether a timeout has been detected.
[0032]
When the processor CPU normally starts up by the restarting process, the timeout detection is not performed. However, when the processor CPU does not return to the normal state by the restarting process, the timeout detection is performed. Since the value has been counted up in A5), the value is larger than 0, and the processor CPU determines that the state is a fault (A9). An alarm is sent for each output (A10). By sending this alarm, maintenance work is performed by the maintenance staff.
[0033]
【The invention's effect】
As described above, the present invention includes the control panel 1 including the processor 10 for controlling the circulating section, and the monitoring panel 2 for monitoring the normality of the processor 10. 10 is monitored, a timeout flag 24 is set when a timeout is detected, an interrupt signal IRQ is transmitted to the processor 10, and after a predetermined time has elapsed, a reset signal is transmitted to the processor 10 and the processor 10 is restarted. When the processor 10 recovers itself before the restart processing, the reset processing becomes unnecessary. When the processor 10 returns to the normal state by the restart processing, the timeout flag 24 and the like are cleared. Then, it can be automatically restored to the original state. Then, when the normal state is not restored even by the restarting process, an alarm is transmitted to notify maintenance personnel of the occurrence of a failure. Therefore, there is an advantage that the maintenance management of the processor 10 in a remote place or the like becomes easy.
[Brief description of the drawings]
FIG. 1 is an explanatory diagram of an embodiment of the present invention.
FIG. 2 is a sequence explanatory diagram of the embodiment of the present invention.
FIG. 3 is a flowchart of an embodiment of the present invention.
FIG. 4 is an explanatory diagram of a communication control device.
[Explanation of symbols]
REFERENCE SIGNS LIST 1 control panel 2 monitoring panel 10 processor 11 infinite loop state 12 clear processing unit 13 restart processing unit 21 watchdog timer (WDT)
22 Detection circuit 23 Cause register 24 Timeout flag 25 Reset circuit 26 Failure occurrence notification circuit

Claims (6)

In a monitoring and control device including a control panel including a processor that controls each unit and a monitoring panel that monitors the normality of the processor,
The monitoring panel is configured to detect a timeout by a watchdog timer for periodically monitoring the normality of the processor, store a timeout detection signal by the detection circuit, and transmit an interrupt signal to the processor. A time-out flag, a time-out flag that is set by the time-out detection signal and cleared during normal operation of the processor, and a processor that is reset and restarted when the time-out flag is continuously set for a predetermined time. And a reset circuit for causing the monitoring and control device to have a configuration. The reset circuit counts the number of times a timeout detection signal is repeatedly output from the detection circuit while setting the timeout flag, and resets the processor when the number reaches a preset number. The supervisory control device according to claim 1, further comprising: The processor of the control panel is configured to perform a restart process by a reset signal from the reset circuit of the monitoring panel, and to clear the timeout flag of the monitoring panel when the application is normally started. The monitoring control device according to claim 1, wherein The monitor panel performs a restart process of the processor of the control panel according to a reset signal from the reset circuit, and a failure occurrence notification circuit that sends an alarm signal to an external device when normal startup is not performed. The monitoring control device according to claim 1, wherein the monitoring control device is provided. A control panel including a processor for controlling each unit; and a monitoring panel for monitoring the normality of the processor. When a timeout is detected by a watchdog timer of the monitoring panel, a timeout flag is set, and an interrupt signal is sent to the processor. Sending a reset signal to the processor when the timeout flag is continuously set for a predetermined period of time to send a reset signal to restart the processor when the timeout flag is continuously set for a predetermined time. A monitoring control method characterized by the above-mentioned. Including a step of causing the processor to restart, clearing the timeout flag by normal startup, and sending an alarm signal from the fault occurrence notification circuit to the external device when normal startup is not performed. 6. The monitoring control method according to claim 5, wherein:

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