TWI390398B - Method and system for monitoring and processing running status of a computer - Google Patents

Description

Computer running state detection and processing method and system

The invention relates to a computer operating state detection and processing method and system.

Downtime is one of the most common and complex failures in the process of using a computer, and it is one of the main causes of business interruption. The so-called crash, usually refers to the display content on the computer display screen, but the computer is not running for a long time. There are many reasons for the crash, which may be caused by computer infection, computer hardware failure, software conflict, hardware and software conflicts.

At present, most of the detection and processing methods of computer system crashes are reported by the computer to the remote unit (server or network administrator) through the network, and the remote unit is based on the received Numerical data to determine whether the computer being monitored is functioning properly. If an abnormality occurs, the remote system transmits a system reset signal to the monitored computer system via the network.

The remote monitoring method involves complex data exchange protocols, and must consider the security of the network. Generally, it must rely on expensive chips (such as BMC (Baseboard Management Controller) control chips) and supporting processing software to avoid system length. The time is in a state of being down.

In view of the above, it is necessary to provide a computer operating state detection and processing method and system, which can effectively detect and deal with the computer crash state, and can reduce the circuit design cost.

A computer running state detecting and processing system for detecting whether a computer is in a normal running state, and automatically restarting the computer when an abnormality occurs in the running of the computer. The computer includes a super input and output chip, a programmable logic element, a south bridge chip, and a device driver. The device driver is configured to control the super input and output wafer to generate and send a state detection start signal to the programmable logic device, and to control the super input and output wafer to generate and send a periodic signal to the programmable logic device. The programmable logic component is configured to receive a state detection start signal sent by the super input/output chip, and is configured to send a restart signal to the south bridge chip when the periodic signal sent by the super input/output chip is not received within a preset time. The south bridge chip is used to restart the computer after receiving the restart signal sent by the programmable logic element.

A computer running state detecting and processing method for detecting whether a computer is in a normal running state, the computer comprising a super input and output chip, a programmable logic component and a south bridge chip, the method comprising the following steps: (A) a computer device driver The program controls the super input/output chip to generate and send a status detection start signal to the programmable logic element; (B) the programmable logic element receives the detection start signal sent by the super input/output chip; (C) the programmable logic element The timer starts counting; (D) determining whether the programmable logic component receives the periodic signal sent by the super input/output chip; (E) determining whether the timer count exceeds the preset time if the periodic signal is not received; (F) If the timer expires more than the preset time, a restart signal is sent to the south bridge chip; (G) the south bridge chip restarts the computer.

Compared with the prior art, the present invention can pass the super input and output chip and can The communication status of the programming logic component determines whether the computer is operating normally, and automatically restarts the computer when an abnormality occurs in the computer.

1 is a system architecture diagram of a preferred embodiment of a computer operating state detection and processing system of the present invention. The system includes a host 10 and an operating system 20. The host 10 is configured to execute the operating system 20, which includes a super input/output (Super I/O) chip 100, a programmable logic device (CPLD) 110, a south bridge chip 120, and an oscillator (oscillator). ) 130. The operating system 20 includes a device driver 200 that controls the Super I/O wafer 100.

The Super I/O chip 100 realizes connection and communication with the CPLD chip 110 through three general purpose input/output (GPIO) interfaces GPIO#1, GPIO#2, and GPIO#3, in this embodiment. GPIO#1, GPIO#2, and GPIO#3 are respectively configured as output, input, and output functions.

The CPLD chip 110 transmits three input/output (I/O) interfaces I/O#1, I/O#2, and I/O#3 connected to GPIO#1, GPIO#2, and GPIO#3, respectively. In connection with the connection and communication with the Super I/O chip 100, in the present embodiment, I/O #1, I/O #2, and I/O #3 are respectively configured as input, output, and input functions.

The south bridge wafer 120 is connected and communicated with the CPLD wafer 110 via a "RESET" pin (not shown). This "RESET" pin can be used to restart the host 10.

In addition, the CPLD chip 110 further includes a determination module 111 and a transmission module 112. The determining module 111 is configured to determine whether the operation of the host computer 10 is normal through the communication status of the Super I/O chip 100 and the CPLD chip 110. The sending module 112 is configured to send a restart signal to the south bridge wafer 120 when the host 10 runs abnormally. Host 10. The module referred to in the present invention is a computer program segment that performs a specific function, and is more suitable for describing the execution process of the software in the computer than the program.

Further, the CPLD wafer 110 further includes a timer 113.

Oscillator 130 provides the operating frequency of timer 113.

The operating principle of the computer running state detection and processing system is as follows: The device driver 200 controls the Super I/O chip 100 to generate and transmit a start detection signal and a periodic signal to the CPLD wafer 110; the CPLD wafer 110 receives the Super I/O chip. After the start detection signal transmitted by 100, the trigger timer 113 starts to count from zero (t=0), and the determination module 111 determines whether the CPLD wafer 110 receives the Super I/O within a preset timing period (eg, t=m period). The periodic signal sent by the chip 100; if the CPLD chip 110 receives the periodic signal within a preset timing period, indicating that the operating system 20 is operating normally, the transmitting module 112 sends a reply message and a timer to the Super I/O chip 100. 113 restarts from zero; if the CPLD wafer 110 does not receive the periodic signal within the preset timing period, indicating that the operating system 20 is abnormal, the transmitting module 112 sends a restart signal to the south bridge wafer 120, and the south bridge wafer 120 is restarted. Host 10.

2 is a flow chart of a preferred embodiment of a method for detecting and processing a computer operating state according to the present invention. First, the host 10 is powered on, and the operating system 20 is started. The device driver 200 controls the Super I/O chip 100 to generate a state detection start signal S, and transmits the state detection start signal S to the CPLD wafer 110 (step S10). The CPLD wafer 110 receives the state detection start signal S transmitted from the Super I/O wafer 100 (step S20). The timer 113 starts timing t=0 (step S30). The judging module 111 judges whether or not the CPLD wafer 110 receives the signal P (hereinafter referred to as "periodic signal P") periodically transmitted by the Super I/O wafer 100 (step S40). Upon receiving the periodic signal P, the transmitting module 112 transmits the reply signal A to the Super I/O wafer 100 (step S50), and the flow returns to step S20. If the periodic signal P is not received, the determination module 111 determines whether the timer 113 counts for more than a preset time, such as a period of m (m > 0) signals P (step S50). If the preset time has not passed, the flow returns to step S40. If the preset time is exceeded, the transmitting module 112 transmits a restart signal R to the south bridge wafer 120 (S60). The south bridge wafer 120 restarts the host 10 to re-import the operating system 20 (step S70).

As shown in FIG. 3, it is a signal diagram when the host 10 is operating normally. When the host 10 is operating normally, that is, the operating system 20 is operating normally, the device driver 200 controls the Super I/O chip 100 to generate a state detection start signal S, and controls the Super I/O wafer 100 to generate a periodic signal P. The CPLD chip 110 returns a signal A every time it receives the signal P sent by the Super I/O. When the host 10 is operating normally, the signal A is also a periodic signal, and there is only a delay in time with respect to the signal P. The "RESET" pin of the south bridge wafer 120 is always at a high potential.

As shown in FIG. 4, it is a schematic diagram of the signal when the host 10 runs an abnormality. When the host 10 is abnormal during operation, that is, when the operating system 20 is dead The device driver 200 cannot normally drive the Super I/O chip 100 to generate and transmit a periodic signal P. When the CPLD wafer 110 does not receive the signal P for more than a predetermined time (e.g., the period of the m signals P), the CPLD wafer 110 transmits a restart signal R to the south bridge wafer 120. The "RESET" pin of the south bridge wafer 120 transitions from a high potential to a low potential, and the host 10 is restarted.

The above is only the preferred embodiment of the present invention, and has been used in a wide range of applications. Any other equivalent changes or modifications which are not departing from the spirit of the present invention should be included in the following claims. Inside.

10‧‧‧Host

100‧‧‧Super I/O Chip

110‧‧‧Programmable logic components

111‧‧‧Judgement module

112‧‧‧Transmission module

113‧‧‧Timer

120‧‧‧Southbridge

130‧‧‧Oscillator

20‧‧‧ operating system

200‧‧‧Device Driver

1 is a system architecture diagram of a preferred embodiment of a computer operating state detection and processing system of the present invention.

2 is a flow chart of a preferred embodiment of a method for detecting and processing a computer operating state according to the present invention.

Figure 3 is a schematic diagram of the signal when the computer is in normal operation.

Figure 4 is a schematic diagram of the signal when the computer is running abnormally.

10‧‧‧Host

100‧‧‧Super I/O Chip

110‧‧‧Programmable logic components

111‧‧‧Judgement module

112‧‧‧Transmission module

113‧‧‧Timer

120‧‧‧Southbridge

130‧‧‧Oscillator

20‧‧‧ operating system

200‧‧‧Device Driver

Claims (7)

A computer running state detecting and processing system for detecting whether a computer is in a normal running state, and automatically restarting a computer when an abnormality occurs in a computer operation, the computer including a super input/output super I/O chip, a programmable logic component CPLD and Southbridge chip: the computer further includes a device driver for controlling the Super I/O chip to generate and send a state detection start signal to the CPLD, and for controlling the Super I/O chip generation and transmission cycle The CPLD is used to receive the status detection start signal sent by the Super I/O chip, and is used to send a restart when the preset time is exceeded and the periodic signal sent by the Super I/O chip is not received. The signal is sent to the south bridge chip; and the south bridge chip is used to restart the computer after receiving the restart signal sent by the CPLD. The computer operating state detection and processing system of claim 1, wherein the Super I/O chip is connected to and communicates with the CPLD through a universal input/output interface. The computer operating state detection and processing system according to claim 1, wherein the CPLD further includes a timer for starting timing when receiving a detection start signal sent by the Super I/O chip. And used to determine whether the periodic signal is received within a preset time. The computer operating state detection and processing system according to claim 3, wherein the CPLD is further configured to send a reply signal when receiving a periodic signal sent by the Super I/O chip within a preset time. Go to the Super I/O chip and reset the timer to zero. A computer running state detecting and processing method for detecting whether a computer is in a normal running state, the computer comprising a super input/output super I/O chip, a programmable logic element CPLD and a south bridge chip, the method comprising the following steps: a computer The device driver controls the Super I/O chip to generate and send a status detection start signal to the CPLD; the CPLD receives the detection start signal sent by the Super I/O chip; the timer of the CPLD starts timing; and determines whether the CPLD receives a periodic signal sent to the Super I/O chip; if the periodic signal is not received, it is determined whether the timer counts exceed a preset time; if the timer expires more than the preset time, a restart signal is sent to the south bridge chip; And the South Bridge chip restarts the computer. The method for detecting and processing a computer operating state according to claim 5, further comprising the steps of: sending a reply message to Super I/ if the timer does not exceed the preset time and the CPLD receives the periodic signal. The O wafer; and the step of returning the timer timing restarts the timing. The method for detecting and processing a computer operating state according to claim 5, further comprising the steps of: if the timer does not exceed the preset time and the CPLD does not receive the periodic signal, returning to determine whether the received signal is received The step of describing the periodic signal.