TW200841170A - Method and system for monitoring and processing running status of a computer - Google Patents

Method and system for monitoring and processing running status of a computer Download PDF

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TW200841170A
TW200841170A TW96111594A TW96111594A TW200841170A TW 200841170 A TW200841170 A TW 200841170A TW 96111594 A TW96111594 A TW 96111594A TW 96111594 A TW96111594 A TW 96111594A TW 200841170 A TW200841170 A TW 200841170A
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computer
programmable logic
chip
signal
output
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TW96111594A
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Chinese (zh)
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TWI390398B (en
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Cong-Feng Wei
Po-Chang Wang
Fu-Chuan Chen
Wei-Yuan Chen
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Hon Hai Prec Ind Co Ltd
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Abstract

A system for monitoring and processing running status of a computer is provided. The computer includes a super input/output (Super I/O) chipset, a complex programmable logic device (CPLD) and a south bridge chipset. The Super I/O chipset generates a start signal and sends the start signal to the CPLD. The CPLD receives the start signal, and sends a restart signal to the south bridge chipset if not receiving any periodical signal from the Super I/O chipset over a preset time. The south bridge chipset restarts the computer when receives the restart signal. A related method is also disclosed.

Description

200841170 九、發明說明: . 【發明所屬之技術領域】 本發明涉及一種電腦運行狀態偵測及處理方法和系 Μ 統。 【先前技術】 當機是用戶在使用電腦過程中最常見、最複雜的故障 之一,也是造成企業服務中斷的主要原因之一。所謂當機, 通常是指電腦顯示幕幕上有顯示内容,但電腦長時間處於 * 不運行狀態。造成當機的原因很多,有可能是電腦受病毒 感染、電腦硬體發生故障、軟體衝突、硬體與軟體衝突等 等。 目前電腦系統當機的偵測及處理方式,大部分是由電 腦將其本身定時記錄的系統狀態透過網路回報給遠端單位 (伺服器或網管人員)處理,該遠端單位則根據接收的數 值資料,判斷受其監控的電腦是否正常運作。若發生異常, 則該遠端系統透過網路傳送系統重置信號至受監控的電腦 糸統。 上述遠端監控方法涉及複雜的資料交換協定,同時又 必須考慮網路的安全性問題,一般必須依賴昂貴的晶片(如 BMC ( Baseboard Management Controller )控制晶片)與配 套的處理軟體,才能避免系統長時間處於當機狀態。 【發明内容】 鑒於以上内容,有必要提供一種電腦運行狀態偵測及 處理方法和系統,可有效偵測並處理電腦死機狀態,且能 6 200841170 降低電路設計成本。200841170 IX. Description of the Invention: [Technical Field] The present invention relates to a computer operating state detection and processing method and system. [Prior Art] The downtime is one of the most common and complicated failures in the process of using a computer, and is one of the main causes of business interruption. The so-called crash, usually refers to the display content on the computer display screen, but the computer is in * not running for a long time. There are many reasons for the crash, which may be caused by computer infection, computer hardware failure, software conflict, hardware and software conflicts. At present, most of the detection and processing methods of computer system crashes are reported by the computer to the remote unit (server or network administrator) through the network, and the remote unit is based on the received Numerical data to determine whether the computer being monitored is functioning properly. If an abnormality occurs, the remote system transmits a system reset signal to the monitored computer via the network. The above remote monitoring method involves a complicated data exchange protocol, and at the same time, the security of the network must be considered. Generally, an expensive chip (such as a BMC (Baseboard Management Controller) control chip) and a corresponding processing software must be relied on to avoid the system length. The time is in a state of being down. SUMMARY OF THE INVENTION In view of the above, it is necessary to provide a computer operating state detection and processing method and system, which can effectively detect and deal with a computer crash state, and can reduce the circuit design cost.

一種電腦運行狀態偵測及處理系統,用於偵測電腦是 否處於正常運行狀態,並當電腦運行發生異常時,自動重 啓電腦。所述電腦包括超級輸入輸出晶片、可編程邏輯元 件、南橋晶片及設備驅動程式。所述設備驅動程式用於控 制所述超級輪入輸出晶片產生並發送一個狀態偵測開始信 號至可編程邏輯元件,並用於控制所述超級輸入輸出晶片 産生並發送週期性信號至可編程邏輯元件。所述可編程邏 輯讀用於接收超級輸人輪出晶片發送的狀態測開始信 遽、並用於當超過預設時間未收到超級輸入輸出晶片發送 =週^旧5魂時,發送-個重啓信號至南橋晶片。所述的 f曰曰片用於在收到可編程邏輯元件發送的重啓信號後, 重新啓動電腦。 一種電月甾、室“、 ^ 逆订狀態偵測及處理方法,用於偵測電腦是 绝=、二拉吊運行狀態’該電腦包括超級輪入輸出晶片、可 r件及南橋晶片,該方法包括以下步驟:(A)電 個二動程式控制所述超級輸入輸出晶片産生並發送 .. °彳5唬至可編程邏輯元件;(B)可編程邏 軏儿件接收超級於λ ^ ^ 可迫拉f奴 输入輪出晶片發送的偵測開始信號;(C) 元件是否 的計時器開始計時;(CO判斷可編程邏輯 若夫跄5^仏到超級輪入輪出晶片發送的週期性信號;(E) Μ時門述週期性信號,則判斷計時器計時是否超過預 口又4間,(F )若朴 缺5表抵θ 4 4為計時超過預設時間,則發送重啓信 就至南橋晶片;f 、U)南橋晶片重啓電腦。 200841170 相較於習知技術,本發明可透過超級輸入輸出晶片與 - 可編程邏輯元件的通信狀況判斷電腦運行是否正常’旅當 , 電腦運行發生異常時,自動重啓電腦。 【實施方式】 如圖1所示,係本發明電腦運行狀態偵測及處理系統 較佳實施例的系統架構圖。該系統包括主機10及作業系統 20。主機10用於執行作業系統20,其包括超級輸入輸出 鲁 (super input/output,Super I/O)晶片 100、可編程邏輯元 件(complex programmable logic device,CPLD) 110、南 橋晶片120及振蕩器(oscillator) 130。作業系統20包括 設備驅動程式200,該設備驅動程式200控制Super I/O晶 片 100。 其中,Super I/O晶片100透過三個一般輸入輸出 (general purpose input/output,GPIO )介面 GPI〇#l、 GPIO#2、GPIO#3實現與CPLD晶片110的連接及通信, % 於本實施例中,GI>IO#l、GHO#2、GFIO#3分別配置爲輸 出、輸入、輸出功能。 CPLD晶片110透過三個分別與GPI〇#l、GPIO#2、 GPIO#3 相連的輸入輸出(input/output,I/O)介面 i/q#i、 I/〇#2、I/〇#3實現與Super I/O晶片100的連接與通信,於 本實施例中,I/0#l、I/0#2、I/0#3分別配置爲輪入、輸出、 輸入功能。 南橋晶片120透過一個“RESET”接腳(圖中未示出) 實現與CPLD晶片110的連接與通信。該“RESET,,接腳 8 200841170 可用於重啓主機ίο。 此外,CPLD晶片11〇還包括判斷模組ιη、發送模組 112。判斷模組111用於透過super I/O晶片1〇〇與CPLD 晶片110的通信狀況判斷電腦主機1〇運行是否正常;發送 模組112用於當主機1〇運行發生異常時,發送重啓信號至 南橋晶片120重啓主機1〇。本發明所稱的模組是完成一特 定功能的電腦程式段,比程式更適合於描述軟體在電腦中 的執行過程。A computer running state detecting and processing system for detecting whether a computer is in a normal running state, and automatically restarting the computer when an abnormality occurs in the running of the computer. The computer includes a super input and output chip, a programmable logic element, a south bridge chip, and a device driver. The device driver is configured to control the super wheel input output chip to generate and send a state detection start signal to the programmable logic component, and to control the super input and output chip to generate and send a periodic signal to the programmable logic component . The programmable logic read is used to receive a state measurement start signal sent by the super input wheel and is used to send a weight when the super input and output chip is not received for more than the preset time. Signal to the south bridge chip. The f-chip is used to restart the computer after receiving a restart signal sent by the programmable logic element. An electric crescent, a room ", ^ reverse order state detection and processing method for detecting that the computer is absolutely =, two pull crane running state" The computer includes a super wheel input output chip, a r piece and a south bridge chip, The method comprises the following steps: (A) an electric two-way program controls the super input and output wafer to generate and transmit: .彳5唬 to the programmable logic element; (B) the programmable logic device receives more than λ ^ ^ The detection start signal sent by the chip can be forced to pull the slave input; (C) whether the timer of the component starts counting; (CO judges the programmable logic to send the periodic signal sent by the super-in and out-out wafers) (E) When the periodic signal is described, it is judged whether the timer counts more than 4 times in the pre-port. (F) If the PC is not enough, the time is longer than the preset time, then the restart signal is sent. The south bridge chip; f, U) the south bridge chip restarts the computer. 200841170 Compared with the prior art, the present invention can judge whether the computer is running normally through the communication status of the super input/output chip and the programmable logic element. Automatically occurs when an exception occurs [Embodiment] FIG. 1 is a system architecture diagram of a preferred embodiment of a computer operating state detection and processing system of the present invention. The system includes a host 10 and an operating system 20. The host 10 is configured to perform operations. System 20, which includes a super input/output (Super I/O) wafer 100, a programmable logic device (CPLD) 110, a south bridge wafer 120, and an oscillator 130. 20 includes a device driver 200 that controls the Super I/O chip 100. The Super I/O chip 100 passes through three general purpose input/output (GPIO) interfaces GPI〇#l, GPIO. #2, GPIO#3 realizes connection and communication with the CPLD chip 110. In the present embodiment, GI>IO#1, GHO#2, and GFIO#3 are respectively configured as output, input, and output functions. Three input/output (I/O) interfaces connected to GPI〇#l, GPIO#2, and GPIO#3, i/q#i, I/〇#2, I/〇#3, and Super Connection and communication of the I/O chip 100, in this embodiment, I/0#l, I/0#2, and I/0#3 are respectively configured as round-in, output, and input functions. The south bridge wafer 120 is implemented with a CPLD wafer 110 through a "RESET" pin (not shown). Connection and communication. The "RESET," pin 8 200841170 can be used to restart the host ίο. In addition, the CPLD chip 11 〇 further includes a judging module i n, a transmitting module 112. The judging module 111 is used to pass the super I / O chip 1 The communication status of the CPLD chip 110 determines whether the computer host 1 is operating normally; the transmitting module 112 is configured to send a restart signal to the south bridge wafer 120 to restart the host 1 when an abnormality occurs in the operation of the host 1. The mode referred to in the present invention is A group is a computer program segment that performs a specific function. It is more suitable than a program to describe the execution of a software on a computer.

進一步地,CPLD晶片11〇還包括計時器ιη。 振蕩器130提供計時器113的工作頻率。 本電腦運行狀態偵測及處理系統工作原理介纟”如下· 設備驅動程式200控制Super 1/()晶片1〇〇 ^ :並=送 開始偵測信號、週期性信號至CPLD晶片11〇 •生、又达 CPLD晶片110接收Super I/O晶片1〇〇笋 測信號後觸發計時器113開始從零計時、的開始債 、ϋ),判斷模组. 111判斷CPLD晶片110在預設計時周期内 4呵供、、 V χπ t=in nprindFurther, the CPLD wafer 11A further includes a timer ιη. Oscillator 130 provides the operating frequency of timer 113. The working principle of the computer running state detection and processing system is as follows: The device driver 200 controls the Super 1/() chip 1 〇〇 ^ : and = sends the start detection signal, periodic signal to the CPLD chip 11 〇 • raw And after the CPLD chip 110 receives the Super I/O chip, the trigger timer 113 starts to start from the zero timing, and the determination module 111 determines that the CPLD wafer 110 is within the preset timing period. 4 供, , V χπ t=in nprind

是否收到Super I/O晶片100發出的週 PWhether to receive the week issued by Super I/O chip 100 P

π I王竣•,若C 晶片110在預設計時周期内收到該週期 系統20運行正常,則發送模組112 — Q 』衣月作某 丄义句Super 1/〇曰 發送回復資訊、計時器U3重新從零_ :日片: 晶片110未在預料時周期内收__ ’右CPLD 業系統20出現異常,則發送模紕112發送重二说則表明作 晶片120,南橋晶片120重新啓動主啓1§號至南橋 如圖2所示’係本發明電腦運行狀態偵測及處理方法 9 200841170 較佳實施例的流程圖。首先,主機10上電,作業系統如 :啓動,設備驅動程式200控制SuperI/0晶片1〇〇産/生'一個 •狀態偵測開始信號s,並發送該狀態偵測開始信號s至 CPLD^Ji 110(#^S10)〇CPLD^^ 110 #^ sJper I/〇 晶片100發送的狀態偵測開始信號s (步驟S2〇)。計時器 113開始rfk t=0 (步驟S3〇)。判斷模組出判斷cpLD 晶片110是否收到SuperI/0晶片1〇〇週期性發送的信號p 鲁(以下稱作“週期性信號P”)(步驟S40)。若收到週期 性4§號P’則發送模組112發送回復信號A至Su{)er 晶 片100 (步驟S50),流程返回步驟S2〇。若未收到週期性 信號P,則判斷模組111判斷計時器113計時是否超過預 設時間,如m (m>〇)個信號p的周期(步驟S50)。若未 超過預設時間,則流程返回步驟S40,若超過預設時間, 則發送模組112發送重啓信號r至南橋晶片12〇 (S6〇)。 南橋晶片120重新啓動主機1〇以重新導入作業系統2〇^步 • 驟 S70)。 如圖3所示,係主機10運行正常時的信號示意圖。 當主機10運行正常,亦即作業系統2〇正常工作時,設備 驅動程式200控制Super I/O晶片1〇〇産生一個狀態偵測開 始信號S,並控制Super I/O晶片1⑽産生週期性信號p。 CPLD晶片110每次收到SuperI/0發送的信號p即回復一 個信號A,當主機1〇運行正常時,信號a亦爲一個週期 性信號,僅相對於信號P在時間上有一個延遲。南橋晶片 120的“RESET”接腳一直處於高電位。 200841170 圖。=機4 主機10運行發生異常時的信號示意 :掬:n運仃過程中出現異常,亦即作業系統20 * 式細無法正常驅動S—晶片 設時二期性信號P。當CPLD晶片110超過預 晶片110f、、^號P的周期)未收到信號p時,CPLD m的重啓信號只至南橋晶片120。南橋晶片 新戍動。 接腳由兩電位跳變到低電位,主機10重 X上所述僅為本發明之較佳實施例而已,且已達廣泛 之使用功效,凡其他未脫離本發明所揭示之精神下所完成 之均等變化或修飾,均應包含在下述之申請專利範圍内。 【圖式簡單說明】 圖1係本發明電腦運行狀態偵測及處理系統較佳實施 例的系統架構圖。 也 圖2係本發明電腦運行狀態偵測及處理方法較佳實施 例的流程圖。 圖3係電腦正常運行時的信號示意圖。 圖4係電腦運行發生異常時的信號示意圖。 要元件符號說明】 主機 10 Super I/O 晶片 100 可編程邏輯元件 110 判斷模組 111 發送模組 112 11 200841170 計時器 113 南橋晶片 120 振蕩器 130 作業系統 20 設備驅動程式 200π I 王竣•, if the C chip 110 receives the cycle system 20 in the preset timing period, the transmission module 112 — Q 』 衣 作 丄 Super Super Super 1 / 〇曰 send reply information, timing U3 re-from zero_: day: wafer 110 is not received within the expected time period __ 'The right CPLD industry system 20 is abnormal, then the transmission module 112 sends a second to indicate that the wafer 120, the south bridge wafer 120 restarts The main opening 1 § to the south bridge is shown in FIG. 2 ' is a flowchart of a preferred embodiment of the computer operating state detection and processing method 9 200841170. First, the host 10 is powered on, and the operating system is activated, for example, the device driver 200 controls the SuperI/0 chip 1 to generate a raw state detection start signal s, and sends the state detection start signal s to the CPLD^ Ji 110 (#^S10) 〇 CPLD^^ 110 #^ sJper I/〇 The state detection start signal s transmitted from the wafer 100 (step S2 〇). The timer 113 starts rfk t = 0 (step S3 〇). The judging module judges whether or not the cpLD wafer 110 has received the signal p Lu (hereinafter referred to as "periodic signal P") periodically transmitted by the SuperI/0 chip 1 (step S40). If the periodicity 4 § P' is received, the transmitting module 112 transmits the reply signal A to the Su{)er wafer 100 (step S50), and the flow returns to step S2. If the periodic signal P is not received, the judging module 111 judges whether or not the timer 113 counts more than the preset time, e.g., the period of m (m > 〇) signals p (step S50). If the preset time has not passed, the flow returns to step S40. If the preset time is exceeded, the transmitting module 112 sends a restart signal r to the south bridge wafer 12 (S6〇). The south bridge wafer 120 restarts the host 1 to re-import the operating system 2 steps (step S70). As shown in FIG. 3, it is a signal diagram when the host 10 is operating normally. When the host 10 is operating normally, that is, the operating system 2 is operating normally, the device driver 200 controls the Super I/O chip 1 to generate a state detection start signal S, and controls the Super I/O chip 1 (10) to generate a periodic signal. p. Each time the CPLD chip 110 receives the signal p sent by the SuperI/0, it replies with a signal A. When the host 1 is operating normally, the signal a is also a periodic signal, and there is only a delay in time with respect to the signal P. The "RESET" pin of the South Bridge wafer 120 is always at a high potential. 200841170 Figure. = Machine 4 When the host 10 runs abnormally, the signal is indicated: 掬: An abnormality occurs during the operation of the n, that is, the operating system 20* can't normally drive the S-chip to set the second-stage signal P. When the signal p is not received when the CPLD wafer 110 exceeds the period of the pre-wafer 110f, the number P, the restart signal of the CPLD m is only to the south bridge wafer 120. South Bridge wafers are new. The pin jumps from two potentials to a low potential, which is only a preferred embodiment of the present invention, and has been used for a wide range of functions, and others have been completed without departing from the spirit of the present invention. Equivalent changes or modifications are intended to be included in the scope of the claims below. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a system architecture diagram of a preferred embodiment of a computer operating state detection and processing system of the present invention. Figure 2 is a flow chart showing a preferred embodiment of the method for detecting and processing computer operating conditions of the present invention. Figure 3 is a schematic diagram of the signal when the computer is in normal operation. Figure 4 is a schematic diagram of the signal when the computer is running abnormally. Element Symbol Description Host 10 Super I/O Chip 100 Programmable Logic Element 110 Judgment Module 111 Transmitter Module 112 11 200841170 Timer 113 South Bridge Chip 120 Oscillator 130 Operating System 20 Device Driver 200

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Claims (1)

200841170 十、申請專利範圍: 1. 一種電腦運行狀態偵測及處理系統,用於偵測電腦 是否處於正常運行狀態,並當電腦運行發生異常 時,自動重啓電腦,所述電腦包括超級輸入輸出晶 片、可編程邏輯元件及南橋晶片:200841170 X. Patent application scope: 1. A computer running state detection and processing system for detecting whether a computer is in a normal running state, and automatically restarting the computer when an abnormality occurs in the computer operation, the computer including super input and output Wafers, Programmable Logic Components, and South Bridge Wafers: 所述電腦還包括設備驅動程式,用於控制所述超級 輸入輸出晶片産生並發送一個狀態偵測開始信號至 可編程邏輯元件,並用於控制所述超級輸入輸出晶 片産生並發送週期性信號至可編程邏輯元件; 所述的可編程邏輯元件用於接收超級輸入輸出晶片 發送的狀態偵測開始信號,並用於當超過預設時間 且未收到超級輸入輸出晶片發送的週期性信號時, 發送一個重啓信號至南橋晶片;及 所述的南橋晶片用於在收到可編程邏輯元件發送的 重啓信號後,重新啓動電腦。 2.如申請專利範圍第1項所述的電腦運行狀態偵測及 處理系統,其中所述的超級輸入輸出晶片是透過通 用輸入輸出介面與所述可編程邏輯元件連接並通 信。 3.如申請專利範圍第1項所述的電腦運行狀態偵測及 處理系統,其中所述的可編程邏輯元件還包括一個 計時器,用於在收到超級輸入輸出晶片發送的偵測 開始信號時開始計時,並用於判斷是否在預設時間 内收到所述週期性信號。 13 200841170 4. 如申請專利範圍第3項所述的電腦運行狀態偵測及 處理系統,其中所述的可編程邏輯元件還用於當在 預設時間内收到超級輸入輸出晶片發送的週期性信 號時,發送回復信號至超級輸入輸出晶片,並將計 時器歸零重新開始計時。The computer further includes a device driver for controlling the super input and output chip to generate and send a state detection start signal to the programmable logic component, and for controlling the super input and output wafer to generate and send a periodic signal to the Programming a logic component; the programmable logic component is configured to receive a state detection start signal sent by the super input/output chip, and to send a periodic signal when the preset time is exceeded and the super input/output wafer is not received. The restart signal is sent to the south bridge chip; and the south bridge chip is used to restart the computer after receiving the restart signal sent by the programmable logic element. 2. The computer operating state detection and processing system of claim 1, wherein the super input/output chip is connected to and communicated with the programmable logic element through a universal input/output interface. 3. The computer operating state detection and processing system of claim 1, wherein the programmable logic component further comprises a timer for receiving a detection start signal sent by the super input/output chip. The timing starts and is used to determine whether the periodic signal is received within a preset time. The computer operating state detection and processing system of claim 3, wherein the programmable logic component is further configured to receive the periodicity of the super input and output wafer transmission when the preset time is received. When the signal is sent, the reply signal is sent to the super input and output chip, and the timer is reset to zero to restart the timing. 5. —種電腦運行狀態偵測及處理方法,用於偵測電腦 是否處於正常運行狀態,該電腦包括超級輸入輸出 晶片、可編程邏輯元件及南橋晶片’該方法包括以 下步驟: 電腦的設備驅動程式控制所述超級輸入輸出晶片産 生並發送一個狀態偵測開始信號至可編程邏輯元 件; 可編程邏輯元件接收所述超級輸入輸出晶片發送的 偵測開始信號; 可編程邏輯元件的計時器開始計時; 判斷可編程邏輯元件是否收到超級輸入輸出晶片發 送的週期性信號; 若未收到所述週期性信號,則判斷計時器計時是否 超過預設時間; 若計時器計時超過預設時間,則發送重啓信號至南 橋晶片;及 南橋晶片重啓電腦。 6. 如申請專利範圍第5項所述的電腦運行狀態偵測及 處理方法還包括以下步驟: 200841170 若計時器計時未超過預設時間且可編程邏輯元件收 到所述週期性信號,則發送回復資訊至超級輸入輸 出晶片;及 返回計時器計時的步驟重新開始計時。 7.如申請專利範圍第5項所述的電腦運行狀態偵測及 處理方法還包括以下步驟: 若計時器計時未超過預設時間且可編程邏輯元件未 收到所述週期性信號,則返回判斷是否收到所述週 期性信號的步驟。5. A computer running state detection and processing method for detecting whether a computer is in a normal running state, the computer comprises a super input/output chip, a programmable logic component and a south bridge chip. The method comprises the following steps: a computer device driver The program controls the super input and output chip to generate and send a state detection start signal to the programmable logic component; the programmable logic component receives the detection start signal sent by the super input and output chip; the timer of the programmable logic component starts timing Determining whether the programmable logic component receives the periodic signal sent by the super input/output chip; if the periodic signal is not received, determining whether the timer count exceeds the preset time; if the timer counts exceed the preset time, Send a restart signal to the South Bridge chip; and the South Bridge chip restarts the computer. 6. The method for detecting and processing a computer operating state according to claim 5, further comprising the following steps: 200841170 sending a timer if the timer does not exceed a preset time and the programmable logic component receives the periodic signal Reply to the super input and output chip; and return to the timer to restart the timing. 7. The method for detecting and processing a computer operating state according to claim 5, further comprising the steps of: returning if the timer does not exceed a preset time and the programmable logic element does not receive the periodic signal; A step of determining whether the periodic signal is received. 1515
TW96111594A 2007-04-02 2007-04-02 Method and system for monitoring and processing running status of a computer TWI390398B (en)

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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110502377A (en) * 2019-08-08 2019-11-26 苏州浪潮智能科技有限公司 It is a kind of that test method is restarted based on CPLD

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN110502377A (en) * 2019-08-08 2019-11-26 苏州浪潮智能科技有限公司 It is a kind of that test method is restarted based on CPLD

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