JP2004348335A - Fault detection method and information processing system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a fault detection method that makes it possible to obtain fault information in reduced space at low cost to provide an information processing system of high reliability and to provide an information processing system. <P>SOLUTION: The information processing system has a bridge board with a bus switch circuit for connecting the universal buses of a plurality of information processors to one another. Should a fault occur in any of the information processors, an SMI interrupt indicating the occurrence of the fault is sent via the bridge board to each of the information processors. On receiving a signal indicating the occurrence of the fault, one of the information processors sends a bus switch signal for accessing the universal bus of the information processor where the fault occurred, and the bridge board connects the universal bus of the information processor which issued the SMI interrupt to the universal bus of the information processor which was selected as a fault diagnosis device by sending the bus switch signal. Following the program of a BIOS, the information processor selected as the fault diagnosis device collects fault information via the universal bus from the internal device of the information processor where the fault occurred. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a failure detection method for acquiring information on a fatal failure that has occurred in an information processing system including a plurality of information processing apparatuses and an information processing system.
[0002]
[Prior art]
Since a relatively large-scale information processing device called a general-purpose computer or a minicomputer is also used by a host computer of a computer network, etc., when a failure occurs, the content and location of the failure are detected and notified to the outside. The fault diagnosis function becomes very important.
[0003]
As a conventional information processing device that has a failure diagnosis function, it has a micro diagnostic device that operates independently of the main system that runs on the operating system, and can cause a fatal failure, for example, a failure between the CPU and memory. Patent Document 1 discloses a configuration in which when a fault occurs, the fault is detected and reported to the outside.
[0004]
Patent Documents 2 and 3 disclose configurations in which two processors that can operate independently are provided, and when a failure occurs in one processor, failure information is collected by the other processor and notified to the outside. Has been described.
[0005]
[Patent Document 1]
JP-A-5-265812
[Patent Document 2]
JP-A-4-329461
[Patent Document 3]
JP-A-3-014136
[0006]
[Problems to be solved by the invention]
Among the conventional information processing devices as described above, in the configuration including the micro diagnostic device described in Patent Document 1, a processing device including a CPU and a memory that operate independently of the main system is included in the information processing device. This necessitates a complicated device configuration and a large mounting area, and increases the cost and makes the device very expensive. Therefore, a relatively small information processing device such as a workstation server, an office computer, or a personal computer, which requires space saving and cost reduction, cannot often adopt a configuration including a micro diagnostic device.
[0007]
In a data processing device without a micro diagnostic device, if a catastrophic failure occurs, the CPU itself cannot operate, or the CPU cannot transmit an instruction to a memory or a PCI / LPC (ISA) bus. As a result, the operation of the operating system stops. Further, such an information processing apparatus cannot execute an event log for saving the contents of a memory or a register in the process of processing or for recording minimum failure information.
[0008]
On the other hand, the configuration described in Patent Literatures 2 and 3 in which two processors obtain fault information from each other can obtain fault information with a small increase in the amount of hardware. It can be applied to a processing device.
[0009]
However, the configurations described in Patent Literatures 2 and 3 have a problem of poor versatility because it is necessary to provide a circuit for monitoring the states of the processors with each other and a dedicated bus for transferring fault information. . Therefore, for example, when the present invention is applied to a configuration in which the processing capability of the entire server is improved by adding a blade having an information processing device function like a recent blade server, the circuit configuration in each blade is increased each time the blade server is added. And the software must be changed, which increases the time and effort required for the change.
[0010]
SUMMARY OF THE INVENTION The present invention has been made to solve the problems of the conventional technology as described above, and it is possible to obtain fault information in a space-saving and low-cost configuration to obtain a highly reliable information processing system. It is an object of the present invention to provide a fault detection method and an information processing system which are used.
[0011]
[Means for Solving the Problems]
In order to achieve the above object, a failure detection method according to the present invention includes a plurality of information processing apparatuses including a general-purpose bus for collecting respective apparatus information from internal devices,
A bridge board including a bus switching circuit for connecting the general-purpose buses of any two information processing devices among the plurality of information processing devices;
A failure detection method for collecting information on a fatal failure that has occurred in an information processing system having
When a failure occurs in the information processing device, the information processing device sends an interrupt indicating the occurrence of the failure to the bridge board,
When the bridge board receives the interrupt, each of the information processing devices except the information processing device that issued the interrupt sends a fault notification signal indicating the occurrence of a fault,
The information processing device that has received the fault notification signal indicating the occurrence of the fault from the bridge board accesses the general-purpose bus of the faulty information processing device if the fault notification signal is not cleared after a predetermined time has elapsed. Bus switch signal to the bridge board,
The bridge board connects the general-purpose bus of the information processing device selected as the failure diagnosis device by transmitting the bus switching signal and the general-purpose bus of the information processing device that has issued the interrupt,
The information processing apparatus selected as the failure diagnosis apparatus is a method of collecting failure information from internal devices of the information processing apparatus in which the failure has occurred via the general-purpose bus according to a BIOS program.
[0012]
On the other hand, the information processing system of the present invention includes a general-purpose bus for collecting device information from internal devices, and when a failure occurs, sends an interrupt indicating the occurrence of the failure to the outside, and detects the occurrence of the failure from outside. If the failure notification signal is not cleared after a predetermined period of time upon receipt of the failure notification signal shown, a bus switching signal for accessing the general-purpose bus of the device in which the failure has occurred is sent out to the outside, and the program of the BIOS is transmitted to the outside. Therefore, a plurality of information processing devices for collecting fault information from the internal device of the device via the general-purpose bus, respectively,
The information processing apparatus further includes a bus switching circuit for connecting the general-purpose buses of any two of the information processing apparatuses, and when the interrupt is received, all of the information processing apparatuses except the information processing apparatus that has issued the interrupt are provided. The general-purpose bus of the information processing device selected as the fault diagnosis device by transmitting the failure notification signal to the information processing device and transmitting the bus switching signal to the general-purpose bus of the information processing device that has issued the interrupt. A bridge board to connect
It is a structure which has.
[0013]
In the above failure detection method and information processing system, a bridge board that receives an interrupt indicating the occurrence of a failure sends a failure notification signal indicating the occurrence of a failure to all information processing apparatuses except the information processing apparatus that issued the interrupt. Each of the information processing devices which has transmitted the fault notification signal indicating the occurrence of the fault from the bridge board, accesses the general-purpose bus of the faulty information processing device if the fault notification signal is not cleared after a predetermined time has elapsed. To the bridge board, and connect the general-purpose bus of the information processing device that issued the interrupt with the bridge board to the general-purpose bus of the information processing device selected as the fault diagnosis device, and select the fault diagnosis device. From the internal device of the information processing device that failed according to the BIOS program Respectively via the use bus by collecting fault information, without using an expensive micro diagnostic apparatus, economic (space, cost) it is possible to acquire the fault information.
[0014]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, the present invention will be described with reference to the drawings.
[0015]
According to the present invention, by connecting a plurality of information processing devices using a bridge board including a general-purpose bus (for example, an I2C bus), information of a failure occurring in an arbitrary information processing device can be transmitted to another information processing device. Make it collectable. The I2C bus is a bus provided in the information processing device in advance to collect various device information (including fault information) from each internal device in the information processing device. However, when a catastrophic failure occurs in the CPU, the main bus, or the like, the operating system does not operate, so that such failure information cannot be collected. In the present invention, another information processing apparatus accesses the I2C bus of the information processing apparatus in which a catastrophic failure has occurred, and an internal device connected to the I2C bus (hereinafter, also referred to as an I2C bus device) causes each failure. Gather information.
[0016]
For example, when a failure occurs in a device under a local bus, a system bus, a memory bus, or the like of an arbitrary information processing apparatus, an SMI (System Management Interrupt) which is a signal indicating the occurrence of the failure from the information processing apparatus via a bridge board. ) An interrupt is notified to each information processing device. The bridge board connects between the I2C bus of the information processing device that first responded to the SMI interrupt and the I2C bus of the information processing device in which a failure has occurred. The information processing apparatus selected as the failure diagnosis apparatus that collects the failure information accesses the I2C bus of the information processing apparatus in which the failure has occurred, and refers to the system configuration information stored in its SROM (Serial Read Only Memory). In accordance with the BIOS program, failure information is acquired from each I2C bus device of the information processing apparatus in which the failure has occurred. By performing such processing, fault information can be economically (space-saving, low-cost) collected without using an expensive micro diagnostic device, and a highly reliable information processing system can be constructed. .
[0017]
(First Embodiment)
FIG. 1 is a block diagram showing the configuration of the first embodiment of the information processing system of the present invention, and FIG. 2 is a block diagram showing the configuration of the bridge board shown in FIG. FIG. 3 is a schematic diagram showing a state of a bus switching operation by the information processing system shown in FIG.
[0018]
The information processing system according to the first embodiment includes two processor boards 1 each having a function as an information processing apparatus. ₁ , 1 ₂ Are connected by the bridge board 2.
[0019]
As shown in FIG. ₁ , 1 ₂ Are a CPU 11, a main memory 14, a local bus connected to the CPU 11, and a north bridge 12 for controlling information communication of a memory bus connected to the main memory 14, a system bus connected to the north bridge 12, and a PCI bus connected to the PCI device 15. And a south bridge 13 for controlling information communication of an LPC / ISA bus to which an LPC / ISA device such as a BIOS ROM 16 or a Super I / O 17 is connected, a connector 20 for connecting to the bridge board 2, and an I2C bus. And an SROM 19, which is a non-volatile memory storing accessible device configuration information, and a sensor 18 connected to an I2C bus for monitoring device status such as temperature and power supply voltage.
[0020]
The local bus is a bus for communicating between the CPU 11 and the north bridge 12, and when a fatal failure occurs in the local bus, the processor board 1 ₁ , 1 ₂ Operation freezes (stops).
[0021]
The memory bus is a bus for communicating between a memory controller (not shown) in the north bridge 12 and the main memory 14. If an uncorrectable fault occurs in the memory bus, the processor board 1 ₁ , 1 ₂ Operation may stop.
[0022]
The system bus is a bus for communicating between the north bridge 12 and the south bridge 13. Processor board 1 even if a catastrophic failure occurs in the system bus ₁ , 1 ₂ Operation stops.
[0023]
The CPU 11 includes a CPU error notification circuit 112 for notifying an error of a process by the CPU 11 to the outside, and an SMI receiving circuit (SMI) 111 for receiving an SMI interrupt issued by the south bridge 13. When a system management interrupt (System Management Interrupt) is received, it operates in an SMM (System Management Mode).
[0024]
The main memory 14 is a storage device for storing programs and data necessary for the processing of the CPU 11, and includes a memory error notification circuit (SPD) 141 for notifying a failure that has occurred during memory access to the outside.
[0025]
The north bridge 12 controls information communication of a local bus and a memory bus, and also has a function as a system controller and a memory controller. Further, it has a north bridge error notification circuit (NB Error) 121 for detecting a fault that has occurred on the local bus and the memory bus and notifying the CPU 11 of the fault detection result.
[0026]
The south bridge 13 includes an SMI issuing circuit 131 that issues an SMI interrupt, an error factor registration circuit (Error registration circuit) 132 that stores failure occurrence information, and a timer that is used to determine whether the failure has been recovered. A circuit (Timer) 133, a south bridge error notifying circuit (SM Error) 134 for detecting a fault occurring on the PCI bus and the LPC / ISA bus, and a GPIO circuit 135 for sending a bus switching signal to the bridge board 2. , An I2C bus master 136 for controlling the communication of the I2C bus.
[0027]
A PCI device 15 having a PCI bus architecture is connected to the PCI bus. The LPC / ISA bus includes, for example, an LPC / ISA device having an LPC / ISA bus architecture such as a Super I / O 17 for controlling a power supply sequence and the like and a BIOS ROM 16 which is a ROM storing a system BIOS code. Connected.
[0028]
The CPU 11 can execute the code of the SMI handler used at the time of SMM by copying the ROM code stored in the BIOS ROM 16 to the main memory 14. In the present embodiment, as shown in FIG. ₁ , 1 ₂ The CPU error notification circuit 112, the memory error notification circuit 141, the north bridge error notification circuit 121, the south bridge error notification circuit 134, the PCI device 15, the Super I / O 17, the sensor 18, and the SROM 19 are connected to the I2C bus, respectively. A program for collecting fault information is stored in the ROM. The CPU 11 executes processing according to a program (SMI handler) in the BIOS ROM to acquire necessary failure information from each device of the failed processor board via the I2C bus.
[0029]
As shown in FIG. 2, the bridge board 2 is a processor board 1 ₁ , 1 ₂ Connector 21 for connecting to ₁ , 21 ₂ A bus switching circuit 22 for switching the connection of the I2C bus, and a processor board 1 ₁ , 1 ₂ AND circuit 23 that generates a failure notification signal (SMI IN signal) indicating that a failure has occurred for each time ₁ , 23 ₂ This is a configuration having:
[0030]
The bridge board 2 has a processor board 1 ₁ , 1 ₂ An SMI OUT signal (= SMI interrupt) indicating that a fault has occurred and a Presence signal, which is a level signal indicating that a processor board is connected, are output to each processor board 1. ₁ , 1 ₂ Respectively.
[0031]
The SMI OUT signal and the Presense signal are output from the AND circuit 23. ₁ , 23 ₂ , And the SMI IN signal, which is the result of their logical product, is transmitted to all processor boards except the own board. By using the logical product of the SMI OUT signal and the Presence signal in this way, it is possible to prevent erroneous detection of a failure due to the processor board not being connected.
[0032]
The bus switching circuit 22 is connected to each processor board 1 ₁ , 1 ₂ Is a circuit that relays between the I2C bus master 136 and the I2C bus to which each device is connected. When no failure occurs (or when failure recovery is possible), each processor board 1 ₁ , 1 ₂ Is set as a path (path {circle around (1)} in FIG. 3) for returning the I2C bus from the board to its own board. If recovery is impossible due to a catastrophic failure, the path (path {circle around (2)} in FIG. 3) connecting the I2C bus of the failed processor board and the I2C bus of the processor board serving as the failure diagnosis device is connected. Set.
[0033]
In FIG. 1, the CPU error notification circuit 112, the memory error notification circuit 141, the north bridge error notification circuit 121, the south bridge error notification circuit 134, the PCI device 15, the Super I / O 17, and the sensor 18 are provided to the I2C bus master 136. , SROM 19, and connector 20 are directly connected to each other. However, an actual I2C bus to which each I2C bus device is connected is connected via a bridge board 2 ((1) or (1) in FIG. 2). 2) The path is connected to the I2C bus master 136. In such a configuration, the I2C bus master of the processor board serving as the failure diagnostic device is connected to the I2C bus device of the failed processor board while the I2C bus master 136 of the failed processor board is completely disconnected. Can be.
[0034]
The I2C bus of the failed processor board and the I2C bus master 136 of the processor board serving as the failure diagnosis device are continuously connected while the bus switching signal is asserted. In the present embodiment, the two processor boards 1 ₁ , 1 ₂ When connecting between the I2C buses, since one processor board always stops operating due to a fatal failure, exclusive processing of the bus switching signal is unnecessary.
[0035]
Next, the operation of the information processing system according to the first embodiment will be described.
[0036]
In the configuration shown in FIG. ₁ It is assumed that a fatal failure has occurred in the CPU 11, local bus, system bus, and memory bus.
[0037]
At this time, an error cause in the south bridge 13 from the CPU error notifying circuit (CPU Error) 112, the north bridge error notifying circuit (NB Error) 121, and the south bridge error notifying circuit (SM Error) 134 that is monitoring the failure. An alert signal indicating the occurrence of a fault is stored in a registration circuit (Error registration circuit) 132.
[0038]
When the Alert signal is stored in the error factor registration circuit 132, an SMI interrupt is issued from the SMI issuing circuit 131 of the south bridge 13 to the SMI receiving circuit (SMI) 111 of the CPU 11.
[0039]
The SMI interrupt is sent to the processor board 1 where the system failure has occurred. ₁ Not only the CPU 11 but also the SMI OUT signal, which is input to the bridge board 2 and the SMI IN signal ₂ Will also be notified. The SMI IN signal is sent to the processor board 1 as a fault notification for each processor board. ₂ Is stored in the error factor registration circuit 132. It should be noted that the failure notification due to the SMI interrupt is sent as a level signal, and the processor board 1 ₁ When all of the faults that have occurred in the above are recovered within a predetermined time, they are automatically cleared.
[0040]
If the failure is not fatal, the processor board 1 ₁ CPU 11 starts the SMM and collects failure information from each I2C bus device in the own board via the I2C bus according to the SMI handler provided by the system BIOS.
[0041]
On the other hand, if the failure is fatal, the processor board 1 ₁ CPU 11 cannot start SMM, and as a result, cannot collect its own error information. In such a case, the processor board 1 connected via the bridge board 2 ₂ With processor board 1 ₁ Collect fault information.
[0042]
Processor board 1 ₂ Is the processor board 1 ₁ When the failure notification issued from is stored, first, it is checked whether or not the failure notification is cleared within a predetermined time by using a timer circuit 133 in the south bridge 13.
[0043]
Processor board 1 within a predetermined time ₁ If the failure notification is not cleared, a Timer interrupt (Timeout) occurs and the processor board 1 ₂ Via the SMI receiving circuit 111. Processor board 1 ₂ CPU 11 starts the SMM, controls the GPIO circuit 135 in accordance with the SMI handler provided by the system BIOS, asserts a Timeout factor, and sends out a bus switching signal.
[0044]
The bus switching signal is input to the bus switching circuit 22 of the bridge board 2. The bus switching circuit 22 that has received the bus switching signal normally switches the I2C bus connected to the path indicated by (1) in FIG. 3 to the path indicated by (2) in FIG. Thereby, the processor board 1 ₂ I2C bus master 136 and processor board 1 ₁ Connected to each I2C bus device, and the processor board 1 ₂ I2C bus master 136 to processor board 1 ₁ Can access each I2C bus device.
[0045]
Processor board 1 ₂ CPU 11 controls its own I2C bus master 136 according to the SMI handler provided by the system BIOS, and ₁ The failure information is acquired from each I2C bus device. If necessary, the failed processor board 1 ₁ Access to the Super I / O 17 of the processor board 1 ₁ Reset / DC OFF (reset operation for turning off and on the power). Also, processor board 1 ₂ Board 1 collected using the notification function (LAN / COM) ₁ Notify the trouble information to the outside. After that, it controls the GPIO circuit 135 to deassert the bus switching signal.
[0046]
Upon detecting the deassertion of the bus switching signal, the bus switching circuit 22 switches the I2C bus to the path indicated by (1) in FIG. ₂ The I2C bus master 136 and each I2C bus device are connected again.
[0047]
(Second embodiment)
FIG. 4 is a block diagram showing the configuration of the second embodiment of the information processing system of the present invention.
[0048]
The information processing system according to the second embodiment has a configuration in which three or more processor boards having a function as an information processing device are connected by a bridge board 3.
[0049]
As shown in FIG. 4, the bridge board 3 of the present embodiment has a connector 31 for connecting to three processor boards. ₁ , 31 ₂ , 31 ₃ A bus switching circuit 32 for switching the connection of the I2C bus, and an AND circuit 33 for generating a signal (SMI IN signal) indicating that a failure has occurred for each processor board ₁ , 33 ₂ , 33 ₃ This is a configuration having: Although FIG. 4 shows an example in which three processor boards are connected to a bridge board, an I2C bus from each processor board is connected to the bus switching circuit 32 in the same manner as in FIG. By providing the connector 31 and the AND circuit 33 respectively, it is possible to cope with a configuration in which four or more processor boards are connected.
[0050]
As in the first embodiment, the bridge board 3 has an SMI OUT signal (= SMI interrupt) indicating that a failure has occurred in the processor board and a Presence which is a level signal indicating that the processor board is connected. A signal is input from each processor board. The SMI OUT signal and the Presense signal are output from the AND circuit 33. ₁ ~ 33 ₃ , And the SMI IN signal as a result of the logical product thereof is sent out to all processor boards except the own board via the bus switching circuit 32.
[0051]
As in the first embodiment, the bus switching circuit 32 sets the I2C buses from the processor boards in which a failure has not occurred (or the failure can be recovered) to paths for returning the I2C buses to their own boards. In addition, an I2C bus from a processor board that cannot be recovered due to a catastrophic failure is set as a path connected to the I2C bus of the processor board serving as a failure diagnosis device.
[0052]
When the bus switching circuit 32 of the present embodiment sends the SMI IN signal to each processor board, the bus switching circuit 32 of the plurality of information processing apparatuses, the processor board that first returned the bus switching signal in response to the SMI IN signal is connected to the failure diagnosis device. And connects the I2C bus of the processor board to the I2C bus of the processor board that sent the SMI OUT signal. In this case, the bus switching circuit 32 executes an exclusion process for invalidating the reception of a bus switching signal issued from another processor board after the completion of the path switching of the I2C bus. Such exclusive processing may be realized by, for example, a logic circuit combining various logic gates.
[0053]
Note that the bus switching circuit may select a predetermined processor board as a failure diagnosis device for a processor board in which a failure has occurred. In this case, since the switching path of the I2C bus is limited, the configuration of the bus switching circuit can be expected to be simplified. However, in such a configuration, if a failure occurs in the selected processor board, failure information may not be collected even though there is another normal processor board. Therefore, it is preferable to select the processor board that first returns the bus switching signal in response to the SMI IN signal as the failure diagnosis apparatus as in the present embodiment.
[0054]
The configuration and operation of the processor board, and the operation of collecting fault information from the processor board in which a fault has occurred after the I2C bus switching is the same as in the first embodiment, and a description thereof will be omitted.
[0055]
Therefore, according to the present invention, even if a catastrophic failure occurs and an operation becomes inoperable in an information processing system including a plurality of information processing apparatuses, economical operation is possible without using an expensive micro diagnostic device. Fault information can be acquired in a space-saving and low-cost manner, and a reset operation of the power supply and fault information can be notified to the outside based on the information. Therefore, a highly reliable information processing system can be constructed at low cost.
[0056]
In particular, according to the present invention, it is necessary to create new software for fault detection because a BIOS program always provided on the processor board is used and fault information of internal devices is collected via a general-purpose bus originally provided on the processor board. Absent. Further, if the bridge board of the present invention is provided in advance, even if an additional processor board is added, it is possible to cope with a slight change, so that an information processing system with high processing capability and high reliability is increased in cost. Can be obtained without inviting.
[0057]
【The invention's effect】
Since the present invention is configured as described above, the following effects can be obtained.
[0058]
The bridge board that received the interrupt indicating the occurrence of the fault sends a fault notification signal indicating the occurrence of the fault to all information processing apparatuses except the information processing apparatus that issued the interrupt, and the fault indicating the occurrence of the fault from the bridge board. The information processing device that has received the notification signal sends a bus switching signal to the bridge board for accessing the general-purpose bus of the information processing device in which the failure has occurred, if the failure notification signal is not cleared after a predetermined time has elapsed, The general-purpose bus of the information processing device that issued the interrupt on the bridge board is connected to the general-purpose bus of the information processing device selected as the failure diagnosis device, and the information processing device selected as the failure diagnosis device causes a failure according to the BIOS program. By collecting fault information from the internal device of the information processing device where the error occurred via the general-purpose bus, Without using a valence micro diagnostic apparatus, economic (space, cost) it is possible to acquire the fault information. Therefore, it is possible to notify the power reset operation and the failure information to the outside based on the failure information, and it is possible to construct a highly reliable information processing system at low cost.
[Brief description of the drawings]
FIG. 1 is a block diagram illustrating a configuration of a first embodiment of an information processing system according to the present invention.
FIG. 2 is a block diagram illustrating a configuration of a bridge board illustrated in FIG. 1;
FIG. 3 is a schematic diagram showing a state of a bus switching operation by the information processing system shown in FIG. 1;
FIG. 4 is a block diagram showing a configuration of a second embodiment of the information processing system of the present invention.
[Explanation of symbols]
1 ₁ , 1 ₂ Processor board
2 Bridge board
11 CPU
12 North Bridge
13 South Bridge
14 Main memory
15 PCI bus
16 BIOS ROM
17 Super I / O
18 Sensor
19 SROM
20, 21 ₁ , 21 ₂ , 31 ₁ ~ 31 ₃ connector
22, 32 bus switching circuit
23 ₁ , 23 ₂ , 33 ₁ ~ 33 ₃ AND circuit
111 SMI receiving circuit
112 CPU error notification circuit
121 North Bridge Error Notification Circuit
131 SMI issuing circuit
132 Error cause registration circuit
133 Timer circuit
134 South Bridge Error Notification Circuit
135 GPIO circuit
136 I2C bus master
141 Memory error notification circuit

Claims (6)

A plurality of information processing apparatuses having a general-purpose bus for collecting respective apparatus information from internal devices,
A bridge board including a bus switching circuit for connecting the general-purpose buses of any two information processing devices among the plurality of information processing devices;
A failure detection method for collecting information on a fatal failure that has occurred in an information processing system having
When a failure occurs in the information processing device, the information processing device sends an interrupt indicating the occurrence of the failure to the bridge board,
When the bridge board receives the interrupt, each of the information processing devices except the information processing device that issued the interrupt sends a fault notification signal indicating the occurrence of a fault,
The information processing device that has received the fault notification signal indicating the occurrence of the fault from the bridge board accesses the general-purpose bus of the faulty information processing device if the fault notification signal is not cleared after a predetermined time has elapsed. Bus switch signal to the bridge board,
The bridge board connects the general-purpose bus of the information processing device selected as the failure diagnosis device by transmitting the bus switching signal and the general-purpose bus of the information processing device that has issued the interrupt,
A failure detection method in which the information processing devices selected as the failure diagnosis devices collect failure information from internal devices of the failed information processing device via the general-purpose bus according to a BIOS program. The bridge board, when transmitting the failure notification signal, among the plurality of information processing devices, the general-purpose bus of the information processing device that first returned the bus switching signal and the general-purpose bus of the information processing device that issued the interrupt. 2. The failure detection method according to claim 1, wherein the failure detection method is connected to a bus to invalidate reception of a bus switching signal issued from another information processing device. Each of the information processing devices sends a Presence signal for determining whether or not the information processing device is connected to the bridge board,
The failure detection method according to claim 1, wherein the bridge board sends a logical product of the interrupt and the Presence signal as the failure notification signal. A general-purpose bus for collecting device information from internal devices is provided. When a fault occurs, an interrupt indicating the occurrence of the fault is sent to the outside, and when a fault notification signal indicating the occurrence of the fault is received from the outside, a predetermined time period If the failure notification signal is not cleared after the elapse, a bus switching signal for accessing the general-purpose bus of the failed device is sent to the outside, and the general-purpose bus is transmitted from an internal device of the device according to a BIOS program. A plurality of information processing devices each collecting failure information via
The information processing apparatus further includes a bus switching circuit for connecting the general-purpose buses of any two of the information processing apparatuses, and when the interrupt is received, all of the information processing apparatuses except the information processing apparatus that has issued the interrupt are provided. The general-purpose bus of the information processing device selected as the fault diagnosis device by transmitting the failure notification signal to the information processing device and transmitting the bus switching signal to the general-purpose bus of the information processing device that has issued the interrupt. A bridge board to connect
Information processing system having The bridge board,
When the failure notification signal is transmitted, among the plurality of information processing devices, the general-purpose bus of the information processing device that first returns the bus switching signal is connected to the general-purpose bus of the information processing device that has issued the interrupt. 5. The information processing system according to claim 4, wherein the reception of a bus switching signal issued from another information processing apparatus is invalidated. The information processing device,
Sending a Presence signal for determining whether or not the own device is connected to the bridge board;
The bridge board,
6. The information processing system according to claim 4, wherein a logical product of the interrupt and the Presence signal is transmitted as the failure notification signal.

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