JP2008176477A - Computer system - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a computer system enabling a computer system administrator to easily specify a defective portion when a hardware failure occurs due to an operation of the computer system not intended by a designer, such as a timeout failure. <P>SOLUTION: In the computer system, a chip set 110 as a circuit to manage data transfer between a processor 101 and a memory 107, and an expansion card 106 comprises a circuit 203 to record memory accesses issued by the processor 101 or the expansion card 106 or access history to the expansion card 106 in the chip set. The computer system is equipped with a means in which the recorded history information is sent to the computer system administrator together with a failure notice in case of failure or the computer system administrator read the information from the outside. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a computer system, and more particularly to a computer system provided with means for extracting information for failure analysis from the outside when a failure occurs in the computer.

  When a hardware failure is detected in an operating computer system, the computer system is required to identify the faulty part, isolate or switch, and continue the processing being executed without stopping the computer system. Further, when the computer system stops due to a hardware failure, the computer system is required to identify and replace the failed part, quickly restore the computer system, and restart the processing. Therefore, a computer system that guarantees high reliability and availability generally includes an error detection mechanism that can detect a hardware fault and identify a faulty part in each component of the computer system. Specifically, in the processor cache memory, system bus, main memory, etc., which is one of the components of the computer system, a parity bit or ECC (Error Collecting Code) is added to the data, and the data is configured in each component. A mechanism is provided for detecting illegal data in the form of a parity error or ECC error when read from an element. As a result, when a parity error or an ECC error is detected when data is read from each component such as a cache memory, the component in which the error has occurred can be specified as a failure part. Examples of an error detection mechanism that enables identification of a failure site other than a parity bit and ECC include a master abort detection mechanism and an error report mechanism by asserting a SERR signal in a transaction processing of a PCI bus. The master abort detection detects that the target device has not returned a response to the request from the PCI bus initiator. Therefore, when the master abort detection mechanism is used, it is possible to specify that the target device is a failure part. The assertion of the SERR signal indicates that a fatal failure has occurred in the PCI bus agent such as a bridge or a PCI device. Therefore, by asserting the SERR signal on the PCI bus, it can be estimated that the agent on the PCI bus is the fault site.

  However, when a hardware failure occurs in the computer system, the failure part may not be identified even if the error detection mechanism described above is provided. The error detection mechanism described above detects an error that can be predicted when a designer designs a calculation system. For this reason, errors such as parity errors and ECC errors described above are detected in the case of hardware failures that occur because the computer system performs an operation that is not intended by the designer, or because a failure cannot return a response. It is not possible to identify the site of failure. When such a hardware failure occurs, it becomes a timeout failure in a general computer system. The computer system is equipped with a mechanism to measure the hardware response time for any request. When there is no response to a request for a certain period of time, a timeout error is detected and a hardware failure is reported to the computer system administrator. To do.

  When a time-out failure occurs, the computer system administrator uses a commercially available digital signal observation device such as a logic analyzer to observe the digital signal on a bus on the computer system in order to estimate the failure location. Therefore, it is necessary to estimate the site of failure. Alternatively, if the computer system is equipped with a mechanism for collecting processor bus traces as in the techniques described in Patent Document 1 and Patent Document 2, it is possible to check the processor bus traces collected when a timeout failure occurs. Estimate the site.

JP-A-5-324396 JP-A-10-293702

  However, with the former means, it is necessary to first connect the observation apparatus to the computer system, then reproduce the time-out failure, collect a digital signal when the failure occurs, and specify the failure site based on the collected result. For this reason, the administrator of the computer system requires a great deal of time and labor for the investigation. In addition, if the reproduction rate of timeout failure is very low, the investigation itself may not be possible. On the other hand, in the latter means, the administrator of the computer system needs to estimate the faulty part by following the signal history of one component of the computer system such as the processor bus. For this reason, it is difficult to specify the faulty part unless the time-out fault has occurred in relation to the location where the trace is collected.

  As described above, in the prior art, when a computer system performs an operation not intended by the designer or a hardware failure occurs due to a failure, such as a timeout failure, the computer system can be quickly recovered. This is a serious problem in a computer system that guarantees high reliability and availability.

  The object of the present invention is that when a computer system performs an operation unintended by the designer, such as a timeout failure, or a hardware failure occurs due to a failure, the administrator of the computer system To provide a computer system capable of facilitating estimation.

  The computer system proposed by the present invention is a memory access issued by a processor or an expansion card or an access to an expansion card in a chip set which is a circuit for managing the exchange of data between the processor, memory and expansion card in the computer system. Is provided with a circuit for recording the history in the chipset. In the following description, a memory access (memory read / write) issued by a processor or an expansion card in a computer system or an access to an expansion card (I / O read / write) is referred to as a transaction.

  The circuit that records history information records the transaction type such as memory address / I / O address, memory read / write, and I / O read / write, which is the destination of the transaction, and what kind of transaction in the computer system when a failure occurs It is possible to guess whether the process was executed by looking at the history information. In addition, the circuit that records history information records the transaction processing status in the chipset as history information, and by looking at the history information on the transaction processing status in the chipset when a failure occurs. Make it understandable. As an example of the transaction processing state, a transaction is issued to the destination memory or expansion card, the destination memory or expansion card returns read data, or the chipset is to the transaction issuing processor or expansion card. For example, the read data is returned. The circuit for recording history information records the time uniquely determined by the computer system when recording the transaction processing state. Specifically, a counter that counts the same value synchronously in the computer system is prepared for each circuit that collects history information, and the value of the counter is recorded simultaneously when the transaction processing state is recorded. Thereby, the administrator of the computer system can view each history information on the same time axis even when a plurality of history information is collected by the computer system.

  In addition, the computer system proposed by the present invention sends the recorded transaction processing state history information for all chipsets to the administrator of the computer system together with a failure notification when a failure occurs, or the administrator of the computer system arbitrarily selects from the outside. Means for reading out at the timing.

  According to the present invention, even if a hardware failure occurs because the computer system has performed an operation not intended by the designer or a failure occurs, such as a timeout failure, the administrator of the computer system can Since it is possible to know the transaction processing state in all the chip sets at the time of occurrence, it becomes easy to identify the faulty part of the computer system, and it is possible to quickly restore the computer system.

  Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is an example of a computer system assumed in the present invention. The computer system includes a node A 100 and a node B 130, an inter-node link 140 that connects the node A 100 and the node B 130, and a management module 150 that manages each component of the computer system.

  The inter-node link 140 enables transmission / reception of transaction information between the node A 100 and the node B 130, and is realized by a connection means suitable for the computer system to be constructed, such as a crossbar or a fully connected network. Can do. The transaction information in this description refers to information necessary for processing a transaction in the computer system. Specifically, the memory address and I / O address to be accessed, the transaction type such as memory read / write and I / O read / write, and the transaction identifier for uniquely managing the transaction in the computer system are read. Or, it is data to be written, ACK for reporting that the write process has been performed, and NACK for reporting that the read or write process could not be performed. Transaction information is issued / received between each component in the computer system via the transaction path 171.

  The functions of the management module 150 are: power management (turn on / off) of each component of the computer system, management of component information, collection of transaction information in the computer system / processing state history at the time of failure, failure notification, system environment (Temperature / Power) monitoring. In this embodiment, the management console 160 and the management module 150 can communicate via the LAN I / F 170. However, the communication means between the management console 160 and the management module 150 is not particularly limited, and communication may be performed using, for example, a serial cable. A user of the computer system can manage / operate the computer system via the management module 150 using the management console 160. When the management module 150 receives a failure report from a node in the computer system where a failure has occurred, the management module 150 issues a transaction information / processing state history collection request to each node constituting the computer system. When the transaction information / processing state history information is returned from each node in response to the collection request, the transaction information / processing state history of each node collected together with the failure notification is transmitted to the management console 160. As a result, the administrator of the computer system can know that a failure has occurred by the failure notification shown on the management console 160, and can view the transaction information / processing state history of each node sent together with the failure notification. Thus, even if the error content does not identify the faulty part, the faulty part can be specified. The management module 150 also sends the transaction information / processing status to each node constituting the computer system even when a computer system administrator issues a transaction information / processing status history collection request via the management console 160. Issue a history collection request. When the transaction information / processing state history information is returned from each node in response to the collection request, the transaction information / processing state history of each node is transmitted to the management console 160.

  The node A 100 includes processors 101 and 102, a processor bus (first path) 103, an intra-node management circuit 104, an I / O bridge 105, a PCI device 106, a memory 107, a PCI bus 108, and a chipset 110. In this embodiment, a general PCI device is used as an expansion card. However, the present invention is not limited to this, and for example, the latest PCI-Express device may be used. Node B 130 has exactly the same components as node A 100. In this embodiment, a two-node configuration is used, but the number of nodes is not particularly specified.

  The processor bus 103 connects the processors 101 and 102 and the chipset 110, and issues and receives transaction information between the processors 101 and 102 and the chipset 110.

  The intra-node management circuit 104 receives a failure notification from each component of the chipset 110 via the failure information notification path 172 and receives information from the processor bus controller 111 and the I / O controller 112 via the failure information collection path 173. Acquisition of transaction information and processing state history, and failure notification to the management module 150 are performed. The intra-node management circuit 104 can communicate with the management module 150 via the LAN I / F (second path) 170, and the management module 150 that has received the fault report manages the intra-node of each node constituting the computer system. Transaction information / processing state history is collected from the processor bus controller 111 and the I / O controller 112 of each node via the circuit 104.

  The I / O bridge 105 connects the chip set 110 and the PCI device 106 via the PCI bus 108, and issues / receives data between the chip set 110 and the PCI device 106.

  The chip set 110 includes a processor bus controller 111, an I / O controller 112, a memory controller 113, and an inter-node link controller 114.

  The processor bus controller 111 receives the transaction and write data issued by the processor 101 or the processor 102 via the processor bus 103, looks at the transaction information, and reads the component information of the chipset 110 to be read / written. Issue transaction and write data. For example, in the processor controller 111 in the node A 100, if the transaction access address is addressed to the memory 107 of the node A, the I / O controller 112 is addressed to the memory controller 113. If the address is addressed to the memory B of the node B or the PCI device 106, the transaction and write data are issued to the inter-node link controller 114. The processor bus controller 111 transmits the read data transmitted from each component of the chipset 110 to the processor 101 or 102 via the processor bus 103. Since the processor bus controller 111 includes a circuit for recording transaction information / processing state history, which is a feature of the present invention, the internal configuration and processing contents will be described in detail later.

  The I / O controller 112 issues I / O read / write and write data issued by the PCI device in each processor or other node in the computer system to the PCI device 106 via the I / O bridge 105. Also, the data read from the PCI device 106 is issued to the processor or PCI device that is the transaction issuing source. In the case of I / O write, when the I / O write and the write data are issued to the PCI device 106 via the I / O bridge 105, the I / O controller 112 sends the transaction issuing processor or PCI device. Issue an ACK. If a failure occurs in the I / O bridge 105, the PCI bus 108, and the PCI device 106, and the I / O read or I / O write and write data cannot be issued to the PCI device 106, the I / O controller 112 , NACK is issued to the transaction issuing processor or PCI device. Specific examples of the failure include a failure of the PCI device 106, the PCI device 106 not responding to the transaction, or the SERR signal being asserted on the PCI bus 108. The PCI device 106 issues a read / write transaction and write data to the memory 107 or the PCI device 106 of another node in the same manner as the processor. For this reason, the I / O controller 112 receives the transaction and write data issued by the PCI device 106 via the I / O bridge 105, sees the transaction information, and reads and writes the transaction and write to the component to be read / written. Publish data. Further, the processor bus controller 110 transmits read data transmitted from each component of the chipset 110 to the PCI device 106 via the I / O bridge 105. Similar to the processor bus controller 111, the I / O controller 112 also includes a circuit that records the transaction information / processing state history, which is a feature of the present invention, so the internal configuration and processing contents will be described in detail later. .

  The memory controller 112 issues memory read / write and write data issued by each processor or each PCI device in the computer system to the memory 107. Also, the data read from the memory 107 is issued to the processor or PCI device that is the transaction issuer. In the case of memory write, when the memory write and write data are issued to the memory 107, the memory controller 113 issues an ACK to the transaction issuing processor or PCI device. Similarly to the I / O controller 112, when a failure such as a memory failure occurs and a memory read or memory write and write data cannot be issued to the memory 107, a NACK is issued to the transaction issuing processor or PCI device. To do.

  The inter-node link controller 114 issues transaction information issued by the processor or PCI device in the own node to other nodes via the inter-node link 140, or transaction information issued by the processor or PCI device of other nodes. Receive. Then, the inter-node link controller 114 issues the received transaction information to the components in the own node to be read / written.

  The internal configuration and processing contents of the processor bus controller 111 having a circuit for recording transaction information / processing state history, which is a feature of the present invention, will be described in detail with reference to FIG. The processor bus controller 111 includes a processor bus I / F controller 200, a transaction controller 201, a management circuit I / F controller 202, an address queue 203, a data in queue 204, a data out queue 205, another unit I / F controller 206, a failure report A circuit 207 and a counter 208 are provided.

  The processor bus I / F controller 200 receives a transaction or write data issued by the processor 101 or 102 from the processor bus 103, or transmits read data to the processor bus 103. When the transaction information is received, the processor bus I / F controller 200 stores the transaction information in an entry in which the transaction information in the address queue 203 is invalid. When there are a plurality of invalid entries, it is desirable to store the transaction information by the LRU method because the transaction information can be viewed in time series. If there is no invalid entry in the address queue 203, the processor bus I / F controller 200 stops processing of the processor bus 103 so that the processor cannot issue a transaction or write data. When write data is received from the processor bus 103, the write data is stored in the data in queue 204. When the read data and ACK and NACK issued by the data out queue 205 are received, the read data, ACK and NACK are issued to the processor bus 103. Further, the processor bus I / F controller 200 monitors the state of the processor bus 103 and, when detecting a failure occurring in the processor bus 103, notifies the failure report circuit 207 of a failure. Specific examples of the failure detected by the processor bus 103 include a parity error of a transaction target address, an ECC error of read / write data, and the like.

  The address queue 203 is a circuit that stores transaction information until transaction processing is completed in the chipset 110. The address queue 203 only notifies the transaction controller 201 that the transaction has been stored, and the transaction controller 201 controls the invalidation of the transaction information when the transaction issuance from the address queue 203 and the transaction processing is completed. FIG. 3 shows a configuration example of the address queue 203. The address queue in FIG. 3 is an example when the number of entries is n. The number of n may be set to a value suitable for the computer system to be realized. For example, the number of transactions that the processor can issue to the chipset at the same time, or the number of transaction information / processing state history to be collected may be set. The entry number 300 stores an entry number. The valid bit 301 indicates that the transaction information stored in the entry is valid when “1” and is invalid when “0”. The target address 302 stores a memory address or I / O address targeted by the transaction. The type 303 stores transaction types such as memory read / write and I / O read / write. The identifier 304 stores a number that can uniquely identify a transaction in the computer system.

  The constituent elements of the address queue 203 described below indicate the transaction processing status in the chipset 110. The issue status 305 has a flag indicating that the transaction has been issued to the destination component, and a counter value for storing the issued time. “Flag” indicates that a transaction has been issued when “1”, and indicates that it has not been issued when “0”. Further, the “counter value” contains the value of the counter 208 when the transaction is issued. The reception status 306 includes a “status” indicating that write data has been received from the processor bus 103 or read data and ACK and NACK have been received from the components of the chipset 110, and a counter value for storing the received time. Have. “Status” indicates that read / write data has been received at “data”, ACK or NACK has been received at “ack” or “nack”, and not received at “0”. Show. The counter value is the value of the counter 208 when the read / write data, ACK and NACK are received. The completion status 307 is a counter that issues read data, ACK, and NACK to the processor bus 103 and stores a “flag” indicating that the transaction processing in the chipset 110 is completed, and the time when the transaction processing is completed. Has a value. The flag indicates that the transaction process is completed when “1”, and indicates that the transaction process is not completed when “0”. The counter value is the value of the counter 208 when the transaction processing is completed.

  In this embodiment, three types of statuses 305 to 307 are shown as information indicating the transaction processing state in the chipset 110, but other statuses may be added if necessary. As an example of the status to be added, the completion / non-completion status of the cache matching control processing in the computer system that provides the ccNUMA configuration of the memory can be mentioned. In addition, since the transaction processing state in the chipset only needs to be recorded together with the counter value, the processing state expression means such as “flag” and “state” are not particularly specified, and is suitable for the computer system to be realized. An expression means may be used.

  The data-in queue 204 is a queue that stores write data. The data out queue 205 is a queue that stores read data, ACK, and NACK. In both the data-in queue 204 and the data-out queue 205, the transaction controller 201 issues an instruction to issue stored data. In this embodiment, both the data-in queue 204 and the data-out queue 205 store data, ACK, and NACK in the entry having the same entry number as when the corresponding transaction information is stored in the address queue 203. Shall. Accordingly, the validity / invalidity determination of the information stored in the data-in queue 204 and the data-out queue 205 is realized by the valid bit 301 of the address queue 203.

  The counter 208 indicates a counter value common to each node. For example, when the computer system is powered on, the counter is incremented synchronously at each node and the counter is operated at the same frequency, so that a common counter value can be realized at each node.

  The other unit I / F controller 206 issues the transaction received from the address queue 203 and the write data received from the data-in queue 204 to each component of the chipset 110 that is the transaction destination, or is the transaction destination. Read data, ACK, and NACK are received from each component of the chipset 110. When the read data, ACK, and NACK are received, the other unit I / F controller 206 stores the read data, ACK, and NACK in the data out queue 205. In addition, the other unit I / F controller 206 monitors the I / F of the components 112 to 113 of the chipset 110, and if a failure is detected when receiving read data, ACK, or NACK, the failure reporting circuit 207 is notified of the failure. To do. Similar to the failure detected by the processor bus 103, a parity error of a transaction target address, an ECC error of read / write data, and the like can be given.

  The transaction controller 201 controls transactions, read / write data, and ACK and NACK. Information on whether or not the component of the destination chipset 110 can receive the transaction or write data is obtained from the other unit I / F controller 206, and if it can be received, a transaction issuance instruction is sent to the address queue 203, or An instruction to issue write data is issued to the data in queue 205. Further, information on whether or not read data and ACK and NACK can be issued to the processor bus 103 is obtained from the processor bus I / F controller 200, and if it can be issued, the read data and ACK, Issue a NACK issue instruction. When issuing an instruction to issue read data, ACK, and NACK to the data out queue 205, the transaction controller 201 determines that the transaction processing in the chipset 110 has been completed, and sets the valid bit 301 of the address queue 203 to “ The transaction information stored in the address queue 203, the data in queue 204, and the data out queue 205 is invalidated. The reason why only the valid bit is updated when the entry is invalidated is to enable viewing of information on a transaction for which transaction processing has been completed.

  Another function of the transaction controller 201 is to update the statuses 305 to 307 indicating the transaction processing state of the address queue 203. When a transaction issuance instruction is issued to the address queue 203, the transaction controller 201 updates the issuance status 305. When the read data, ACK, and NACK are stored in the data out queue 205, a notification that the read data, ACK, and NACK are stored is received from the data out queue 205, and the reception status 306 is updated. Alternatively, when the write data is stored in the data-in queue 204, a notification that it has been stored is received from the data-in queue 204, and the reception status 306 is updated. When a read data, ACK, or NACK issuance instruction is issued to the data out queue 205, the completion status 307 is updated.

  The failure detected by the transaction controller 201 is a transaction processing timeout. The transaction controller 201 monitors the time from when the transaction information is stored in the address queue 203 until it is invalidated, and if the transaction information continues to be valid in the address queue 203 beyond the specified time, a transaction processing timeout may occur. The transaction controller 201 transmits a failure report to the failure report circuit 207 by determining that it has occurred. In this embodiment, the failure detected by the transaction controller 201 is only a timeout failure. However, the types of failures to be detected may be increased according to the specifications of the computer system to be realized.

  The failure report circuit 207 issues a failure report from the processor bus I / F controller 200, the transaction controller 201, and the other unit I / F controller 206 to the intra-node management circuit 104 via the failure information notification path 172.

  The management circuit I / F controller 202 is a circuit that processes a transaction information / processing state history collection request sent from the intra-node management circuit 104 via the failure information collection path 173. The management circuit I / F controller 202 that has received the transaction information / processing state history collection request reads the transaction information / processing state of all entries in the address queue 203, and passes the failure information collection path (second path) 173. The read transaction information / processing state is transmitted to the node management circuit 104. The path used for collecting the transaction information / processing state is realized by a completely different path from the path for sending the transaction information, and even if a failure occurs and the transaction processing of the chipset 110 stops, the transaction information / processing state history It is guaranteed that the management module 150 can collect data.

  Next, similar to the processor bus controller 111, the internal configuration and processing contents of the I / O controller 112 having a circuit for recording the history of transaction information and processing state, which is a feature of the present invention, will be described with reference to FIG. . The I / O controller 112 includes an I / O I / F controller 400, a transaction controller 401, a management circuit I / F controller 402, an address queue 403, a data in queue 404, a data out queue 405, another unit I / F controller 406, A failure report circuit 407, a counter 408, and an I / O request controller 409 originating from another unit are provided.

  The other unit originating I / O request controller 409 is a circuit that processes an I / O read / write issued by a PCI device in each processor or other node in the computer system. When information indicating that I / O read / write and write data can be issued from the I / O I / F controller 400 to the I / O bridge 105 is obtained, the other unit originating I / O request controller 409 reads the I / O I / O I / O read / write and write data are issued to the I / O bridge 105 via the F controller 400. Further, the other unit originating I / O request controller 409 obtains information from the other unit I / F controller 406 as to whether or not the component of the destination chipset 110 can receive the read data. The read data read from the PCI device 106 is issued to the processor or PCI device that is the transaction issuing source via the other unit I / F controller 406. In the case of I / O write, when the I / O write and write data are issued to the PCI device 106 via the I / O bridge 105, the other unit originating I / O request controller 409 determines whether the transaction issuing processor or An ACK is issued to the PCI device. If a failure occurs in the I / O bridge 105, the PCI bus 108, and the PCI device 106 and a transaction or write data cannot be issued to the PCI device 106, the I / O controller 112 determines whether the transaction issuing processor or the PCI is issued. Issue a NACK to the device.

  The I / O I / F controller 400 receives the transaction and write data from the I / O bridge 105, the read data from the PCI device 106 for the I / O read issued by the PCI device in each processor or other node in the computer system. Receive or issue read data and ACK and NACK to the I / O bridge 105, and I / O read / write and write data issued by each processor in the computer system or a PCI device in another node. When a transaction is received, the I / O I / F controller 400 stores the transaction information in an entry in which the transaction information in the address queue 403 is invalid. When there are a plurality of invalid entries, it is desirable to store the transaction information by the LRU method because the transaction information can be viewed in time series. When the write data is received from the I / O bridge 105, the I / O I / F controller 400 stores the write data in the data in queue 404. If there is no invalid entry in the address queue 403, the I / O I / F controller 400 stops the processing of the I / O bridge 105 so that the PCI device cannot issue a transaction or write data. When read data, ACK, and NACK are received from the data out queue 405, the read data, ACK, and NACK are issued to the I / O bridge 105. When the I / O I / F controller 400 receives the read data from the PCI device 106 for the I / O read issued by the PCI device in each processor or other node in the computer system, the I / O I / F controller 400 issues an I / O request originating from another unit. Read data is issued to the controller 409. Further, the I / O I / F controller 400 monitors the state of the I / O bridge 105 and, when detecting a failure occurring in the I / O bridge 105, notifies the failure report circuit 407 of a failure. Specific examples of the failure detected by the I / O bridge 105 include SERR assert detection, master abort, and the like because the present embodiment uses the PCI bus 108.

  The other unit I / F controller 406 sends the transaction received from the address queue 403 and the write data received from the data in queue 404 to each component of the chipset 110 that is the destination of the transaction, each processor in the computer system, and others. The read data from the PCI device 106 is issued for the I / O read issued by the PCI device in the node. When the other unit I / F controller 406 receives read data and ACK and NACK from each component of the chipset 110 that is the destination of the transaction, the other unit I / F controller 406 reads the data out queue 405. Data, ACK and NACK are stored. When I / O read / write and write data issued by a PCI device in each processor or other node in the computer system are received, the I / O read / write and write data is sent to the I / O request controller 409 from other units. Send. Also, the other unit I / F controller 406 monitors the I / F of the components 111, 113, and 114 of the chipset 110, and if a failure is detected when receiving read data, ACK, or NACK, the other unit I / F controller 406 sends a failure report circuit 407. Report a failure. Specific examples of the failure to be detected include a parity error of a target address of a transaction, an ECC error of read / write data, and the like.

  The components 401 to 405, 407, and 408 of the I / O controller 112 have the same functions as those of the components 201 to 205, 207, and 208 of the processor bus controller 111, and thus description thereof is omitted.

The flow of failure notification and transaction information / processing state history collection when a failure is detected in this embodiment will be described below. For the sake of explanation, assume that a timeout failure has occurred in the transaction controller 201 in the processor bus controller 111 of the node A 100.
When the transaction controller 201 detects a timeout failure, the transaction controller 201 notifies the failure reporting circuit 207 that a timeout failure has occurred. The failure report circuit 207 that has received the failure report reports to the management module 150 via the intra-node management circuit 104 that “the timeout failure has occurred in the transaction controller 201 in the processor bus controller 111 of the node A 100”. The management module 150 that has received the failure report issues a transaction information / processing state history collection request to the intra-node management circuit 104 of each node. Upon receiving the transaction information / processing state history collection request, the intra-node management circuit 104 reads the transaction information / processing state of all entries in the address queues 203 and 403 via the management circuit I / F controllers 202 and 402. Then, the intra-node management circuit 104 transmits the read transaction information / processing state history of the address queues 203 and 403 to the management module 150. Upon receiving the transaction information / processing state history of the address queues 203 and 403 of each node from the intra-node management circuit 104 of each node, the management module 150 stores the transaction information / processing state history as “the processor bus controller of the node A 100”. A failure notification indicating that a timeout failure has occurred in the transaction controller 201 at 111 is transmitted to the management console 160.

  The administrator of the computer system refers to the transaction information / processing state history sent together with the timeout failure notification, and specifies the failure site as follows, for example. Looking at the transaction information / processing state history collected from the address queue 203 of the node A 100, it is confirmed that read data and NACK are not returned only for the I / O read addressed to the PCI device 106 of the node B 130 when a failure occurs. Suppose that. Since no NACK is returned, it is considered that the I / O controller 112 of the Node B 130 has issued an I / O request to the PCI device. In this case, it can be presumed that the failure of the PCI device 106 of the Node B 130 does not return read data is the cause of the timeout failure, and therefore, the PCI device 106 of the Node B 130 can be cited as a failure part. However, after the PCI device 106 of the Node B 130 issues read data, there is a case where transmission of return data is stopped in the chip set 110 of the Node B 130 due to, for example, a logic failure of the chip set. . In this case, the previous guess is wrong, and the chipset 110 of the Node B 130 is correct for the faulty part. If it is desired to prevent such a failure site estimation error as much as possible, the granularity of the transaction processing state to be recorded may be made fine. In this embodiment, the transaction processing state is recorded only at three timings: transaction issuance, reception of read / write data or ACK and NACK, and completion of transaction processing. Therefore, for example, if the transaction processing status is recorded even when the transaction information is issued / received by the memory controller or the I / O controller, the transmission status of the return data can be known in detail, so that a fault location estimation error is prevented as much as possible. Things are possible.

As described above, according to the above embodiment, the administrator of the computer system can know the transaction processing state history in all the chip sets in the computer system together with the failure notification. Therefore, the following effects can be obtained.
(1) Since the transaction processing state history in all the chip sets in the computer system can be known, the transaction processing state at the time of failure occurrence can be known even when a timeout failure occurs, and the failure part can be specified.
(2) It is not necessary to use a commercially available digital signal observation device such as a logic analyzer to indicate the failure location when a timeout failure occurs, and it is not necessary to reproduce the phenomenon. Can do.
(3) Instead of looking at one component of the computer system, such as tracing the processor bus, the transaction processing status in all chip sets of the computer system is seen, so information related to timeout failures can be obtained without fail. The analysis of the part becomes easy.

It is a block diagram of a computer system assumed by the present invention. It is a block block diagram of the processor bus controller in the Example of this invention. It is a figure which shows the structure of the address queue in the Example of this invention. It is a block block diagram of the I / O controller in the Example of this invention.

Explanation of symbols

100, 130 ... Node A and Node B,
101, 102 ... processor,
103 ... processor bus,
104: In-node management circuit,
105 ... I / O bridge,
106: PCI device,
107: Memory,
108 ... PCI bus,
110 ... chipset,
111 ... Processor bus controller,
112 ... I / O controller,
113 ... Memory controller,
114: Inter-node link controller,
140 ... inter-node link,
150 ... management module,
160 ... management console,
170 ... LAN I / F,
171 ... Transaction path,
172 ... failure information notification path,
173 ... Fault information collection path,
200: Processor bus I / F controller,
201, 401 ... transaction controller,
202, 402 ... management circuit I / F controller,
203, 403 ... address queue,
204, 404 ... data in queue,
205, 405 ... Data out queue,
206, 406 ... Other unit I / F controller,
207, 407 ... fault reporting circuit,
208, 408 ... counter,
300 ... Entry number,
301 ... Valid bit of entry,
302 ... Target address of transaction,
303 ... Transaction type,
304 ... transaction identifier,
305 ... Transaction issue status,
306 ... Transaction reception status,
307 ... transaction completion status,
400 ... I / O I / F controller,
409 ... I / O request controller originating from another unit.

Claims (3)

A first path; a processor and a chipset connected to the first path; a memory and an expansion card connected to the chipset; and the expansion between the processor and the memory and the processor and the expansion by the chipset. In a computer system having a node for controlling information exchange between cards,
The chip set includes a recording unit that records, together with time information, processing status in the chip set of access to the memory issued by the processor or an expansion card and access to the expansion card issued by the processor. ,
The node further includes means for reading out the processing state and time information in the chip set recorded in the recording means via the second path and transmitting to the other apparatus in response to a request from the other apparatus. A computer system characterized by   The computer system according to claim 1, wherein the time information is a time uniquely determined in the chipset.   Each of the chips has a plurality of nodes, and the processing state in each chip set of access from the processor or expansion card of each node to the memory or expansion card of another node is uniquely determined by the plurality of nodes. 2. The computer system according to claim 1, wherein the computer system records the information in a set recording means.

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