CN112650612A

CN112650612A - Memory fault positioning method and device

Info

Publication number: CN112650612A
Application number: CN202011550974.9A
Authority: CN
Inventors: 赵俊
Original assignee: New H3C Cloud Technologies Co Ltd
Current assignee: New H3C Cloud Technologies Co Ltd
Priority date: 2020-12-24
Filing date: 2020-12-24
Publication date: 2021-04-13

Abstract

The specification provides a memory fault positioning method and device, and relates to the technical field of communication. A memory fault positioning method is applied to BMC and comprises the following steps: when a fault is determined according to a register in a logic chip on a mainboard, acquiring fault information of an internal register from a processor of the mainboard; determining a system address of a fault memory according to the fault information; according to the mapping relation between the stored system address and the physical address, carrying out address conversion on the system address to obtain the physical address of the fault memory; the physical address is recorded in a system event log. The method can improve the maintainability of the server.

Description

Memory fault positioning method and device

Technical Field

The present disclosure relates to the field of communications technologies, and in particular, to a method and an apparatus for locating a memory fault.

Background

With the rapid development of information technology at home and abroad, servers have been widely applied to various industries, and people pay more and more attention to the reliable operation of the servers. In the faults of the server, the hard disk and the memory occupy the first two digits, wherein the memory faults can directly influence the operation of the system, so that the service interruption of a client is caused, and the rapid positioning of the memory faults becomes an important research direction. The memory failure is mainly divided into correctable errors and uncorrectable errors, the correctable errors do not affect the operation of the system, and the uncorrectable errors can cause the system to hang up, so that the system stops working completely. Therefore, uncorrectable errors need to be of more concern.

For the system hang-up, there are two cases, one is MCERR (Machine Check Error) caused by system software, and the other is IERR (Internal Error) caused by system hardware. Under the condition of MCERR, the BIOS (Basic Input Output System) of the server can still work, and performs error detection and reporting. However, in the case of the IERR, the BIOS also stops operating, and error location and reporting cannot be implemented. Therefore, how to realize the positioning and reporting of the memory fault under the condition of the occurrence of the IERR is a problem to be solved urgently by technical staff.

Disclosure of Invention

In order to overcome the problems in the related art, the present specification provides a memory fault location method and apparatus.

According to a first aspect of the embodiments of the present specification, there is provided a memory fault location method, applied to a BMC, including:

when a fault is determined according to a register in a logic chip on a mainboard, acquiring fault information of an internal register from a processor of the mainboard;

determining a system address of a fault memory according to the fault information;

according to the mapping relation between the stored system address and the physical address, carrying out address conversion on the system address to obtain the physical address of the fault memory;

the physical address is recorded in a system event log.

Optionally, before determining that a fault occurs according to a register in a logic chip on the motherboard, the method further includes:

and receiving and storing the mapping relation between the system address and the physical address of the memory.

Further, determining a system address of the failed memory according to the failure information, further comprising:

determining a fault type according to the first fault information acquired from the first register;

if the fault type is the fault of the processor, determining a fault module according to second fault information acquired from a second register;

and acquiring the system address corresponding to the fault module from the third register corresponding to the fault module.

Further, after determining the type of the fault according to the first fault information acquired in the first register, the method further includes:

and if the memory fault is determined not to be the fault of the processor according to the fault type, stopping the positioning of the memory fault.

Further, the fault module comprises an IMC, an IIO, an MLC and a DCU;

acquiring a system address corresponding to the fault module from a third register corresponding to the fault module, wherein the system address corresponding to the fault module comprises:

and if the fault module is IIO and the system address cannot be analyzed, acquiring the system address corresponding to the IMC from a third register corresponding to the IMC.

According to a second aspect of the embodiments of the present specification, there is provided a memory fault location device, applied to a BMC, including:

the acquisition unit is used for acquiring the fault information of the internal register from the processor of the mainboard when the fault is determined according to the register in the logic chip on the mainboard;

the address unit is used for determining a system address of the fault memory according to the fault information;

the conversion unit is used for carrying out address conversion on the system address according to the mapping relation between the stored system address and the physical address to acquire the physical address of the fault memory;

and the recording unit is used for recording the physical address in the system event log.

Optionally, the apparatus further includes:

and the storage unit is used for receiving and storing the mapping relation between the system address and the physical address of the memory.

Further, the address unit includes:

the type determining subunit is used for determining a fault type according to the first fault information acquired from the first register;

the module determining subunit is used for determining a fault module according to the second fault information acquired from the second register if the fault type is the fault of the processor;

and the address determining subunit is used for acquiring the system address corresponding to the fault module from the third register corresponding to the fault module.

Optionally, the apparatus further includes:

and the termination unit is used for stopping the positioning of the memory fault if the processor is determined not to be in fault according to the fault type.

Further, the fault module comprises an IMC, an IIO, an MLC and a DCU;

and the address unit is further used for acquiring the system address corresponding to the IMC from the third register corresponding to the IMC if the fault module is the IIO and the system address cannot be resolved.

The technical scheme provided by the implementation mode of the specification can have the following beneficial effects:

in the embodiment of the present specification, after a fault is determined on a motherboard, fault information of an internal register in a processor is obtained, a system address of a memory in which the fault occurs is determined according to the fault information, address conversion is performed to obtain a physical address, and then recording is performed in a system event log, so that a problem that a system is hung up due to an internal error, and thus, memory fault location cannot be performed is avoided, and maintainability of a server is improved.

It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the specification.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present specification and together with the description, serve to explain the principles of the specification.

Fig. 1 is a flowchart of a memory fault location method according to the present application;

fig. 2 is a schematic structural diagram of a motherboard to which a memory fault location method according to the present application is applied;

FIG. 3 is a block diagram illustrating the relationship between a processor and a memory according to the present application;

fig. 4 is a schematic structural diagram of a memory fault location device according to the present application.

Detailed Description

Reference will now be made in detail to the exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, like numbers in different drawings represent the same or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present specification.

The application provides a memory fault positioning method, which is applied to BMC and comprises the following steps:

s100, when the memory is determined to have a fault according to the register in the logic chip on the mainboard, obtaining fault information of the internal register from a processor of the mainboard.

As shown in fig. 2, the main board is provided with a processor, a logic chip, and a BMC (Baseboard Management Controller). The BMC may monitor devices and modules in the server and record in an SEL (System Event Log). The processor may be a CPU or other devices for performing operations, and the motherboard may be provided with a plurality of CPUs, such as two CPUs shown in fig. 2. The Logic chip may be a CPLD (Complex Programmable Logic Device). The present application will be described with reference to the structure of fig. 2. The BMC can be connected with the CPU through PECI (Platform Environment Control Interface), and is connected with the CPLD through a CATERR/MSMI pin, and the CPU is connected with the CPLD through the CATERR/MSMI pin.

When the CPU knows that a fault occurs according to hardware interruption, a fault notification is sent to the CPLD through a CATERR/MSMI pin, and the CPLD records in an internal register according to the fault notification. In the scenario shown in FIG. 2, it can be seen that CPU1 is connected to the CPLD through the CATERR1/MSMI1 pin, and CPU2 is connected to the CPLD through the CATERR2/MSMI2 pin.

In the normal working process of the server, the BMC may periodically (for example, with 1 second as a period) read out the value of the internal register from the CPLD through the CATERR3/MSMI3 pin to determine whether the CPU has reported a fault, if the value of the internal register indicates that there is no fault, continue to count time until the next period is read again, and if the value of the internal register indicates that there is a fault, the BMC is triggered, accesses the internal register of the CPU through the PECI, and acquires the fault information recorded by the internal register of the CPU. When the mainboard is provided with two CPUs, the BMC can respectively acquire and record the fault information in the internal registers of the two CPUs.

And S101, determining the system address of the fault memory according to the fault information.

The CPU includes a plurality of internal registers for storing fault information related to a fault, and the BMC needs to determine a system address of a memory in which the fault occurs according to values of the plurality of internal registers. The internal memory used is explained below.

First register (e.g., MCA _ ERR _ SRC _ LOG): the register stores the type of failure, including the failure of the CPU and an external failure (i.e., the failure occurs in another CPU), and whether IERR is MCERR at the time of the failure. When a memory failure occurs, although it can be identified as IERR, it is recorded in the register related to MCERR as well, and more information about the memory failure is recorded in the register related to MCERR.

Whether the fault type of the fault is the fault of the present CPU can be determined based on the first fault information (e.g., bits [28:27] and [19:18] in the first register) stored in the first register. If the fault is not the fault of the CPU, other internal registers of the CPU do not need to be analyzed continuously, the memory fault location aiming at the CPU is stopped, and if the fault is the fault of the CPU, other internal registers of the CPU are analyzed continuously.

Second register (e.g., MCerr _ Logging _ Reg): in the internal register, a module identification (i.e., second failure information) of the failed module, which is typically a module associated with memory, is stored. As shown in fig. 3, IMCs are provided in a processor, each IMC is provided with a plurality of channels, and each channel may correspond to a plurality of memories. Then, the module may include the IMC, and the second failure information may distinguish whether the failure occurs in the IMC itself or in the plurality of channels associated with the IMC. Each channel can be plugged with a memory. In fig. 3, it can be seen that two IMCs are provided in one processor, 3 channels are associated under one IMC, and two memories can be plugged into one channel.

For example, bits [7:0] in MCerr _ Loging _ Reg may be used to determine whether the fault originated from the IMC itself or the channel associated with the IMC. When it is confirmed from bits [7:0] that the failure originated from a lane, further look at bits [13:10] is needed to determine which lane to locate.

Specifically, bit [7:0] ═ 01100000 represents IMC0, bit [7:0] ═ 01100100 represents IMC1, the channel is determined from bit [13:10] after IMC is determined, bit [13:10] ═ 0101 represents channel 0, bit [13:10] ═ 0111 represents channel 1, and bit [13:10] ═ 1001 represents channel 2. The specific bit values in the registers are not enumerated one by one for the other channels.

The IMC itself is determined from bit 2 that the fault originated, and it is also possible to determine which IMC the fault is in from bits [7:0 ]. Bit [7:0] ═ 01100010 represents IMC0, and bit [7:0] ═ 01100110 represents IMC 1.

Through the above process, a specific fault module can be determined from the second fault information acquired from the second register.

Corresponding registers are provided in the CPU for the modules to store the state of the modules, which may be referred to as module specific registers. At the module. For example, MC7_ BANK and MC8_ BANK may be set to store the state information of the block and the system address for IMC0 itself and IMC1 itself. For the 6 channels associated with IMC0 and IMC1, the 6 registers MC13_ BANK through MC18_ BANK may be set to store the state information and system address of the module.

In the MC7_ BANK, MC8_ BANK, and MC13_ BANK to MC18_ BANK, a plurality of sub-registers are provided, including a STATUS register (MC _ STATUS), an address register (MC _ ADDR), a redundant register (MC _ MISC), and a control register (MC _ CTL). Wherein a validity flag is set in the status register and the address register. In the process of acquiring the system address, the BMC checks whether the validity flag in the status register is valid, checks the address register if the validity flag is valid, confirms whether the validity flag in the address register is valid when the address register is checked, and acquires the address stored in the address register as the system address if the validity flag is valid.

Also, due to the effects of memory diffusion, memory failures may be logged to other modules, such as IIO, MLC and DCU. Wherein, a corresponding register (MC3_ BANK) is arranged for MLC, a corresponding register (MC1_ BANK) is arranged for DCU, and a corresponding register (MC6_ BANK) is arranged for IIO.

When the failure module is an IIO, whether a PCIE (Peripheral Component Interconnect Express) failure exists can be determined according to the sub-register (MC6_ MISC) in the MC6_ BANK, that is, whether the system address of the PCIE associated with the IIO can be resolved. If the system address of the PCIE cannot be resolved, it may be considered to be caused by a failure of the memory. At this time, the system address of the fault memory may be obtained for the register corresponding to the IMC.

And S102, according to the mapping relation between the stored system address and the physical address, performing address conversion on the system address to acquire the physical address of the fault memory.

The mapping relationship between the system address and the physical address can be stored in the BMC, and after the BMC acquires the system address based on the fault memory, the system address can be converted into the actual physical address based on the mapping relationship. The physical address indicates where the memory is plugged in, which can be used to locate the memory in the server.

The mapping relationship may be stored in the BMC in a fixed relationship, or may be sent to the BMC in the form of a file through a data channel between the BIOS and the BMC before step S100, that is, during the BIOS power-on process, so that the BMC stores the file in the nonvolatile memory, and thus, the file is used when a memory failure is detected.

The specific system address and physical address translation is similar to the current approach and will not be described further.

And S103, recording the physical address in the system event log.

After the BMC determines the physical address of the fault memory, the fault memory may be recorded in a SEL (System Event Log) of the BMC and may be displayed on a display device such as a display.

After the physical address of the failed memory is displayed, the worker can position the memory in the server according to the physical address, so as to replace the failed memory.

In the embodiment of the present specification, after a fault is determined on a motherboard, fault information of an internal register in a processor is obtained, a system address of a memory in which the fault occurs is determined according to the fault information, address conversion is performed to obtain a physical address, and then recording is performed in a system event log, so that a problem that a system is hung up due to an internal error, and thus, fault location of the memory cannot be performed is avoided, and maintainability of a server is improved.

In a large server, a large amount of memory may be provided therein, and in this way, a failed memory can be located from the large amount of memory.

Correspondingly, the present application further provides a memory fault location device, as shown in fig. 4, applied to a BMC, including:

Optionally, the apparatus further includes:

Further, the address unit includes:

Optionally, the apparatus further includes:

Further, the fault module comprises an IMC, an IIO, an MLC and a DCU;

It will be understood that the present description is not limited to the precise arrangements described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

The above description is only for the purpose of illustrating the preferred embodiments of the present disclosure and is not to be construed as limiting the present disclosure, and any modifications, equivalents, improvements, etc. made within the spirit and principle of the present disclosure are intended to be included within the scope of the present disclosure.

Claims

1. A memory fault positioning method is applied to a Baseboard Management Controller (BMC), and comprises the following steps:

recording the physical address in a system event log.

2. The method of claim 1, further comprising, prior to said determining a fault from a register in a logic chip on a motherboard:

3. The method of claim 1, wherein determining the system address of the failing memory based on the failure information further comprises:

4. The method according to claim 3, wherein after determining the fault type of the memory fault according to the first fault information obtained from the first register, the method further comprises:

and if the processor is determined not to be the fault according to the fault type, stopping the positioning of the memory fault.

5. The method according to claim 3, characterized in that the failure module comprises an integrated management controller IMC, an integrated input-output module IIO, an intermediate buffer MLC and a data buffer DCU;

the obtaining the system address corresponding to the faulty module from the third register corresponding to the faulty module includes:

6. A memory fault locating device is applied to BMC and comprises:

the system comprises an acquisition unit, a processing unit and a control unit, wherein the acquisition unit is used for acquiring the fault information of an internal register from a processor of a mainboard when the fault is determined according to a register in a logic chip on the mainboard;

the address unit is used for determining the system address of the fault memory according to the fault information;

and the recording unit is used for recording the physical address in a system event log.

7. The apparatus of claim 6, further comprising:

8. The apparatus of claim 6, wherein the address unit comprises:

9. The apparatus of claim 8, further comprising:

10. The apparatus of claim 8, wherein the failed module comprises an IMC, an IIO, an MLC, and a DCU;

the address unit is further configured to obtain the system address corresponding to the IMC from a third register corresponding to the IMC if the faulty module is an IIO and the system address cannot be resolved.