CN117711475A - Fault detection circuit and method of storage unit and functional chip - Google Patents

Abstract

The application relates to the field of fault detection and discloses a fault detection circuit and method of a storage unit and a functional chip, wherein the fault detection circuit comprises: the first detection circuit is connected with the storage unit and is used for performing parity check and/or ECC check on the storage unit in the operation stage of the storage unit; the second detection circuit is connected with the storage unit or the first detection circuit and is used for performing MBIST verification on the storage unit under the condition that continuous error reporting exists; the control module is connected with the first detection circuit and the second detection circuit and used for controlling the communication relation between the first detection circuit and the second detection circuit and the storage unit, receiving the parity check result, the ECC check result and the MBIST check result and determining the fault area of the storage unit according to the parity check result, the ECC check result and the MBIST check result. Therefore, the data can be prevented from being read and written in the fault area, and the reliability of the application of the storage unit is improved.

Description

Fault detection circuit and method of storage unit and functional chip

Technical Field

The present invention relates to the field of fault detection, and for example, to a fault detection circuit and method of a memory cell, and a functional chip.

Background

In the related art, the volatile memory units (RAM, random Access Memory) of the functional chip generally employ an ECC check mechanism to check the stored data at the operation stage. However, when the continuous error reporting condition exists, the ECC check mechanism cannot analyze and locate multiple faulty addresses in the volatile storage unit, and a situation that multiple bits cannot detect the faulty addresses may also be caused.

It should be noted that the information disclosed in the foregoing background section is only for enhancing understanding of the background of the present application and thus may include information that does not form the prior art that is already known to those of ordinary skill in the art.

Disclosure of Invention

The following presents a simplified summary in order to provide a basic understanding of some aspects of the disclosed embodiments. This summary is not an extensive overview, and is intended to neither identify key/critical elements nor delineate the scope of such embodiments, but is intended as a prelude to the more detailed description that follows.

The embodiment of the disclosure provides a fault detection circuit, a fault detection method and a fault detection functional chip of a storage unit, which can realize analysis and positioning of multiple fault addresses in a volatile storage unit when continuous fault reporting exists, and can detect fault addresses which cannot be detected by multiple bits.

In some embodiments, a failure detection circuit of a memory cell includes: the first detection circuit is connected with the storage unit and is used for performing parity check and/or ECC check on the storage unit in the operation stage of the storage unit; the second detection circuit is connected with the storage unit or the first detection circuit and is used for performing MBIST verification on the storage unit under the condition that continuous error reporting exists; the control module is connected with the first detection circuit and the second detection circuit and used for controlling the communication relation between the first detection circuit and the second detection circuit and the storage unit, receiving the parity check result, the ECC check result and the MBIST check result and determining the fault area of the storage unit according to the parity check result, the ECC check result and the MBIST check result.

Optionally, the first detection circuit includes: the parity check circuit is connected with the storage unit and used for performing parity check on the storage unit; and/or the ECC check circuit is connected with the storage unit and used for performing ECC check on the storage unit.

Optionally, the parity check circuit includes: the first generation circuit, the first verification circuit and the first gate circuit; the input end of the first generating circuit is connected with the control module through the first gate circuit, and the output end of the first generating circuit is connected with the input end of the storage unit; the input end of the first verification circuit is connected with the output end of the storage unit, and the output end of the first verification circuit is connected with the control module; the first generation circuit is used for generating a first input check code and checking the storage unit based on the first input check code; the first check circuit is used for receiving a first output check code generated after the storage unit is checked, and comparing the first input check code with the first output check code to determine a parity check result; the ECC check circuit includes: a second generation circuit, a second check circuit, and a second gate circuit; the input end of the second generating circuit is connected with the control module through the second gate circuit, and the output end of the second generating circuit is connected with the input end of the storage unit; the input end of the second checking circuit is connected with the output end of the storage unit, and the output end of the second checking circuit is connected with the control module; the second generation circuit is used for generating a second input check code and checking the storage unit based on the second input check code; the second checking circuit is used for receiving a second output check code generated after checking the storage unit, and comparing the second input check code with the second output check code to determine an ECC check result.

Optionally, the fault detection circuit of the storage unit further includes: and the alarm circuit is connected with the output end of the first detection circuit and is used for outputting alarm signals according to the parity check result and/or the ECC check result.

Optionally, the fault detection circuit of the storage unit further includes: the recording module is connected with the control module and the output end of the first detection circuit and is used for recording the fault address in the storage unit according to the parity check result and/or the ECC check result.

In some embodiments, a fault detection method of a storage unit is applied to a fault detection circuit of a storage unit, where the fault detection method includes: in the operation stage of the storage unit, a first detection circuit is communicated, and parity check and/or ECC check is carried out on the storage unit; under the condition of continuous error reporting, a second detection circuit is communicated, and MBIST verification is carried out on the storage unit; and determining a fault area in the storage unit according to the MBIST check result, the ECC check result and the parity check result.

Optionally, determining the failure area inside the storage unit according to the MBIST check result, the ECC check result and the parity check result includes: determining a starting address bit with faults in the storage unit according to the parity check result and/or the ECC check result; confirming the number of address bits with faults in the storage unit according to the MBIST verification result; and determining a fault area in the storage unit according to the initial address bit and the address bit number.

Optionally, the fault detection method further includes: and in the power-on stage of the memory cell, a second detection circuit is communicated, and MBIST verification is carried out on the memory cell.

In some embodiments, a functional chip includes: a chip body; a memory unit mounted on the chip body; the fault detection circuit of the memory cell is connected with the memory cell and is mounted on the chip body.

The fault detection circuit and method of the storage unit and the functional chip provided by the embodiment of the disclosure can realize the following technical effects:

in the embodiment of the disclosure, a first detection circuit, a second detection circuit and a control module are arranged in a fault detection circuit of a storage unit. The first detection circuit may be used to parity and/or ECC check the memory cells and the second detection circuit may be used to MBIST check the memory cells. Specifically, in the operation stage of the storage unit, the first detection circuit is used for performing parity check and/or ECC check on the storage unit, and if continuous error reporting occurs, the second detection circuit is communicated for performing MBIST check on the storage unit. The initial address bit with faults in the storage unit can be analyzed and determined according to the parity check result and/or the ECC check result, and the number of the address bits with faults in the storage unit can be analyzed and determined according to the MBIST check result. Therefore, when the continuous fault reporting condition exists, the embodiment of the disclosure can analyze and locate multiple fault addresses in the volatile storage unit, and determine the fault area in the storage unit. Therefore, when the storage unit is used later, the data can be prevented from being read and written in the fault area, and the reliability of the application of the storage unit is improved.

In addition, since MBIST verification is a scan verification of all address bits in a memory cell, embodiments of the present disclosure can detect a failed address that cannot be detected by multiple bits.

The foregoing general description and the following description are exemplary and explanatory only and are not restrictive of the application.

Drawings

One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which like reference numerals refer to similar elements, and in which:

FIG. 1 is a schematic diagram of a fault detection circuit for one memory cell provided by an embodiment of the present disclosure;

FIG. 2 is a schematic diagram of a fault detection circuit of another memory cell provided by an embodiment of the present disclosure;

FIG. 3 is a schematic diagram of a fault detection circuit of another memory cell provided by an embodiment of the present disclosure;

FIG. 4 is a schematic diagram of a method for detecting a failure of a memory cell according to an embodiment of the present disclosure;

FIG. 5 is a schematic diagram of a control module provided by an embodiment of the present disclosure;

fig. 6 is a schematic diagram of a functional chip provided in an embodiment of the disclosure.

Reference numerals illustrate:

10. a failure detection circuit of the memory cell;

100. a first detection circuit; 110. a parity check circuit; 111. a first generation circuit; 112. a first verification circuit; 113. a first gate circuit; 120. an ECC check circuit; 121. a second generation circuit; 122. a second checking circuit; 123. a second gate circuit;

200. a second detection circuit; 201. MBIST verification circuitry; 202. a third gate circuit; 203. a fourth gate circuit;

300. a control module; a 301 processor; 302. a memory; 303. a communication interface; 304. a bus;

400. an alarm circuit;

500. a recording module;

600. a functional chip; 610. a chip body; 620. and a memory cell.

Detailed Description

So that the manner in which the features and techniques of the disclosed embodiments can be understood in more detail, a more particular description of the embodiments of the disclosure, briefly summarized below, may be had by reference to the appended drawings, which are not intended to be limiting of the embodiments of the disclosure. In the following description of the technology, for purposes of explanation, numerous details are set forth in order to provide a thorough understanding of the disclosed embodiments. However, one or more embodiments may still be practiced without these details. In other instances, well-known structures and devices may be shown simplified in order to simplify the drawing.

The terms first, second and the like in the description and in the claims of the embodiments of the disclosure and in the above-described figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate in order to describe embodiments of the present disclosure. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion.

The term "plurality" means two or more, unless otherwise indicated.

In the embodiment of the present disclosure, the character "/" indicates that the front and rear objects are an or relationship. For example, A/B represents: a or B.

The term "and/or" is an associative relationship that describes an object, meaning that there may be three relationships. For example, a and/or B, represent: a or B, or, A and B.

The term "corresponding" may refer to an association or binding relationship, and the correspondence between a and B refers to an association or binding relationship between a and B.

It should be noted that, without conflict, the embodiments of the present disclosure and features of the embodiments may be combined with each other.

In order to facilitate understanding of the embodiments of the present disclosure, technical terms that may appear in the embodiments of the present disclosure are first explained below:

parity Check: is a method for checking the correctness of code transmission. The verification is performed based on whether the number of "1" s in the digits of the transmitted set of binary codes is odd or even. Odd parity is used, otherwise even parity. The type of check used is predefined. A parity bit is typically specially set, with which the number of "1" s in the set of codes is odd or even. If the odd check is used, when the receiving end receives the group of codes, checking whether the number of 1's is odd, thereby determining the correctness of the transmitted codes.

ECC (Error Checking and Correcting) checking: is to store a code encrypted with data on the extra bits of the data bits. When data is written into the memory, the corresponding ECC code is also saved. When the data just stored is read back again, the stored ECC code is compared with the ECC code generated when the data is read. If the two ECC check bits are not identical, an alarm is given. In addition, the ECC check also has error correction capability, and when the ECC check adopts an 'one correction and two detection' algorithm, the ECC check has the functions of alarming accumulation and correction for 1bit errors and alarming for 2bit errors; when ECC check adopts an algorithm of 'correcting two-check-three', the alarm accumulation and correction function is carried out on 1/2bit errors, and the alarm is carried out on 3bit errors.

MBIST (Memory build in self test, memory cell built-in self test) check: the test vector of the pointer to the memory cell is automatically generated by the built-in memory cell test logic, rather than by an external test machine. In MBIST verification, test results can be obtained from the output interface of the memory unit only by transmitting a test instruction to the memory unit. Comparing the test result with the input, and if the test result is consistent with the input, indicating that no fault exists; if not, a fault is indicated.

As shown in connection with fig. 1-3, embodiments of the present disclosure provide a fault detection circuit 10 for a memory cell. The failure detection circuit 10 of the memory cell includes: the first detection circuit 100, the second detection circuit 200 and the control module 300. The first detection circuit 100 is coupled to the memory cells for performing parity and/or ECC checking on the memory cells during the memory cell operation phase. The second detection unit is connected to the storage unit or the first detection circuit 100, and is configured to perform MBIST verification on the storage unit when there is a continuous error. The control unit is connected to the first detection circuit 100 and the second detection circuit 200, and is configured to control a communication relationship between the first detection circuit 100 and the second detection circuit 200 and the memory cell, receive the parity check result, the ECC check result, and the MBIST check result, and determine a failure area of the memory cell according to the parity check result, the ECC check result, and the MBIST check result.

Specifically, the memory cell is a volatile memory cell. Since volatile memory cells require frequent erasing and writing during use, the first detection circuit 100 is required to perform parity and/or ECC checking on the memory cells while the memory cells are in an operational phase.

Specifically, when the storage unit is in the operation stage, if the parity check and/or the ECC check have continuous error reporting, it indicates that multiple fault addresses exist in the storage unit, and at this time, all fault addresses in the storage unit cannot be accurately located by the parity check and/or the ECC check. Therefore, in this case, MBIST verification needs to be performed on the memory cells using the second detection circuit 200, so that the control module 300 accurately locates the failure area inside the memory cells according to the parity check result, the ECC check result, and the MBIST check result.

In the embodiment of the disclosure, during the operation phase of the memory cell, the first detection circuit 100 performs parity check and/or ECC check on the memory cell, and if a continuous error reporting condition occurs, the second detection circuit 200 is connected to perform MBIST check on the memory cell. The initial address bit with faults in the storage unit can be analyzed and determined according to the parity check result and/or the ECC check result, and the number of the address bits with faults in the storage unit can be analyzed and determined according to the MBIST check result. Therefore, when the continuous fault reporting condition exists, the embodiment of the disclosure can analyze and locate multiple fault addresses in the volatile storage unit, and determine the fault area in the storage unit. Therefore, when the storage unit is used later, the data can be prevented from being read and written in the fault area, and the reliability of the application of the storage unit is improved.

In addition, since MBIST verification is a scan verification of all address bits in a memory cell, embodiments of the present disclosure can detect a failed address that cannot be detected by multiple bits.

As shown in fig. 2, in some embodiments, the first detection circuit 100 includes: parity check circuit 110 and/or ECC check circuit 120. The parity check circuit 110 is connected to the memory cell for performing parity check on the memory cell. The ECC check circuit 120 is connected to the memory cell and is used for performing ECC check on the memory cell.

Specifically, the first detection circuit 100 may include only the parity check circuit 110, may include only the ECC check circuit 120, and may include both the parity check circuit 110 and the ECC check circuit 120.

Specifically, in the case where the first detection circuit 100 includes the parity check circuit 110 and the ECC check circuit 120, the parity check circuit 110 and the ECC check circuit 120 are both connected to the control module 300, and the control module 300 can control whether to perform parity check or ECC check on the memory cells by controlling the communication relationship between the parity check circuit 110 and the ECC check circuit 120 and the memory cells.

In the embodiment of the present disclosure, the first detection circuit 100 is provided with the parity check circuit 110 and/or the ECC check circuit 120, and the control module 300 may control whether to perform parity check or ECC check on the storage unit by controlling the connection relationship between the parity check circuit 110 and the ECC check circuit 120 and the storage unit, so that a user may select a fault detection mode of the operation stage of the storage unit according to the requirement, thereby improving the flexibility of performing fault detection on the storage unit.

As shown in fig. 3, in some embodiments, the parity check circuit 110 includes: a first generation circuit 111, a first verification circuit 112, and a first gate circuit 113; the input end of the first generation circuit 111 is connected with the control module 300 through the first gate circuit 113, and the output end is connected with the input end of the storage unit; the input end of the first checking circuit 112 is connected with the output end of the storage unit, and the output end is connected with the control module 300; the first generation circuit 111 is configured to generate a first input check code, and perform parity check on the storage unit based on the first input check code; the first check circuit 112 is configured to receive a first output check code generated after checking the memory cell, and compare the first input check code with the first output check code to determine a parity check result.

Specifically, when the memory cells are parity checked by the parity check circuit 110, the first generation circuit 111 generates a first input check code and then performs a read operation with respect to the memory areas of the memory cells. After reading, the first check circuit 112 may obtain the first output check code, and may compare the first input check code with the first output check code. If the results are consistent, the storage unit is proved to have no fault address. If the results are inconsistent, it is proved that the memory unit has a faulty address, in which case an alarm signal can be issued.

Optionally, gates may also be provided at the input of the first verification circuitry 112 and the output of the memory cell, so that the first verification circuitry 112 may be disabled when parity is not being performed.

As shown in fig. 3, in some embodiments, ECC check circuit 120 includes: a second generation circuit 121, a second verification circuit 122, and a second gate circuit 123; the input end of the second generating circuit 121 is connected with the control module 300 through the second gate circuit 123, and the output end is connected with the input end of the storage unit; the input end of the second checking circuit 122 is connected with the output end of the storage unit, and the output end is connected with the control module 300; the second generating circuit 121 is configured to generate a second input check code, and check the memory cell based on the second input check code; the second checking circuit 122 is configured to receive a second output check code generated after checking the memory cell, and compare the second input check code with the second output check code to determine an ECC check result.

Specifically, when the memory cell is subjected to ECC verification by the ECC verification circuit 120, the second generation circuit 121 generates a second input verification code and then reads and writes an address or data for a memory area of the memory cell. After reading and writing the address or data, the second check circuit 122 may obtain the second output check code, and may compare the second input check code with the second output check code. When the ECC check circuit 120 adopts the algorithm of "correcting one check two", the alarm accumulation and correction function is performed for 1bit errors, and the alarm is directly performed for 2bit errors, so as to send an alarm signal. When the ECC check circuit 120 adopts the algorithm of 'correcting two-check-three', the function of alarming accumulation and correction is carried out on 1/2bit errors, and the function of directly alarming is carried out on 3bit errors, so that an alarm signal is sent.

Optionally, gates may also be provided at the input of the second verification circuitry 122 and the output of the memory cells, so that the second verification circuitry 122 may be disabled when no ECC verification is performed.

As shown in fig. 3, in some embodiments, the second generation circuit 121 is connected to the first generation circuit 111, and the second verification circuit 122 is connected to the first verification circuit 112. The second detection circuit 200 includes: MBIST verification circuitry 201, third gate circuitry 202, and fourth gate circuitry 203. The MBIST verification circuit 201 has a first input terminal connected to the control module 300, a second input terminal connected to the output terminal of the second verification circuit 122 through the third gate circuit 202, and an output terminal connected to the second generation circuit 121 through the fourth gate circuit 203.

Specifically, by connecting the second generation circuit 121 to the first generation circuit 111, connecting the second verification circuit 122 to the first verification circuit 112, connecting the second input terminal of the MBIST verification circuit 201 to the output terminal of the second verification circuit 122 through the third gate circuit 202, and connecting the output terminal of the MBIST verification circuit 201 to the second generation circuit 121 through the fourth gate circuit 203. The memory cells may be subjected to parity check and ECC check at the same time as the memory cells are subjected to MBIST check by the connected MBIST check circuit 201. Therefore, the failure area in the storage unit can be judged by integrating the MBIST check result, the parity check result and the ECC check result which are obtained by one-time detection, and the accuracy of analyzing and positioning a plurality of failure addresses is improved.

As shown in fig. 3, in some embodiments, the fault detection circuit 10 of the memory cell further includes: the alarm circuit 400 is connected to the output end of the first detection circuit 100, and is configured to output an alarm signal according to the parity check result and/or the ECC check result.

Specifically, in the case where the first detection circuit 100 includes the parity check circuit 110 and the ECC check circuit 120, the alarm circuit 400 employs an or gate control circuit, and connects the parity check circuit 110 and the ECC check circuit 120 to two input terminals of the or gate control circuit, respectively. Thus, the alarm circuit 400 may issue an alarm signal whenever either one of the parity check result and the ECC check result is alarmed.

As shown in fig. 3, in some embodiments, the fault detection circuit 10 of the memory cell further includes: the recording module 500 is connected to the control module 300 and the output terminal of the first detection circuit 100, and is configured to record the failure address in the storage unit according to the parity check result and/or the ECC check result.

Specifically, by providing the recording module 500 between the control module 300 and the output terminal of the first detection circuit 100, the fault address detected by the parity check and/or the ECC check can be recorded in time, and when the fault area determination is performed, the control module 300 can determine the fault address detected by the parity check and/or the ECC check by looking at the recording module 500. In this way, the control module 300 is not required to receive and store parity and/or ECC check detection data, reducing the workload of the control module 300.

In connection with the fault detection circuit of the storage unit shown in fig. 1 to 3, the embodiment of the disclosure provides a fault detection method of the storage unit, an execution body of the fault detection method may be a control module in the fault detection circuit, as shown in fig. 4, and the fault detection method includes:

s401, the control module is communicated with the first detection circuit in the operation stage of the storage unit, and performs parity check and/or ECC check on the storage unit.

Specifically, the memory cell is a volatile memory cell.

In particular, volatile memory cells require frequent erasing and writing during use. Thus, when the memory cell is in the run phase, the first detection circuit needs to be connected to perform parity check and/or ECC check on the memory cell.

And S402, the control module is communicated with a second detection circuit under the condition of continuous error reporting, and performs MBIST verification on the storage unit.

Specifically, when the storage unit is in the operation stage, if the parity check and/or the ECC check have continuous error reporting, the storage unit is indicated to have multiple fault addresses. At this time, the parity check and/or ECC check mode cannot accurately locate all the failed addresses in the memory cells. Therefore, in this case, MBIST verification needs to be performed on the memory cell by using the second detection circuit, so that the control module accurately locates the failure area inside the memory cell according to the parity check result, the ECC check result, and the MBIST check result.

S403, the control module determines a fault area in the storage unit according to the MBIST check result, the ECC check result and the parity check result.

Specifically, the starting address bit with a fault and the number of address bits with a fault in the storage unit can be analyzed and determined according to the parity check result, the ECC check result and the MBIST check result. Therefore, the control module can determine the fault area inside the storage unit according to the MBIST check result, the ECC check result and the parity check result.

Optionally, determining the failure area inside the storage unit according to the MBIST check result, the ECC check result and the parity check result includes: determining a starting address bit with faults in the storage unit according to the parity check result and/or the ECC check result; confirming the number of address bits with faults in the storage unit according to the MBIST verification result; and determining a fault area in the storage unit according to the initial address bit and the address bit number.

In the embodiment of the disclosure, during the operation stage of the storage unit, the first detection circuit is used for performing parity check and/or ECC check on the storage unit, and if continuous error reporting occurs, the second detection circuit is communicated for performing MBIST check on the storage unit. The initial address bit with faults in the storage unit can be analyzed and determined according to the parity check result and/or the ECC check result, and the number of the address bits with faults in the storage unit can be analyzed and determined according to the MBIST check result. Therefore, when the continuous fault reporting condition exists, the embodiment of the disclosure can analyze and locate multiple fault addresses in the volatile storage unit, and determine the fault area in the storage unit. Therefore, when the storage unit is used later, the data can be prevented from being read and written in the fault area, and the reliability of the application of the storage unit is improved.

In some embodiments, the method for detecting a failure of a storage unit further includes: and in the power-on stage of the memory cell, a second detection circuit is communicated, and MBIST verification is carried out on the memory cell.

In the embodiment of the disclosure, in the power-up stage of the memory cell, an MBIST check is performed on the memory cell once. Therefore, the operation of the storage unit with a plurality of fault addresses can be avoided, and the working reliability of the storage unit is improved.

In some embodiments, the control module 300, as shown in fig. 5, packs: a processor (processor) 301 and a memory (memory) 302. Optionally, the control module 300 may also include a communication interface (Communication Interface) 303 and a bus 304. The processor 301, the communication interface 303, and the memory 302 may communicate with each other via the bus 304. The communication interface 303 may be used for information transfer. The processor 301 may call logic instructions in the memory 302 to perform the fault detection method of the memory cell of the above-described embodiment.

Further, the logic instructions in memory 302 described above may be implemented in the form of software functional units and stored in a computer readable storage medium when sold or used as a stand alone product.

The memory 302 serves as a computer readable storage medium, and may be used to store a software program, a computer executable program, and program instructions/modules corresponding to the methods in the embodiments of the present disclosure. The processor 301 executes the functional applications and data processing by executing the program instructions/modules stored in the memory 302, i.e., implements the failure detection method of the memory unit in the above-described embodiment.

Memory 302 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, at least one application program required for functionality; the storage data area may store data created according to the use of the terminal device, etc. In addition, memory 302 may include high-speed random access memory, and may also include non-memory.

As shown in connection with fig. 6, an embodiment of the present disclosure provides a functional chip 600, including: the chip body 610, the memory cell 620, and the failure detection circuit 10 of the memory cell described above. The memory unit 620 is mounted to the chip body 110. The failure detection circuit 10 of the memory cell is connected to the memory cell 620. The mounting relationships described herein are not limited to placement within the functional chip 600, but include mounting connections to other components of the functional chip 600, including but not limited to physical, electrical, or signal transmission connections, etc. Those skilled in the art will appreciate that the failure detection circuit of the memory cell may be adapted to a viable functional chip 600 to implement other viable embodiments.

Embodiments of the present disclosure provide a computer-readable storage medium storing computer-executable instructions configured to perform the fault detection method of the above-described storage unit.

The above description and the drawings illustrate embodiments of the disclosure sufficiently to enable those skilled in the art to practice them. Other embodiments may involve structural, logical, electrical, process, and other changes. The embodiments represent only possible variations. Individual components and functions are optional unless explicitly required, and the sequence of operations may vary. Portions and features of some embodiments may be included in, or substituted for, those of others. Moreover, the terminology used in the present application is for the purpose of describing embodiments only and is not intended to limit the claims. As used in the description of the embodiments and the claims, the singular forms "a," "an," and "the" (the) are intended to include the plural forms as well, unless the context clearly indicates otherwise. Similarly, the term "and/or" as used in this application is meant to encompass any and all possible combinations of one or more of the associated listed. Furthermore, when used in this application, the terms "comprises," "comprising," and/or "includes," and variations thereof, mean that the stated features, integers, steps, operations, elements, and/or components are present, but that the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof is not precluded. Without further limitation, an element defined by the phrase "comprising one …" does not exclude the presence of other like elements in a process, method or apparatus comprising such elements. In this context, each embodiment may be described with emphasis on the differences from the other embodiments, and the same similar parts between the various embodiments may be referred to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method sections disclosed in the embodiments, the description of the method sections may be referred to for relevance.

Those of skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. The skilled artisan may use different methods for each particular application to achieve the described functionality, but such implementation should not be considered to be beyond the scope of the embodiments of the present disclosure. It will be clearly understood by those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, which are not repeated herein.

In the embodiments disclosed herein, the disclosed methods, articles of manufacture (including but not limited to devices, apparatuses, etc.) may be practiced in other ways. For example, the apparatus embodiments described above are merely illustrative, and for example, the division of the units may be merely a logical function division, and there may be additional divisions when actually implemented, for example, multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed. In addition, the coupling or direct coupling or communication connection shown or discussed with each other may be through some interface, device or unit indirect coupling or communication connection, which may be in electrical, mechanical or other form. The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to implement the present embodiment. In addition, each functional unit in the embodiments of the present disclosure may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). In some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. In the description corresponding to the flowcharts and block diagrams in the figures, operations or steps corresponding to different blocks may also occur in different orders than that disclosed in the description, and sometimes no specific order exists between different operations or steps. For example, two consecutive operations or steps may actually be performed substantially in parallel, they may sometimes be performed in reverse order, which may be dependent on the functions involved. Each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.

Claims (10)

1. A fault detection circuit of a memory cell, comprising:

the first detection circuit is connected with the storage unit and is used for performing parity check and/or ECC check on the storage unit in the operation stage of the storage unit;

the second detection circuit is connected with the storage unit or the first detection circuit and is used for performing MBIST verification on the storage unit under the condition that continuous error reporting exists;

the control module is connected with the first detection circuit and the second detection circuit and used for controlling the communication relation between the first detection circuit and the second detection circuit and the storage unit, receiving the parity check result, the ECC check result and the MBIST check result and determining the fault area of the storage unit according to the parity check result, the ECC check result and the MBIST check result.

2. The fault detection circuit of claim 1, wherein the first detection circuit comprises:

the parity check circuit is connected with the storage unit and used for performing parity check on the storage unit;

and/or the number of the groups of groups,

and the ECC check circuit is connected with the storage unit and used for carrying out ECC check on the storage unit.

3. The fault detection circuit of claim 2, wherein,

the parity check circuit includes: the first generation circuit, the first verification circuit and the first gate circuit; the input end of the first generating circuit is connected with the control module through the first gate circuit, and the output end of the first generating circuit is connected with the input end of the storage unit; the input end of the first verification circuit is connected with the output end of the storage unit, and the output end of the first verification circuit is connected with the control module;

the first generation circuit is used for generating a first input check code and checking the storage unit based on the first input check code;

the first check circuit is used for receiving a first output check code generated after the storage unit is checked, and comparing the first input check code with the first output check code to determine a parity check result;

the ECC check circuit includes: a second generation circuit, a second check circuit, and a second gate circuit; the input end of the second generating circuit is connected with the control module through the second gate circuit, and the output end of the second generating circuit is connected with the input end of the storage unit; the input end of the second checking circuit is connected with the output end of the storage unit, and the output end of the second checking circuit is connected with the control module;

the second generation circuit is used for generating a second input check code and checking the storage unit based on the second input check code;

the second checking circuit is used for receiving a second output check code generated after checking the storage unit, and comparing the second input check code with the second output check code to determine an ECC check result.

4. The fault detection circuit of claim 3, wherein the second generation circuit is coupled to the first generation circuit and the second verification circuit is coupled to the first verification circuit;

the second detection circuit includes: MBIST verification circuitry, third gate circuitry, and fourth gate circuitry; the first input end of the MBIST checking circuit is connected with the control module, the second input end of the MBIST checking circuit is connected with the output end of the second checking circuit through the third gate circuit, and the output end of the MBIST checking circuit is connected with the second generating circuit through the fourth gate circuit.

5. The fault detection circuit of any one of claims 1 to 4, further comprising:

and the alarm circuit is connected with the output end of the first detection circuit and is used for outputting alarm signals according to the parity check result and/or the ECC check result.

6. The fault detection circuit of any one of claims 1 to 4, further comprising:

the recording module is connected with the control module and the output end of the first detection circuit and is used for recording the fault address in the storage unit according to the parity check result and/or the ECC check result.

7. A failure detection method of a memory cell, applied to the failure detection circuit of a memory cell according to any one of claims 1 to 6, comprising:

in the operation stage of the storage unit, a first detection circuit is communicated, and parity check and/or ECC check is carried out on the storage unit;

under the condition of continuous error reporting, a second detection circuit is communicated, and MBIST verification is carried out on the storage unit;

and determining a fault area in the storage unit according to the MBIST check result, the ECC check result and the parity check result.

8. The fault detection method of claim 7, wherein determining the fault region within the memory cell based on MBIST, ECC, and parity results comprises:

determining a starting address bit with faults in the storage unit according to the parity check result and/or the ECC check result;

confirming the number of address bits with faults in the storage unit according to the MBIST verification result;

and determining a fault area in the storage unit according to the initial address bit and the address bit number.

9. The fault detection method according to claim 7 or 8, characterized by further comprising:

and in the power-on stage of the memory cell, a second detection circuit is communicated, and MBIST verification is carried out on the memory cell.

10. A functional chip, comprising:

a chip body;

a memory unit mounted on the chip body;

the failure detection circuit of a memory cell according to any one of claims 1 to 7, connected to the memory cell, and mounted on a chip body.