CN114461476A

CN114461476A - Memory bank fault detection method, device and system

Info

Publication number: CN114461476A
Application number: CN202210134713.1A
Authority: CN
Inventors: 刘辉; 刘俊
Original assignee: Shenzhen Yuanchuang Storage Technology Co ltd
Current assignee: Shenzhen Yuanchuang Storage Technology Co ltd
Priority date: 2022-02-14
Filing date: 2022-02-14
Publication date: 2022-05-10
Anticipated expiration: 2042-02-14
Also published as: CN114461476B

Abstract

The invention provides a method, a device and a system for detecting faults of a memory bank, wherein the method comprises the following steps: arranging a memory bank fault detection device, and connecting the detection device with memory bank installation equipment to construct a memory bank monitoring channel; grading the integrated fragments of the memory chip through the memory monitoring channel to obtain grade fragments; address calibration is carried out on bit storage grids in the level fragments, numbering and sequencing are carried out on the level fragments and the bit storage grids, and a numbering result is obtained; according to the numbering result, whether the information processing work of the memory bank numbering address is normal or not is judged, the judgment result is obtained, and the abnormal result is subjected to alarm display.

Description

Memory bank fault detection method, device and system

Technical Field

The invention relates to the technical field of memory bank detection, in particular to a memory bank fault detection method, device and system.

Background

At present, with the continuous development of the integrated circuit manufacturing process and the gradual reduction of the semiconductor size, the density of the memory is getting higher, especially with the rapid increase of the complexity of the memory bank, the probability of the failure of the memory bank is getting higher, the types of the failure are getting more, the detection of the failure of the memory bank is getting more and more complex, the detection time is getting longer, and the detection cost is getting higher, in addition, most of the memory bank detection technologies are the detection of the failure of the external structures such as the memory bank installation connection, and the detection technology is too monotonous, for example, CN 2015104719-a detection device and method for rapidly positioning the failed memory bank, the memory failure code table is established according to the condition of the server motherboard, and a BIOS platelet is externally connected to the server motherboard, the memory failure detection is performed in the PEI memory self-test stage of the server motherboard code, the fault memory code is displayed through the nixie tube small plate, and then the code displayed by the nixie tube small plate is compared with the memory fault code table to detect the memory bank fault.

Disclosure of Invention

The invention provides a method, a device and a system for detecting faults of a memory bank, which are used for solving the problems, and the invention realizes the detection of the internal faults by carrying out grade division and address calibration on integrated fragments and bit storage grids inside the memory bank by constructing a memory bank monitoring channel, can carry out quick alarm display on a detection result, saves the detection time and avoids the loss of memory bank information caused by inaccurate fault detection and other reasons.

1. A memory bank fault detection method comprises the following steps:

arranging a memory bank fault detection device, and connecting the detection device with memory bank installation equipment to construct a memory bank monitoring channel;

grading the integrated fragments of the memory chip through the memory monitoring channel to obtain grade fragments;

address calibration is carried out on bit storage grids in the level fragments, numbering and sequencing are carried out on the level fragments and the bit storage grids, and a numbering result is obtained;

and judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, acquiring a judgment result, and carrying out alarm display on an abnormal result.

As an embodiment of the present invention: set up DRAM fault detection device to be connected detection device and DRAM erection equipment, construct DRAM monitoring channel, include:

connecting the set memory bank fault monitoring device with the memory bank mounting equipment, and performing primary fault prejudgment according to fault display of the memory bank mounting equipment to obtain a prejudgment result;

wherein, the prejudgment result comprises: a memory bank mechanical failure and a memory bank storage failure;

when the pre-judgment result shows that the memory bank is in a mechanical fault, fault feedback is carried out, and a detector carries out fault processing according to the fault feedback;

when the pre-judgment result shows that the memory bank storage fault exists, a memory bank channel monitoring mechanism is formulated, and a chip separation route in the memory bank is determined according to the memory bank channel monitoring mechanism through a memory bank detection device;

and determining an N-bit routing inspection route based on the chip separation route, and constructing a memory bank monitoring channel according to the N-bit routing inspection route.

As an embodiment of the present invention: when the prejudgment result shows that the memory bank storage fault occurs, a memory bank channel monitoring mechanism is formulated, and a memory bank monitoring channel is constructed through a memory bank detection device according to the memory bank channel monitoring mechanism, wherein the prejudgment result comprises the following steps:

performing data analysis on the memory bank technical index data displayed by the memory bank detection device according to a preset storage threshold value of the memory bank chip, and formulating a memory bank channel monitoring mechanism;

wherein, the memory bank channel monitoring mechanism comprises:

determining the number information lines of storage routes of the memory chips and the integrated chip fragments to generate chip separation routes;

the number information of the chip separation routes is represented by N bits, and N bit routing inspection routes are obtained;

recording memory information transmission time and information processing time of each routing inspection route based on the N-bit routing inspection routes, and performing equal-time section division on the memory information transmission time and the information processing time to obtain section time;

according to the section time, performing system sampling to obtain a section time sample, and performing data comparison on the section time sample with preset information transmission time and preset information processing time to obtain time difference value data;

monitoring whether the difference data is within a preset time error threshold value or not to obtain a monitoring result;

and on the basis of the monitoring result, when the difference data is not in a preset time error threshold value, carrying out fault detection on the route memory bank according to the N-bit routing inspection route.

As an embodiment of the present invention: through the memory bank monitoring channel, carry out grade division to the integrated burst of memory bank chip, obtain the grade burst, include:

acquiring fragmentation grade data according to a chip through the memory bank monitoring channel;

extracting information processing parameters of the chip fragments based on the fragment grade data, and performing fragment grade division according to the information processing parameters to obtain grade fragments;

dividing the chip integration fragments into three levels, wherein the three levels comprise: first-level slicing, second-level slicing and third-level slicing.

As an embodiment of the present invention: address calibration is carried out on bit storage lattices in the level fragments, numbering and sequencing are carried out on the level fragments and the bit storage lattices, and a numbering result is obtained, wherein the address calibration comprises the following steps:

performing address calibration on a bit storage grid in the level fragment, and executing memory addressing, wherein the address calibration comprises: calibrating a row address and a column address;

performing primary check detection on the storage grid data through a preset check code of the storage grid to obtain a primary detection result;

analyzing results based on the primary detection result, extracting checking error information, performing information exception classification storage management on the checking error information, and acquiring exception classification information;

sending the abnormal classification information to a memory bank fault detection device through a memory bank monitoring channel;

carrying out information marking indexing on the abnormal classification information, and numbering according to a, b and c to generate an index catalog;

numbering the bit storage grids according to 1, 2, 3,. to obtain numbered bit storage grids;

correspondingly matching the index directory with the number bit storage grid, and numbering according to 1-a/b/c, 2-a/b/c, 3-a/b/c.;

and storing the numbering sequence information of the numbering chip to obtain a numbering result.

As an embodiment of the present invention: performing address calibration on a bit storage grid in the level fragment, and executing memory addressing, wherein the address calibration comprises: the row address calibration and the column address calibration comprise the following steps:

the steps for performing memory addressing are as follows:

the method comprises the following steps: performing address calibration on a bit storage grid in the level fragment, wherein the address calibration comprises: calibrating a row address and a column address;

step two: recording the row address in a vertical coordinate signal, recording the column address in an abscissa signal, and acquiring horizontal and vertical coordinate signal information;

step three: based on the horizontal and vertical coordinate signal information, the memory bank fault detection device searches signal information through a memory bank monitoring channel, and locks address information through the signal information search;

step four: and performing address interpretation according to the address information, and determining whether the address information is a calibration address based on the address interpretation.

As an embodiment of the present invention: the judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, obtaining the judging result and carrying out alarm display on the abnormal result comprises the following steps:

judging whether the information corresponding to the serial number works normally or not according to the serial number result to obtain a judgment result;

based on the judgment result, when the judgment result shows that the information storage time of the memory bank is abnormal, the voice alarm prompt for the abnormal information storage time is carried out through a memory bank fault detection device;

based on the judgment result, when the judgment result shows that the processing of the address information of the memory cell is abnormal, the memory cell fault detection device is used for carrying out voice alarm prompt on the abnormal address information of the memory cell;

based on the judgment result, when the judgment result shows that the information corresponding to the grading fragment number is abnormal, a voice alarm prompt for abnormal information corresponding to the number is carried out through a memory fault detection device;

and formulating a corresponding alarm processing scheme through different voice alarm prompts.

As an embodiment of the present invention: through different voice alarm prompts, formulate and correspond to report an emergency and ask for help or increased vigilance processing scheme, include:

according to the abnormal voice alarm prompt of the information storage time, a system operation repairing and reading speed changing scheme is formulated;

according to the abnormal voice alarm prompt of the address information of the memory grid, an insertion sequence scheme for adjusting the memory banks in the installation equipment is formulated;

and formulating a scheme for detecting the integrity of the serial number and re-matching the serial number information according to the abnormal voice alarm prompt of the information corresponding to the serial number.

As an embodiment of the present invention: the method comprises the following steps: the device comprises a data line, a display screen, a detection host and an alarm;

the display screen is embedded in the detection host, and the detection host is connected with the alarm and the memory bank installation equipment through data lines;

the alarm receives the abnormal detection data sent by the detection host through a data line and executes abnormal data alarm operation;

the detection host further comprises: and the channel monitor monitors the channel condition of the memory bank through connection.

As an embodiment of the present invention: the method comprises the following steps:

a channel building module: the device is used for setting a memory bank fault detection device, connecting the detection device with memory bank installation equipment and constructing a memory bank monitoring channel;

a fragment acquisition module: grading the integrated fragments of the memory chip through the memory monitoring channel to obtain grade fragments;

a numbering and sequencing module: address calibration is carried out on bit position storage grids in the grade fragments, numbering and sequencing are carried out on the grade fragments and the bit position storage grids, and numbering results are obtained

A judgment warning module: and judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, acquiring a judgment result, and performing alarm display on an abnormal result.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by the practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and drawings.

The technical solution of the present invention is further described in detail by the accompanying drawings and embodiments.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the principles of the invention and not to limit the invention. In the drawings:

FIG. 1 is a flow chart of a method for detecting a memory bank fault according to an embodiment of the present invention;

FIG. 2 is a diagram of a memory bank failure detection apparatus according to an embodiment of the present invention;

fig. 3 is a block diagram of a system for detecting a memory bank fault according to an embodiment of the present invention.

Detailed Description

The preferred embodiments of the present invention will be described in conjunction with the accompanying drawings, and it will be understood that they are described herein for the purpose of illustration and explanation and not limitation.

Example 1:

the embodiment of the invention provides a memory bank fault detection method, which comprises the following steps:

judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, acquiring a judgment result, and carrying out alarm display on an abnormal result;

in one practical scenario: the detection of the fault of the memory bank is mainly to detect the installation and the insertion of the memory bank, and the detection system has the advantages that the detection of the fault of the memory bank is too simple, the specific position of the internal information processing and storage of the memory bank cannot be detected, and the fault of the memory bank caused by the overlong time of the information processing in the memory bank cannot be detected;

when the invention is implemented: firstly, connecting a memory bank fault device with memory bank installation equipment, monitoring chip fragments and bit storage grids in a memory bank through a built memory bank monitoring channel, judging whether the chip fragments and the bit storage grids are normal according to the monitored information condition, and displaying the fault position and the fault reason of the memory bank through alarming so as to finish the detection of the memory bank fault;

the beneficial effects of the above technical scheme are: the memory bank fault detection device has the advantages that the memory bank monitoring channel is constructed and the memory bank chip is subjected to hierarchical processing, the integrated fragments of the memory bank chip can be rapidly subjected to working conditions of the monitoring fragments through hierarchical division, the bit storage grid is the position for storing processing information and is subjected to address calibration, the calibrated address can be accurately positioned through the memory bank monitoring channel, and the specific position of information storage faults in the memory bank is alarmed and displayed through the memory bank fault detection device.

Example 2:

in one embodiment, the setting a memory bank fault detection device, and connecting the detection device with a memory bank installation device to construct a memory bank monitoring channel includes:

determining an N-bit routing inspection route based on the chip separation route, and constructing a memory bank monitoring channel according to the N-bit routing inspection route;

in one practical scenario: when fault detection is needed for internal storage problems of a memory bank, the storage condition and the information storage path inside the memory bank need to be clear, but a memory bank monitoring path in the prior art is lacked, and when the fault problem of the memory bank is detected in the prior art, a method for constructing a memory bank monitoring channel is not mentioned, so that the fault detection of the memory bank is not comprehensive enough, and the detection position and the fault reason of the fault cannot be accurately known;

when the invention is implemented: firstly, primary judgment is carried out on the fault display through a memory bank fault detection device, the judgment result is divided into a memory bank mechanical fault and a memory bank storage fault, the memory bank mechanical fault can be detected by checking the installation and poor contact of the memory bank, the memory bank chip and integrated fragments thereof are divided and divided by constructing a memory bank monitoring channel for the memory bank storage fault, an information transmission processing route is determined, and the specific detection on the memory bank storage fault problem can be completed according to the generated N-bit routing inspection route;

the beneficial effects of the above technical scheme are: through constructing the memory bank monitoring channel, the information processing conditions in different routing inspection routes in the memory bank can be monitored through the channel, the chips on the memory bank are separated, the storage conditions on each route which can be organized can be monitored through the separation, the monitoring method is more convenient, the condition that the information stored on the memory bank chip is overlapped in monitoring is avoided, too much monitoring work is reduced, and the fault detection of the memory bank is more efficient.

Example 3:

in one embodiment, N bits represent the number information of chip separation routes to obtain N bits of routing inspection routes, and anomaly detection is performed according to the obtained routing inspection routes, so that the coordinates of information in the routes need to be determined for information detection in the routes, and the information coordinates are calculated according to the following formula:

wherein,

and

the horizontal and vertical coordinates of the starting point of the information in the transmission process are represented;

and

the horizontal and vertical coordinates of the information at the transmission end point are represented;

is shown in the routing inspection route

The azimuth angle at the point;

is shown in the total path length

Integrating cosine values of the azimuth angles;

is shown in the total path length

Above, the cosine value of the azimuth is integrated.

The sine integral and the cosine integral of the azimuth angle are calculated by considering the corner curve in the routing inspection route, so that coordinate deviation exists, and the deviation of the azimuth angle can be eliminated through integral calculation;

for the azimuth angle

The calculation method of (a) is as follows:

wherein

Representing an initial azimuth;

and

and the curvature of the starting point and the ending point of the curve element in the routing inspection route is shown.

Through the calculation, the coordinates of information transmission can be obtained, so that the fault information can be quickly positioned through the coordinates;

the working principle of the technical scheme is as follows: for the routing inspection route separated from the memory chip, the coordinate position of the information in the route can be determined, and when the coordinate calculation is carried out, the coordinate position is firstly set

And

the horizontal and vertical coordinates of the information at the transmission end point are shown, and then

And

and (3) calculating:

(ii) a When calculating the horizontal and vertical coordinates, the determination is needed first

And

horizontal and vertical coordinates and azimuth angles of starting point of information in transmission process

Integral calculation is carried out for azimuth

Can be calculated by

Calculating to obtain coordinate values, and determining the position according to the coordinate information;

the beneficial effects of the above technical scheme are: the information position can be rapidly determined by calculating the coordinates, so that the fault position point can be accurately found, the fault detection time of the memory bank is saved, and the loss is reduced.

Example 4:

in one embodiment, when the predetermined result shows that the memory bank storage fails, a memory bank channel monitoring mechanism is formulated, and a memory bank monitoring channel is constructed by a memory bank detection device according to the memory bank channel monitoring mechanism, including:

wherein, the memory bank channel monitoring mechanism comprises:

on the basis of the monitoring result, when the difference data is not within a preset time error threshold value, performing route memory bank fault detection according to the N-bit routing inspection route;

in one practical scenario: the method for recording the time of operations such as storage processing of information in the memory bank is not available, so that whether the processing time of the information in the memory bank is reasonable and normal cannot be determined, and the prior art also does not mention the technology for establishing a memory bank channel monitoring mechanism;

when the invention is implemented: a memory bank channel monitoring mechanism is formulated, and the internal faults of the memory bank can be systematically monitored through the formulated monitoring mechanism, wherein the recorded time is divided into equal time intervals so as to perform systematic sampling on time information in a large number of time periods, so that the primary detection and judgment on the problem of whether the memory bank has information processing faults or not can be rapidly performed;

the beneficial effects of the above technical scheme are: through formulating the memory bank channel monitoring mechanism, can be according to the monitoring mechanism of formulating can be reasonable monitor the storage trouble of memory bank to carry out the record to the time of information transmission and information processing's time in each route, then carry out the scope to the time of record and predetermine the time error threshold value and compare, can go on preliminary judgement to the memory bank whether break down, consequently can save the time to memory bank fault detection.

Example 5:

in one embodiment, based on N-bit routing inspection routes, memory information transmission time and information processing time of each routing inspection route are recorded, equal-time segment division is carried out on the memory information transmission time and the information processing time, N segment times are obtained, and the total memory information transmission time arranged on one routing inspection route is equal to the total memory information transmission time

Will transmit the total time to

Time is divided into equal time intervals, and the divided time is used for the time of the section

N denotes 1, 2, 3.. cndot,

systematic sampling is performed for the segment time by the following equation:

wherein,

is shown as

Decimated block time samples;

representing a first segment time;

then the divided section time is processed from the first section time by the formula

Sampling is carried out until the extraction of n sections is finished;

then will be

And preset information transmission time

Comparing to obtain difference data

(ii) a Judging and monitoring whether the obtained difference data is within a preset time error threshold value or not

Represents the monitoring results:

wherein,

representing a preset time error threshold.

The working principle of the technical scheme is as follows: the technology divides the memory information transmission time into equal-time sections to obtainTaking n sections of time, setting the total time of memory information transmission on a routing inspection route as

Will transmit the total time to

N denotes according to 1, 2, 3.

System sampling is carried out, then the system is passed again and then the system sampling is carried out

And preset information transmission time

Comparing to obtain difference data

(ii) a Whether the obtained difference data are judged and monitored within a preset time error threshold value or not is judged, and the monitoring result judgment mode is as follows:

when the result shows that the fault is abnormal, carrying out abnormal fault warning prompt through the memory bank monitoring channel, and when the result shows that the fault is normal, continuing to detect;

the beneficial effects of the above technical scheme are: the section time is sampled to obtain a section time sample, so that the detection time can be saved, then the sample is subjected to data comparison, preliminary difference data can be obtained more adequately, the judgment can be performed rapidly according to the difference data, and the monitoring efficiency is higher through threshold judgment.

Example 6:

in an embodiment, the performing, through the memory bank monitoring channel, rank division on the integrated fragments of the memory bank chip to obtain the rank fragments includes:

dividing the chip integration fragments into three levels, wherein the three levels comprise: first-level slicing, second-level slicing and third-level slicing;

in one practical scenario: the integrated fragments of the memory chip are not classified, so that information management cannot be performed on the classified fragments, and when a fault occurs during information storage of the fragments, the fault finding is complicated due to lack of classification and classification of the fragments, and a fault detection error condition is generated;

the invention is implemented as follows: the integrated fragments of the chip are classified into grades, the integrated fragments are classified according to the processing effect of the fragments on information, the information management of the fragments can be determined through the classification, and the abnormal information can be searched according to the corresponding classification of the classification for the abnormal problem of any information, so that the detection on the faults of the memory bank can be more accurate, and the detection time can be saved;

the beneficial effects of the above technical scheme are: according to the constructed memory bank monitoring channel, the integrated fragments of the chip are graded, the fragments are mainly graded into three grades according to the function of the fragments, and the three grades are respectively classified into the three grades according to the characteristics of the fragments, so that the memory bank information processed by the fragments can be classified, and the information processing and analyzing efficiency is improved.

Example 7:

in one embodiment, address calibration is performed on bit storage cells in the level fragments, and numbering and sorting are performed on the level fragments and the bit storage cells to obtain a numbering result, including:

performing address calibration on a bit storage grid in the level fragment to determine memory addressing, wherein the address calibration comprises: calibrating a row address and a column address;

storing the information of the numbering sequence of the numbering chip to obtain a numbering result;

in one practical scenario: the integrated fragments in the memory chip are not finely divided, and the bit storage grids are not numbered and sequenced, so that the internal storage faults of the memory chip cannot be accurately detected due to the lack of the technology;

when the invention is implemented: firstly, address calibration is carried out on the bit storage grids of the fragments, abnormal information of the storage grids in the memory bank can be searched according to the calibrated addresses, the information is firstly detected and verified through a preset verification code, the abnormal information can be extracted, a primary detection result is obtained, and the abnormal classification information is indexed by information marking, and is numbered according to a, b and c to generate an index catalog, numbering the bit storage cells according to 1, 2, 3.. to obtain numbered bit storage cells, the index directory and the number bit storage grid are correspondingly matched, and numbering is carried out according to 1-a/b/c, 2-a/b/c, 3-a/b/c, so that the position and the abnormal information of the abnormal information can be accurately searched;

the beneficial effects of the above technical scheme are: the method comprises the steps of calibrating the address of a bit storage grid, rapidly searching the position of the fault storage grid through a memory bank fault monitoring channel, marking and indexing detected abnormal information, and carrying out directory numbering through the index, so that the abnormal information can be accurately detected through the directory numbering, the specific information problem of the abnormal information can be obtained, and the memory bank can be optimized and improved according to the obtained abnormal information.

Example 8:

in one embodiment, address scaling is performed on bit cells in the level slices, and memory addressing is performed, where the address scaling includes: the row address calibration and the column address calibration comprise the following steps:

the steps for performing memory addressing are as follows:

step two: recording the row address in a vertical coordinate signal, recording the column address in a horizontal coordinate signal, and acquiring horizontal and vertical coordinate signal information;

step four: performing address interpretation according to the address information, and determining whether the address information is a calibration address based on the address interpretation;

in one practical scenario: the address in the memory bank information is searched by detecting the memory bank, and the step is memory addressing, so that the address information is accurately positioned, but the prior art does not relate to address calibration of a storage grid, so that the fault position in the memory bank cannot be accurately positioned;

the invention is implemented as follows: the method comprises the steps that address calibration is carried out on bit storage grids of a chip in a memory bank, so that addresses can be searched through a memory bank monitoring channel, the positions of the storage grids can be rapidly determined through searching the addresses, faults occurring in the storage grids in the memory bank can be effectively positioned, and when information stored in the storage grids is abnormal, the storage grids can be rapidly searched through calibrated address information;

the beneficial effects of the above technical scheme are: and executing memory addressing, namely quickly locking the horizontal coordinate signals and the vertical coordinate signals by a method of searching memory information addresses, and quickly finding the abnormal storage grids or abnormal calibration information at the address calibration positions from the row addresses and the column addresses of the horizontal coordinate and the vertical coordinate.

Example 9:

in one embodiment, the determining whether the information processing work of the memory bank numbering address is normal according to the numbering result, obtaining the determination result, and performing alarm display on the abnormal result includes:

based on the judgment result, when the judgment result shows that the memory bank information storage time is abnormal, performing voice alarm prompt for information storage time abnormity through a memory bank fault detection device;

formulating corresponding alarm processing schemes through different voice alarm prompts;

in one practical scenario: after the alarm is connected with the detection equipment or the detection device, the alarm gives an alarm after receiving an abnormal signal, but the alarm is only single alarm, specific alarm prompt voice is not available, and voice classification alarm is not available, so that the detection personnel cannot be clearly prompted, and the detection personnel cannot quickly find out the fault reason of the memory bank;

when the invention is implemented: according to the judgment result, when the memory bank information storage time is displayed to be abnormal, the memory bank storage grid address information processing is displayed to be abnormal and the hierarchical fragment number corresponding information is displayed to be abnormal, corresponding abnormal alarm is carried out on the three abnormal reasons, then the memory bank fault detection device is used for displaying the written memory bank fault prompt, and the alarm device is used for carrying out corresponding alarm voice prompt, so that the loss problem caused by the untimely fault processing can be solved;

the beneficial effects of the above technical scheme are: and as for the judged abnormal result, abnormal result voice alarm is carried out, abnormal information is transmitted to the memory bank fault detection device, then the alarm carries out prompt on the memory bank fault condition through voice alarm operation, so that detection personnel can find the fault condition of the memory bank in time, and the memory bank fault is maintained according to the voice alarm prompt, thereby avoiding more loss.

Example 10:

in an embodiment, the formulating a corresponding alarm processing scheme through different voice alarm prompts includes:

according to the abnormal voice alarm prompt of the information corresponding to the number, a scheme for detecting the integrity of the number and re-matching the number information is formulated;

in one practical scenario: according to the prior art, after an alarm task is executed through an alarm device, a corresponding problem solution is not formulated, the formulated corresponding solution can help a detector to timely process the fault problem of the memory bank according to the formulated scheme, and the fault processing cannot be timely performed after an alarm prompt is received without formulating the scheme, so that the fault of the memory bank is further aggravated, and more information loss is caused;

when the invention is implemented: through different abnormal voice prompts of the alarm, and according to the voice prompts, corresponding solutions are formulated, so that the memory bank can be ensured to be processed according to the formulated solutions after the alarm prompts are received at the first time;

the beneficial effects of the above technical scheme are: according to the voice alarm prompt, a solution of the corresponding abnormal problem is formulated, so that the detection personnel can be convenient to maintain according to the formulated scheme, more information loss of the memory bank due to untimely maintenance can be guaranteed, the formulated scheme is a scheme for preliminary maintenance of the memory bank faults, and the time wasted due to uncertain fault reasons is mainly saved.

Example 11:

in one embodiment, the method comprises the following steps: the device comprises a data line, a display screen, a detection host and an alarm;

the detection host further comprises: the channel monitor monitors the channel condition of the memory bank through connection;

in one practical scenario: in the existing memory bank detection technology, the fault condition of a memory bank is reacted through a data set and a data label, but the data set is not explicitly managed, so that the fault information in the data set with the memory bank fault is possibly disordered;

when the invention is implemented: the display screen is connected to the detection host in an embedded mode, data information of detection data can be displayed through the display screen, the detection host is connected with the alarm and the memory bank installation equipment through the data lines, and the alarm can be given out for prompting the abnormal condition of the memory bank through the alarm, wherein a channel monitor built in the detection host can be used for monitoring channels of the memory bank in the memory bank installation equipment, and the storage condition of channels divided in the memory bank is monitored in real time;

the beneficial effects of the above technical scheme are: the alarm can directly prompt an operator that the memory bank has a fault, so that the operator can timely maintain the memory bank to avoid leakage and loss of memory information, and the detection host can detect and search the fault of specific storage problems in the memory bank through the connected channel monitor.

Example 12:

in one embodiment, the method comprises the following steps:

A judgment warning module: judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, acquiring a judgment result, and carrying out alarm display on an abnormal result;

in one practical scenario: the detection of the faults of the memory bank mainly comprises the detection of the installation and the insertion of the memory bank, and the detection system of the faults of the memory bank is too simple to detect the faults of the memory bank, cannot detect the specific position of the internal information processing and storage of the memory bank, and cannot detect whether the time for processing the information in the memory bank is too long or not so as to cause the faults of the memory bank;

when the invention is implemented: through the functional interaction among all modules, a memory bank monitoring channel capable of monitoring a chip information storage processing route in a memory bank is constructed in a channel construction module, then address calibration and sequencing are carried out on the memory bank chip and the chip fragments and storage grids by a fragment acquisition module and a numbering and sequencing module, the specific fault address of the memory bank can be searched, and finally, the information of abnormal detection and judgment is transmitted and alarmed through a judgment alarm module;

the beneficial effects of the above technical scheme are: through the channel construction module, the fragment acquisition module, the serial number sequencing module and the judgment warning module, a memory bank fault detection system is formed jointly, through interaction among the modules, according to a routing inspection channel formed among memory bank chips, the chip integration fragments and the storage grids, specific fault points of information storage faults in the memory banks are accurately detected, detected fault information is transmitted to a memory bank fault detection device through the constructed memory bank monitoring channel to be subjected to alarm prompt, and the fault positions of the memory banks can be found rapidly.

It will be apparent to those skilled in the art that various changes and modifications may be made in the present invention without departing from the spirit and scope of the invention. Thus, if such modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include such modifications and variations.

Claims

1. A method for detecting a memory bank fault is characterized by comprising the following steps:

address calibration is carried out on bit position storage lattices in the level fragments, and the level fragments and the bit position storage lattices are numbered and sequenced to obtain numbering results;

2. The method for detecting the failure of the memory bank according to claim 1, wherein the step of setting the failure detection device of the memory bank and connecting the detection device with the memory bank installation equipment to construct a memory bank monitoring channel comprises the following steps:

3. The method according to claim 1, wherein when the predetermined result indicates a memory bank storage failure, a memory bank channel monitoring mechanism is formulated, and a memory bank monitoring channel is constructed by a memory bank detection device according to the memory bank channel monitoring mechanism, the method comprising:

wherein, the memory bank channel monitoring mechanism comprises:

according to the section time, performing system sampling to obtain a section time sample, and performing data comparison on the section time sample data, preset information transmission time and preset information processing time to obtain time difference value data;

4. The method for detecting the failure of the memory bank according to claim 1, wherein the step of performing the hierarchical classification on the integrated slices of the memory bank chip through the memory bank monitoring channel to obtain the hierarchical slices comprises:

5. The method for detecting the failure of the memory bank according to claim 1, wherein the address calibration is performed on the bit storage cells in the level fragments, and the numbering and sorting are performed on the level fragments and the bit storage cells to obtain the numbering result, and the method comprises the following steps:

6. The method according to claim 5, wherein address scaling is performed on bit cells in the level slices to perform memory addressing, wherein the address scaling comprises: the row address calibration and the column address calibration comprise the following steps:

the steps for performing memory addressing are as follows:

7. The method for detecting the failure of the memory bank according to claim 1, wherein the step of judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, obtaining the judgment result and displaying the abnormal result by alarming comprises the steps of:

8. The method according to claim 7, wherein the step of formulating a corresponding alarm processing scheme through different voice alarm prompts comprises:

and formulating a scheme for detecting the integrity of the number and re-matching the number information according to the abnormal voice alarm prompt of the information corresponding to the number.

9. A memory bank fault detection device, comprising: the device comprises a data line, a display screen, a detection host and an alarm;

10. A memory bank fault detection system, comprising:

A judgment warning module: and judging whether the information processing work of the memory bank numbering address is normal or not according to the numbering result, acquiring a judgment result, and carrying out alarm display on an abnormal result.