CN114579392A - AXI bus monitor for write transactions - Google Patents

AXI bus monitor for write transactions Download PDF

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CN114579392A
CN114579392A CN202110089932.8A CN202110089932A CN114579392A CN 114579392 A CN114579392 A CN 114579392A CN 202110089932 A CN202110089932 A CN 202110089932A CN 114579392 A CN114579392 A CN 114579392A
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write
channel
response
bus
data
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涂友钢
张泽
黄好城
刘传杰
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Chengdu Starblaze Technology Co ltd
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/3003—Monitoring arrangements specially adapted to the computing system or computing system component being monitored
    • G06F11/3027—Monitoring arrangements specially adapted to the computing system or computing system component being monitored where the computing system component is a bus
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38—Information transfer, e.g. on bus
    • G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
    • G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

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Abstract

The present application provides a monitor for an AXI bus for write transactions. The bus monitor is used for coupling slave devices of a bus to the bus, wherein the bus comprises a write address channel, a write data channel and a write response channel; the bus monitor comprises an error signal generating device; the error signal generating means couples the write address channel and the write data channel, the error signal generating means outputting a slave device exception signal in response to no data being captured from the write data channel for a first write transaction within a specified time after the first write transaction is captured from the write address channel; the error signal generating means is further coupled to a write response channel, and in response to a failure to capture a response to the first write transaction from the write response channel within a specified time after capturing data of the first write transaction from the write data channel, the error signal generating means outputs a slave device exception signal.

Description

AXI bus monitor for write transactions
Technical Field
The present application relates to chip technology, and in particular, to a monitor for an AXI bus for write transactions.
Background
Axi (advanced eXtensible interface) is a bus protocol, which is a high-performance, high-bandwidth, low-latency on-chip bus. A bus supporting the AXI protocol is referred to as an AXI bus.
The AXI bus includes 5 independent channels, a read address Channel (ReadAddressChannel), a read Data Channel (ReadDataChannel), a Write address Channel (WriteAddressChannel), a Write Data Channel (writedata Channel), and a Write response Channel (WriteResponseChannel).
A channel includes a set of signals used to transfer transactions between a master and a slave of an AXI bus. Table 1 shows the signals for the read address channel, Table 2 shows the signals for the read data channel, Table 3 shows the signals for the write address channel, Table 4 shows the signals for the write data channel, and Table 5 shows the signals for the write response channel.
TABLE 1
Signal Source Description of the invention
ARID[3:0] Master device Read address ID
ARADDR[31:0] Master device Reading address
ARLEN[3:0] Master device Burst read length
ARSIZE[2:0] Master device Burst type reading size
ARBURST[1:0] Master device Burst read type
ARLOCK[1:0] Master device Lock type
ARCACHE[3:0] Master device Cache type
ARPROT[2:0] Master device Type of protection
ARVALID Master device The read address is valid. The signal is held until ARREADY is high
ARREADY Slave device Slave device ready
TABLE 2
Figure BDA0002912064870000011
Figure BDA0002912064870000021
TABLE 3
Figure BDA0002912064870000022
TABLE 4
Figure BDA0002912064870000023
TABLE 5
Figure BDA0002912064870000024
Figure BDA0002912064870000031
Fig. 1 shows the structure of an AXI bus.
The AXI bus is used to couple one or more masters (master 1, master 2, … … master N) with one or more slaves (slave 1, slave 2, slave 3 … … slave N). The master device writes data to the slave device or reads data through the slave device. The master and slave devices are coupled to each other through an AXI bus interconnect (Interconnection), which is simply referred to as an AXI bus for the sake of simplicity without causing confusion.
The AXI bus defines transactions. The read transaction includes an address provided by the master to the slave on the read address channel and data provided by the slave to the master on the read data channel. The write transaction includes an address provided by the master to the slave on the write address channel, data provided by the master to the slave on the write data channel, and a response provided by the slave to the master on the write response channel.
Figure 2 is a timing diagram illustrating a read transaction of an AXI bus.
The master issues one or more read transactions to a specified slave on a read address channel. The read transaction indicates the address to read (indicated by the ARADDR signal of FIG. 2) and the length of data to read (not shown in FIG. 2). The master also indicates to the slave the presence of an address to read by setting the read address valid signal (the ARValid signal of FIG. 2). The slave provides a device ready signal (the ARReady signal of fig. 2) to the master indicating that it is capable of receiving a read address. In the example of FIG. 2, the master concurrently issues 2 read addresses (A and B of the ARADDR signal of FIG. 2) to the slave. The two addresses belong to two read transactions. Read address B has been issued before read address a is responded to. The slave provides the read data (D (a0, D (a1), D (a2), D (B0) and D (B2) signals of fig. 2) to the master on a read data channel, where a and B each indicate their corresponding read addresses). The slave device also indicates the read data to the master device via a signal such as RValid, RLast, etc. in the data channel. Optionally, according to the AXI protocol, for 2 or more concurrent read addresses (each corresponding to a read transaction), the slave starts processing the second read address after all data to be read is provided for one read address.
Figure 3 is a timing diagram illustrating a write transaction of an AXI bus.
In the example of FIG. 3, a master issues a write transaction to a designated slave on a write address channel. The write transaction indicates the address to which the data is to be written (indicated by the AWADDR signal of FIG. 3) and the length of the data to be written (not shown in FIG. 3). The master also indicates to the slave the occurrence of an address to write by setting a write address valid signal (AWValid signal of fig. 3). The slave provides a device ready signal (AWReady signal of fig. 3) to the master indicating that it is capable of receiving a write address. In the example of fig. 3, the master issues 1 write address (a of the AWADDR signal of fig. 3) to the slave. The slave provides the read data (D (a0, D (a1), D (a2), and D (A3)) signals of fig. 3) to the master at the write data channel. The master also indicates the written data to the master on the data channel via a signal such as WValid, WLast, etc. The slave indicates to the master through the write response channel that it received the data to be written by the write transaction (BValid signal and BResp signal (ok) of fig. 3).
The transaction is identified by an ID. Multiple transactions may be concurrent on the AXI bus. Multiple transactions identified by the same ID may be concurrent but must complete in sequence, and data transfers of subsequent transactions cannot be initiated before data transfers of previous transactions are completed. Multiple concurrent transactions, identified by different IDs, may be transmitted out of order and completed.
The AXI bus performs data transmission, when abnormality occurs in the transmission process, such as the master device being hung up, the slave device being hung up, and logic running out of order, the upstream and downstream ends (the master device and the slave device) interfere with each other, so that the AXI bus cannot perform normal data transmission, and only the AXI bus can be recovered by waiting for system restart.
Disclosure of Invention
An abnormality may occur to the AXI bus devices (master and/or slave). Especially in the development phase of chips or bus devices, the bus devices and even the buses themselves may fail. A locally occurring fault may also propagate within the chip or the electronic device, resulting in an abnormal operation of the entire device, or even a danger. And also causes difficulty in fault location, thereby affecting development and debugging processes.
After the bus is abnormal, the abnormality is generally difficult to be effectively processed, so that other devices, buses or other bus transactions have chain reactions, the error range and the influence are further amplified, and the system needs to be restarted to recover. This can have a significant impact on system stability, data security, etc.
According to an embodiment of the application, an AXI bus device is provided with a monitor module for monitoring the transmission condition of the bus by intercepting the transaction of the bus. When the bus abnormity is identified, the information of the position of the abnormity, the abnormal affair ID and the like is reported so as to monitor the running condition of the AXI bus, find, locate and process the abnormity in time and promote the repair of the defect causing the abnormity.
According to the monitor module of the embodiment of the application, when the bus is detected to be dead, that is, the existing bus transaction is sent, but data and response information corresponding to the transaction are not completed for a long time, the monitor module takes over the master device or the slave device with the abnormality, and generates (false) substitute signals to replace the master device or the slave device with the abnormality to complete the transmission of the transaction on the bus according to the captured transaction which starts to be transmitted but is not completed. Thereby avoiding cascading failures at the upstream and downstream ends. Optionally, external components such as the CPU are also notified of bus exception conditions and processing conditions. Therefore, the external CPU can timely access the processing of AXI bus abnormality, and the AXI bus abnormality processing can be completed by means of means such as bus reset without resetting the whole system.
In order to solve the above technical problem, according to a first aspect of the present application, there is provided a first bus monitor of the first aspect of the present application for coupling a slave device of a bus to the bus; the bus monitor comprises an error signal generating device; the error signal generation means, coupled to a write address channel and a write data channel, outputs a slave device exception signal in response to no capture of data for a first write transaction from the write data channel within a specified time after capture of the first write transaction from the write address channel; the error signal generating means is further coupled to a write response channel, and in response to a failure to capture a response to the first write transaction from the write response channel within a specified time after capturing data of the first write transaction from the write data channel, the error signal generating means outputs a slave device exception signal.
According to a first bus monitor of the first aspect of the present application, there is provided a second bus monitor of the first aspect of the present application, further comprising a monitor signal generating means; the monitoring signal generating device is coupled with a write address channel, a write-read data channel and a write response channel, responds to the abnormal signal of the slave device obtained from the error signal generating device, and indicates the slave device to receive write data to a write data channel if the data of a first write transaction is not captured from the write data channel within a specified time after the first write transaction is captured from the write address channel; the monitor signal generating means indicates to the write response channel a response to the first write transaction if no response to the first write transaction is captured from the write response channel within a specified time after data of the first write transaction is captured from the write data channel, and the monitor signal generating means further indicates to the write address channel that a second write transaction is not ready to be received from the write address channel in response to obtaining the slave exception signal from the error signal generating means.
According to a second bus monitor of the first aspect of the present application, there is provided a third bus monitor of the first aspect of the present application, further comprising output gating means; the output gating means couples a write address channel, a write data channel, and a write response channel, the output gating means providing a signal to the bus through the write data channel that the monitor signal generating means indicates that a slave is ready to receive write data in response to obtaining the slave exception signal from the error signal generating means, or the output gating means providing a signal to the bus through the write response channel that the monitor signal generating means indicates a response to the first write transaction, and the monitor signal generating means also indicating to the write address channel that a second write transaction is not ready to receive from the write address channel in response to obtaining the slave exception signal from the error signal generating means.
According to one of the first to third bus monitors of the first aspect of the present application, there is provided a fourth bus monitor of the first aspect of the present application, the error signal generating means timing in response to a number of the plurality of write transactions with the first ID captured from the write address channel not being equal to a number of last data transfers (WLast) of the write transactions with the first ID captured from the write data channel; in response to a number of the plurality of write transactions with the first ID captured from the write address channel being equal to a number of last data transfers of the write transactions with the first ID captured from the write address channel and a number of the plurality of write transactions with the first ID captured from the write address channel being not equal to a number of responses to the write transactions with the first ID captured from the write response channel, the error signal generation means times; a timing reset of the error signal generation means in response to a number of the plurality of write transactions with the first ID captured from the write address channel being equal to a number of responses to the write transactions with the first ID captured from the write response channel, or in response to a response to one of the plurality of write transactions with the first ID captured from the write response channel, or in response to a data transfer to one of the plurality of write transactions with the first ID captured from the write data channel; in response to timing timeout, the error signal generation means outputs the slave device abnormality signal.
According to one of the first to fourth bus monitors of the first aspect of the present application, there is provided the fifth bus monitor of the first aspect of the present application, wherein the error signal generating means includes a first counter, a second counter, a third counter, and a timer; the first counter counts a number of a plurality of write transactions having a first ID captured from the write address channel; the second counter counts a number of last data transfers captured from the write data channel for a plurality of write transactions having a first ID; the third counter counts a number of responses to a plurality of write transactions having a first ID captured from the write response channel; in response to the count value of the first counter not being equal to the count value of the second counter or the count value of the first counter not being equal to the count value of the third counter, the timer times; in response to the count value of the first counter being equal to the count value of the second counter, or in response to capturing a data transfer from the write data channel to one of the plurality of write transactions having the first ID, or in response to capturing a response from the write response channel to one of the plurality of write transactions having the first ID, the timer resets; the error signal generation means outputs the slave device abnormality signal in response to a timer exceeding a specified threshold.
According to one of the first to fifth bus monitors of the first aspect of the present application, there is provided the sixth bus monitor of the first aspect of the present application, wherein the error signal generation means identifies a capture of a write transaction according to a write address valid signal (AWValid) of the write address channel, identifies a capture of a last data transmission of a write transaction according to a signal (WLAST) of the write data channel indicating last data of a write transaction, and identifies a capture of a response to a write transaction according to a write response valid signal (BValid) of the write response channel.
According to one of the first to fifth bus monitors of the first aspect of the present application, there is provided the seventh bus monitor of the first aspect of the present application, wherein the error signal generation means identifies a capture of the write transaction according to a write address valid signal (AWValid) and a device ready (AWReady) signal of the write address channel, identifies a capture of a last data transfer for the write transaction according to a signal (WLAST) indicating last data of the write transaction, a write data valid signal (WValid) and a device ready signal (WReady) of the write data channel, and identifies a capture of a response to the write transaction according to a write response valid signal (BValid) and a host ready signal (BReady) of the write response channel.
According to one of the second to seventh bus monitors of the first aspect of the present application, there is provided the eighth bus monitor of the first aspect of the present application, wherein the monitor signal generation means indicates to the write data channel that the signal that the slave is ready to receive write data is a device ready signal (WReady) for the write data channel; the signal indicating the response to the first write transaction to the write response channel by the monitor signal generation means is a write response valid signal (BValid) for the write response channel; the monitor signal generation means indicates to the write address channel that the signal not ready to receive the second write transaction from the write address channel is an overridden device ready signal (AWReady) for the write address channel.
According to one of the third to eighth bus monitors of the first aspect of the present application, there is provided a ninth bus monitor of the first aspect of the present application, in response to the slave abnormality signal being acquired from the error signal generating means, the output gating means supplies a device ready signal (WReady) for the write data channel generated by the monitor signal generating means to the bus through the write data channel, the output gating means supplies a write response valid signal (BValid) for the write response channel generated by the monitor signal generating means to the bus, or the output gating means supplies a device not ready signal (AWReady) for the write address channel generated by the monitor signal generating means to the bus; in response to the slave abnormality signal not being acquired from the error signal generation means, the output strobe means supplies the signal for the write address channel, the signal for the write data channel, and the signal for the write response channel acquired from the bus to the slave, and supplies the signal for the write address channel, the signal for the write data channel, and the signal for the write response channel acquired from the slave to the bus.
According to one of the first to ninth bus monitors of the first aspect of the present application, there is provided the tenth bus monitor of the first aspect of the present application, further comprising configuration means; the configuration means is for providing an error enable signal to the error signal generating means, a reset signal to the error signal generating means and the monitor signal generating means, and a bypass signal to the output gating means.
According to a tenth bus monitor of the first aspect of the present application, there is provided the eleventh bus monitor of the first aspect of the present application, wherein the error signal generation means generates the slave abnormality signal in response to the error enable signal; in response to the reset signal, the error signal generation means cancels the slave device abnormality signal; in response to the bypass signal, or the reset signal, the output gating means supplies the signal for the write address channel, the signal for the write data channel, and the signal for the write response channel, which are acquired from the bus, to the slave, and supplies the signal for the write address channel, the signal for the write data channel, and the signal for the write response channel, which are acquired from the slave, to the bus.
According to one of the first to eleventh bus monitors of the first aspect of the present application, there is provided the twelfth bus monitor of the first aspect of the present application, wherein the error signal generation means outputs a slave abnormality signal in response to a response from the write data channel to any one of the plurality of write transactions having the first ID not being captured within a specified time after capturing the plurality of write transactions having the first ID from the write address channel.
According to a twelfth bus monitor of the first aspect of the present application, there is provided the thirteenth bus monitor of the first aspect of the present application, wherein the error signal generating means includes a first counter, a second counter, a third counter and a timer corresponding to each ID of the write transaction; a first counter counts a number of write transactions captured from the write address channel having an ID corresponding to the first counter; the second counter counts a number of last data transfers of write transactions captured from the write data channel having an ID corresponding to the second counter; the third counter counts a number of responses of the write transaction captured from the write response channel having the ID corresponding to the third counter.
According to a thirteenth bus monitor of the first aspect of the present application, there is provided the fourteenth bus monitor of the first aspect of the present application, wherein in response to acquisition of the slave abnormality signal from the error signal generation means for each first ID of a write transaction, if a value of a first counter corresponding to the first ID is the same as a value of a second counter corresponding to the first ID and a value of the second counter corresponding to the first ID is different from a value of a third counter corresponding to the first ID, the monitor signal generation means indicates a write response valid signal (BValid) for the write response channel, a signal corresponding to the first ID, and a write response signal (BResp) representing an error of the slave to the write response channel.
According to a fourteenth bus monitor of the first aspect of the present application, there is provided the fifteenth bus monitor of the first aspect of the present application, wherein if there is no first ID for each first ID of a write transaction, satisfying a condition that a value of a first counter corresponding to the first ID is the same as a value of a second counter corresponding to the first ID and a value of the second counter corresponding to the first ID is not the same as a value of a third counter corresponding to the first ID, the monitor signal generating means indicates to the write response channel a revoked write response valid signal (BValid) for the write response channel.
According to a fourteenth or fifteenth bus monitor of the first aspect of the present application, there is provided the sixteenth bus monitor of the first aspect of the present application, wherein the output gating means supplies the monitor signal generating means to the bus through the write response channel a write response valid signal (BValid) indicating a valid signal for the write response channel, a signal corresponding to the first ID, and a write response signal (BResp) representing the slave error, or the output gating means supplies the monitor signal generating means to the bus through the write response channel a write response valid signal (BValid) indicating a revocation, for the write response channel.
According to one of the fourteenth to sixteenth bus monitors of the first aspect of the present application, there is provided the seventeenth bus monitor of the first aspect of the present application, wherein the response of the write transaction having the ID corresponding to the third counter, captured from the write response channel, is a write response valid signal (BValid) for the write response channel indicated by the monitor signal generating means, a signal corresponding to the first ID, and a write response signal (BResp) representing the slave error.
According to one of the fourteenth to seventeenth bus monitors of the first aspect of the present application, there is provided the eighteenth bus monitor of the first aspect of the present application, wherein for each first ID of a write transaction, in response to acquiring the slave abnormality signal from the error signal generating means, if a value of a first counter corresponding to the first ID is different from a value of a second counter corresponding to the first ID, the monitor signal generating means indicates a device ready signal (WReady) for the write data channel.
According to one of the first to eighteenth bus monitors of the first aspect of the present application, there is provided a nineteenth bus monitor of the first aspect of the present application, the bus including the write address channel, the write data channel, and the write response channel.
According to a second aspect of the present application there is provided a first bus monitor according to the second aspect of the present application for coupling a master of a bus to the bus; the bus monitor comprises an error signal generating device; the error signal generating means couples a write address channel and a write data channel, and in response to no capture of data for a first write transaction from the write data channel within a specified time after capture of the first write transaction from the write address channel, the error signal generating means outputs a master exception signal; and said error signal generating means is further coupled to a write response channel, said error signal generating means outputting a master exception signal in response to no response being captured from said write response channel to said first write transaction within a specified time after the last data of said first write transaction was captured from said write data channel.
According to a first bus monitor of the second aspect of the present application, there is provided a second bus monitor of the second aspect of the present application, further comprising monitor signal generating means; the monitoring signal generating device is coupled with a writing address channel; the monitoring signal generating means comprises a memory; the monitoring signal generation device captures the data length to be written by the first write transaction from the write address channel and stores the data length to be written by the first write transaction in the memory; the monitor signal generating means captures a length of data written by the first write transaction from the write data channel; in response to acquiring the master device exception signal from the error signal generation device, if the complete data to be written by the first write transaction is not captured from the write data channel within a specified time after the first write transaction is captured from the write address channel, the monitoring signal generation device acquires the data length to be written by the first write transaction from the memory, and transmits data of the first difference amount through the write data channel according to a first difference between the data length to be written by the first write transaction and the data length written by the first write transaction.
According to a second bus monitor of a second aspect of the present application, there is provided the third bus monitor of the second aspect of the present application, wherein in response to acquisition of the master device abnormality signal from the error signal generation means, if no response to the first write transaction is captured from the write response channel within a specified time after the last data of the first write transaction is captured from the write data channel, the monitor signal generation means indicates the response to the first write transaction to the master device.
According to a second or third bus monitor of the second aspect of the present application, there is provided a fourth bus monitor of the second aspect of the present application, the monitor signal generating means indicating to the master that it is not ready to receive a second write transaction from the write address channel in response to retrieving the master exception signal from the error signal generating means.
According to one of the second to fourth bus monitors of the second aspect of the present application, there is provided the fifth bus monitor of the second aspect of the present application, further comprising output gating means; the output gating device is coupled with a write address channel, a write data channel and a write response channel, and responds to the master device abnormal signal acquired from the error signal generating device, and the output gating device provides data transmitted to a slave device by the monitoring signal generating device through the write data channel to the write data channel of the bus.
According to one of the third to fifth bus monitors of the second aspect of the present application, there is provided a sixth bus monitor of the second aspect of the present application, comprising output gating means; in response to obtaining the master exception signal from the error signal generating means, the output gating means provides the master with a response to the first write transaction indicated to the master by the monitor signal generating means.
According to one of the fourth to sixth bus monitors of the second aspect of the present application, there is provided a seventh bus monitor of the second aspect of the present application, comprising output gating means; in response to obtaining the master exception signal from the error signal generating means, the output gating means provides a signal to the master that the monitor signal generating means indicates to the master that it is not ready to receive a second write transaction from the write address channel.
According to one of the first to seventh bus monitors of the second aspect of the present application, there is provided the eighth bus monitor of the second aspect of the present application, in response to the number of the plurality of write transactions with the first ID captured from the write address channel not being equal to the number of the last data transfer of the write transactions with the first ID captured from the write data channel, the error signal generating means timing; in response to a number of write transactions with a first ID captured from the write address channel being equal to a number of last data transfers of write transactions with a first ID captured from the write address channel and a number of write transactions with a first ID captured from the write address channel being not equal to a number of responses to write transactions with a first ID captured from the write response channel, the error signal generation means times; a timing reset of the error signal generation means in response to a number of capture of a plurality of write transactions having the first ID from the write address channel being equal to a number of capture of responses to write transactions having the first ID from the write response channel, or in response to a capture of a response to one of a plurality of write transactions having the first ID from the write response channel, or in response to a capture of a data transfer to one of a plurality of write transactions having the first ID from the write data channel; in response to a timing timeout, the error signal generation means outputs the master exception signal.
According to one of the first to eighth bus monitors of the second aspect of the present application, there is provided the ninth bus monitor of the second aspect of the present application, wherein the error signal generating means includes a first counter, a second counter, a third counter, and a timer; the first counter counts a number of a plurality of write transactions having a first ID captured from the write address channel; the second counter counts a number of burst data transfers captured from the write data channel for a plurality of write transactions having a first ID; the third counter counts a number of responses to a plurality of write transactions having a first ID captured from the write response channel; in response to the count value of the first counter not being equal to the count value of the second counter or the count value of the first counter not being equal to the count value of the third counter, the timer times; in response to the count value of the first counter being equal to the count value of the second counter, or in response to capturing a data transfer from the write data channel to one of the plurality of write transactions having the first ID, or in response to capturing a response from the write response channel to one of the plurality of write transactions having the first ID, the timer resets; the error signal generation means outputs the slave abnormality signal in response to a timer exceeding a specified threshold.
According to one of the first to ninth bus monitors of the second aspect of the present application, there is provided the tenth bus monitor of the second aspect of the present application, wherein the error signal generation means identifies a capture of a write transaction according to a write address valid signal (AWValid) of the write address channel, identifies a capture of a last data transmission of a write transaction according to a signal (WLAST) of the write data channel indicating last data of a write transaction, and identifies a capture of a response to a write transaction according to a write response valid signal (BValid) of the write response channel.
According to one of the first to ninth bus monitors of the second aspect of the present application, there is provided the eleventh bus monitor of the second aspect of the present application, wherein the error signal generation means identifies the capture of the write transaction according to a write address valid signal (AWValid) and a device ready (AWReady) signal of the write address channel, identifies the capture of the last data transfer for the write transaction according to a signal (WLAST) indicating the last data of the write transaction, a write data valid signal (WValid) and a device ready signal (WReady) of the write data channel, and identifies the capture of the response to the write transaction according to a write response valid signal (BValid) and a host ready signal (BReady) of the write response channel.
According to one of the third to eleventh bus monitors of the second aspect of the present application, there is provided the twelfth bus monitor of the second aspect of the present application, wherein the monitor signal generation means indicates to the master that the signal of the response to the write transaction is a write response valid signal (BValid) for the write response channel; the monitor signal generation means indicates to the master device that the signal not ready to receive a second write transaction from the write address channel is a revoked device ready signal (AWReady) for the write address channel.
According to one of the second to twelfth bus monitors of the second aspect of the present application, there is provided the thirteenth bus monitor of the second aspect of the present application, wherein the monitor signal generation means includes a counter, and the counter of the monitor signal generation means counts a length of data written by the first write transaction captured from the write data channel; wherein the monitor signal generating means identifies capture of data written by the first write transaction based on a write data valid signal (WValid) and/or a device ready signal (WReady) of the write data channel.
According to one of the first to thirteenth bus monitors of the second aspect of the present application, there is provided the fourteenth bus monitor according to the second aspect of the present application, further comprising configuration means; the configuration means is for providing an error enable signal to the error signal generating means, a reset signal to the error signal generating means and the monitor signal generating means, and a bypass signal to the output gating means.
According to a fourteenth bus monitor of the second aspect of the present application, there is provided the fifteenth bus monitor of the second aspect of the present application, wherein the error signal generation means generates the master abnormality signal in response to the error enable signal; in response to the reset signal, the error signal generation means cancels the master device abnormality signal; in response to the bypass signal, or the reset signal, the output gating means supplies the signal for the write address channel, the signal for the write data channel, and the signal for the write response channel acquired from the bus to the master device, and supplies the signal for the write address channel, the signal for the write data channel, and the signal for the write response channel acquired from the master device to the bus.
According to one of the first to fifteenth bus monitors of the second aspect of the present application, there is provided the sixteenth bus monitor of the second aspect of the present application, wherein the error signal generation means outputs a master exception signal in response to a response from the write data channel to any one of the plurality of write transactions having the first ID not being captured within a specified time after capturing the plurality of write transactions having the first ID from the write address channel.
According to a sixteenth bus monitor of the second aspect of the present application, there is provided the seventeenth bus monitor of the second aspect of the present application, wherein the error signal generation means outputs a master exception signal in response to a response from the write response channel to any one of the plurality of write transactions having the first ID not being captured within a specified time after capturing complete data of the plurality of write transactions having the first ID from the write data channel.
According to a seventeenth bus monitor of the second aspect of the present application, there is provided the eighteenth bus monitor of the second aspect of the present application, wherein the error signal generating means includes a first counter, a second counter, a third counter and a timer corresponding to each ID of the write transaction; the first counter counts the number of write transactions captured from the write address channel with the ID corresponding to the first counter; the second counter counts the number of burst data transfers of the write transaction captured from the write data channel having the ID corresponding to the second counter; the third counter counts a number of responses of the write transaction captured from the write response channel having the ID corresponding to the third counter.
According to an eighteenth bus monitor of the second aspect of the present application, there is provided the nineteenth bus monitor of the second aspect of the present application, wherein in response to acquisition of the master abnormality signal from the error signal generation means for each first ID of a write transaction, if a value of a first counter corresponding to the first ID is the same as a value of a second counter corresponding to the first ID and a value of a second counter corresponding to the first ID is not the same as a value of a third counter corresponding to the first ID, the monitor signal generation means indicates a write response valid signal (BValid) for the write response channel, a signal corresponding to the first ID, and a write response signal (BResp) representing an error of the slave to the master.
According to a nineteenth bus monitor of the second aspect of the present application, there is provided the twentieth bus monitor of the second aspect of the present application, wherein if there is no first ID for each first ID of a write transaction, satisfying a case where a value of a first counter corresponding to the first ID is different from a value of a second counter corresponding to the first ID and a value of the second counter corresponding to the first ID is different from a value of a third counter corresponding to the first ID, the monitor signal generating means indicates to the master a revoked write response valid signal (BValid) for the write response channel.
According to one of the eighteenth to twentieth bus monitors of the second aspect of the present application, there is provided the twenty-first bus monitor of the second aspect of the present application, wherein the monitor signal generation means includes a counter corresponding to each ID of the write transaction; a counter of the monitoring signal generation device counts the length of data written by a write transaction captured from the write data channel and having an ID corresponding to the counter of the monitoring signal generation device; the monitoring signal generating device identifies that the data which is captured and written by the writing transaction with the ID corresponding to the counter of the monitoring signal generating device is captured according to the ID of the writing data channel, the writing data valid signal (WValid) and the equipment ready signal (WReady).
According to a nineteenth or twentieth bus monitor of the second aspect of the present application, there is provided the twenty-second bus monitor of the second aspect of the present application, wherein the output gating means supplies the write response valid signal (BValid) for the write response channel, the signal corresponding to the first ID, and the write response signal (BResp) representing the slave error to the master device through the write response channel, which the monitor signal generating means indicates to the master device to cancel, or supplies the write response valid signal (BValid) for the write response channel, which the monitor signal generating means indicates to the master device to cancel, to the master device through the write response channel.
According to one of the eighteenth to twenty-second bus monitors of the second aspect of the present application, there is provided the twenty-third bus monitor of the second aspect of the present application, wherein a response of the write transaction with an ID corresponding to the third counter, captured from the write response channel, is a write response valid signal (BValid) for the write response channel, a signal corresponding to the first ID, and a write response signal (BResp) representing an error of the slave, which are indicated to the master by the monitor signal generating means.
According to one of the nineteenth to twenty-third bus monitors of the second aspect of the present application, there is provided the twenty-fourth bus monitor of the second aspect of the present application, wherein for each first ID of a write transaction, in response to acquiring the master exception signal from the error signal generating means, the monitor signal generating means indicates a device ready signal (WReady) for the write data channel to the master if a value of a first counter corresponding to the first ID is different from a value of a second counter corresponding to the first ID.
According to one of the nineteenth to twenty-fourth bus monitors of the second aspect of the present application, there is provided a twenty-fifth bus monitor according to the second aspect of the present application, for each first ID of a write transaction, in response to obtaining the master exception signal from the error signal generating device, if a write transaction corresponding to the first ID is captured from the write address channel and complete data to be written by the write transaction corresponding to the first ID is not captured from the write data channel, the monitoring signal generation device acquires the data length to be written by the write transaction corresponding to the first ID from the memory, according to a first difference of a data length to be written by the write transaction corresponding to the first ID and a corresponding first ID of the data length already written by the write transaction corresponding to the first ID, transmitting the data of the first difference amount corresponding to the first ID to the slave device through the write data channel.
According to one of the first to twenty-fifth bus monitors of the second aspect of the present application, there is provided a twenty-sixth bus monitor of the second aspect of the present application, the bus including the write address channel, the write data channel, and the write response channel.
According to a third aspect of the present application, there is provided a first electronic system according to the third aspect of the present application, comprising a master device, a slave device, a bus, a master device bus monitor and a slave device bus monitor; the bus provides a write data channel, a write address channel and a write response channel; the master bus monitor is to couple the master with the bus; the slave bus monitor is to couple the slave with the bus; the master bus monitor is a bus monitor according to one of the first to twenty-sixth bus monitors of the second aspect of the present application; the slave bus monitor is a bus monitor according to one of the first to nineteenth bus monitors of the first aspect of the present application.
According to a first electronic system of the third aspect of the present application, there is provided a second electronic system according to the third aspect of the present application, further comprising a processor; the processor generates an exception and/or resets the master bus monitor or the slave bus monitor in response to receiving a master exception signal output by the master bus monitor or a slave exception signal output by the slave bus monitor.
According to the first or second electronic system of the third aspect of the present application, there is provided the third electronic system according to the third aspect of the present application, further comprising a processor; the master device abnormal signal generated by the master device bus monitor is also provided to the monitoring signal generating device of the slave device bus monitor; the monitoring signal generating device of the slave bus monitor generates a slave abnormal signal in response to receiving the master abnormal signal; the slave device abnormal signal generated by the slave device bus monitor is also provided to the monitoring signal generating device of the master device bus monitor; the monitoring signal generating means of the master bus monitor generates a master abnormality signal in response to receiving the slave abnormality signal.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings needed to be used in the description of the embodiments or the prior art will be briefly described below, it is obvious that the drawings in the following description are only some embodiments described in the present application, and other drawings can be obtained by those skilled in the art according to the drawings.
FIG. 1 illustrates a block diagram of a prior art storage device;
FIG. 2 illustrates a timing diagram of a read transaction for a prior art AXI bus;
FIG. 3 illustrates a timing diagram of a write transaction for a prior art AXI bus;
figure 4 illustrates a block diagram of an AXI bus according to an embodiment of the present application;
FIG. 5 illustrates a block diagram of a bus monitor for master write transactions, according to an embodiment of the present application;
FIG. 6 illustrates a block diagram of a bus monitor for a slave write transaction in accordance with an embodiment of the present application;
FIGS. 7A and 7B illustrate block diagrams of an error signal generation apparatus of a bus monitor for write transactions according to an embodiment of the present application;
FIG. 8 illustrates a block diagram of a monitor signal generation apparatus of a bus monitor for master write transactions according to an embodiment of the present application; and
FIG. 9 shows a block diagram of a monitor signal generation apparatus of a bus monitor for a slave write transaction according to an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application are clearly and completely described below with reference to the drawings in the embodiments of the present application, and it is obvious that the described embodiments are some, but not all, embodiments of the present application. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
Figure 4 shows a block diagram of an AXI bus according to an embodiment of the application.
According to an embodiment of the application, a bus monitor for master write transactions (briefly referred to as bus monitor MW) and a bus monitor for slave write transactions (briefly referred to as bus monitor SW) are provided.
The bus monitor MW is located between the master and the AXI bus, monitors the behavior of the AXI bus write channel by capturing signals of the write address channel, the write data channel and the write response channel to identify the occurrence of an exception condition, and provides a false substitute signal to the AXI bus (and the coupled master) when an exception occurs to complete the transmission of the write transaction, avoiding that the exception affects the coupled master, bus and/or slave.
The bus monitor SW is located between the slave device and the AXI bus, monitors the behavior of the AXI bus write channel by capturing signals of the write address channel, the write data channel and the write response channel to identify the occurrence of an abnormal situation, and provides a false substitute signal to the AXI bus (and the coupled slave device) when an abnormality occurs to complete the transmission of the write transaction, avoiding the abnormality from affecting the master device, the bus and/or the coupled slave device.
Referring to fig. 4, a master 1 is coupled to the bus through a bus monitor MW, a master 2 is coupled to the bus through a bus monitor MW, a slave 2 is coupled to the bus through a bus monitor SW, and the other masters and slaves are directly coupled to the bus (without going through the bus monitor). Thus a bus monitor MW/bus monitor SW according to an embodiment of the present application, which follows the AXI protocol, can be used either alone or in combination. When used alone (e.g. the bus monitor MW coupling the master 2), the master 2 is coupled to the AXI bus through the bus monitor MW and accesses, for example, the slave 3. The slave device 3 does not need to be aware of the bus monitor MW but only interacts with the master device 2 according to the AXI protocol. Similarly, the bus monitor SW may also be used alone. When used in combination, the master device 2 is coupled to the AXI bus by a bus monitor MW and accesses, for example, a slave device 2 to which a bus monitor SW is coupled. The slave device 2 does not need to be aware of the bus monitor MW and the bus monitor SW but only interacts with the master device 2 according to the AXI protocol. In the example of fig. 4, the presence of the bus monitor MW and the bus monitor SW does not affect the transmission between the master/slave devices not coupled with the bus monitor, e.g. the master N and the slave 1 communicate according to the AXI protocol, without being affected by the bus monitor MW/the bus monitor SW.
Optionally, the bus monitors MW/SW are also coupled to each other in an out-of-band manner (different from the manner of the AXI bus), so that the bus monitors MW communicate information to the bus monitors SW in a manner other than that prescribed by the AXI protocol. For example, the bus monitor MW informs the bus monitor SW (with which it is communicating according to the AXI protocol) in an out-of-band manner upon recognition of an exception and vice versa. So that the bus monitor MW/SW is informed of an abnormality of its communication counterpart even if the AXI bus itself is abnormal.
Optionally, the bus monitor MW/SW also informs the external device (e.g. a processor or controller in the chip) about the recognized exception, so that the external device can perform error handling, such as by restarting the bus, or output exception information to the outside of the chip.
Still alternatively, the abnormality information output by the bus monitor MW/SW may also have its own identification to facilitate fault location or to identify the bus device causing the abnormality. The bus monitor MW/SW may also output one or more write transactions being transmitted on the bus when an exception occurs, thereby further assisting in fault localization.
FIG. 5 illustrates a block diagram of a bus monitor for master write transactions, according to an embodiment of the present application.
A bus monitor for master write transactions (referred to simply as bus monitor MW) couples the master and the AXI bus through the write address channel, write data channel and write response channel of the AXI bus. Logically, a bus monitor MW couples the master to the AXI bus. Physically, a bus monitor MW is located between the master and the bus.
The bus monitor MW monitors signals of the write address channel, the write data channel and the write response channel between the master and the bus to monitor write transactions transmitted on the bus. When a write transaction is normally transmitted on the bus, the bus monitor MW applies the intercepted signal to the bus as it is without affecting the transmission of the transaction. When an exception occurs in a write transaction on a bus, a bus monitor reports the occurrence of the exception and generates a false substitute signal to make the write transaction transmitted on the bus meet the requirements of the AXI protocol to avoid bus fault propagation.
It will be appreciated that the failure may be from a master, bus or accessed slave. After the master device has caused a failure, the bus monitor MW takes over the master device's completion of the transmission of the write transaction to avoid affecting the processing of the write transaction by the bus or slave device. After a failure of the bus or slave, the bus monitor MW takes over the transmission of the write transaction to the bus or slave to avoid affecting the master's processing of the write transaction.
The input signals intercepted by the bus monitor MW include signals from the write address channel, the write data channel and the write response channel. The bus monitor MW also provides the intercepted signals or false substitute signals it generates to the channels or masters. It will be appreciated that on the write address channel the master provides the bus with the address of the write transaction and the bus provides the slave ready signal (AWReady) to the master so that the relevant signal provided by the master indicative of the address of the write transaction is provided as an input to the bus monitor MW and the bus provides the slave ready signal (AWReady) to the master as an input to the bus monitor MW; and the bus monitor MW outputs a correlation signal indicating the address of the write transaction to the bus on the write address channel and a slave ready signal (AWReady) to the master.
Similarly, on the write data channel, the master provides the relevant signal indicating the data to be written by the write transaction as an input to the bus monitor MW, while the bus provides a slave ready signal (WReady) to the master as an input to the bus monitor MW; and the bus monitor MW outputs a correlation signal to the bus on the write data channel indicating the data to be written by the write transaction, and a slave ready signal (WReady) to the master. On the write response channel, the bus provides the relevant signal indicating the response of the write transaction as an input to the bus monitor MW, while the master provides a master ready signal (break) to the bus as an input to the bus monitor MW; and the bus monitor MW outputs a correlation signal indicating the response of the write transaction to the master on the write response channel and a master ready signal (break) to the bus.
The bus monitor MW comprises error signal generating means, monitoring signal generating means, output gating means, memory and optional configuration means.
The error signal generating means of the bus monitor MW captures a write transaction initiated on the write address channel from the write address channel, captures data to be written for the write transaction transmitted on the write data channel from the write data channel, and captures a response to the write transaction from the write response channel. The bus monitor MW identifies the occurrence of an exception according to a long-term absence of capture of complete write data for a write transaction after the write transaction is captured, or the bus monitor MW identifies the occurrence of an exception according to a long-term absence of capture of a response to a write transaction after a complete write data for a write transaction is captured. In response to identifying an exception, the bus monitor MW generates a master exception signal. The generated master exception signal is provided to other components of the bus monitor MW, for example, a monitoring signal generating means and/or an output gating means. The generated master exception signal is also provided outside the bus monitor MW, for example to the CPU of the chip or to a debugging means for fault localization and further processing.
According to the AXI specification, multiple write transactions may be concurrent on the bus. Write transactions with the same ID, need to be responded to sequentially; write transactions with different IDs may be processed out of order. The bus monitor MW identifies for a write transaction marked by an ID whether it is anomalous or not.
Alternatively, referring also to table 3, on the write address channel, the error signal generating means of the bus monitor MW recognize from the write address valid signal (AWValid) that a write transaction has occurred and capture signals such as a write length signal (AWLEN) and/or a write size signal (AWSIZE) associated with the write address valid signal (AWValid). Optionally, the error signal generating means identifies that a write transaction has occurred based on the co-occurrence of a write address valid signal (AWValid) and a slave ready signal (AWReady). Optionally, the error signal generating means identifies the ID of the write transaction from the ID signal (AWID).
On the write data channel, the error signal generation device identifies the write data in which the write transaction occurs according to the write data valid signal (WValid), and identifies the last write data in which the write transaction occurs according to the write data valid signal (WValid) and the last write data signal (WLast) (thereby identifying that the transfer of the write data corresponding to the write transaction is completed). Optionally, the error signal generating means identifies the last data to be written by the occurrence of the write transaction according to the common occurrence of the write data valid signal (WValid), the last write data signal (WLast) and the slave ready signal (WReady). Since there may be more data to be written by a write transaction, the error signal generation mechanism also records the length of data to be written by the write transaction and the length of data that has been transmitted on the write data channel for the write transaction to identify whether the complete data to be written for the write transaction has been captured.
On the write response channel, the error signal generation means recognizes that a response to the write transaction (also referred to as a write response) has occurred from the write response valid signal (BValid). Alternatively, the error signal generation means recognizes that the write response has occurred from a common occurrence of the write response valid signal (BValid) and the master ready signal (break).
According to an embodiment of the application, the bus monitor MW also generates a false substitute signal to avoid other devices of the bus hanging up after an anomaly is identified. In order to generate a spurious substitute signal, in response to a write transaction being captured, the length of data to be written for the write transaction is also recorded in the memory of the bus monitor MW in association with the ID of the write transaction. Optionally, the address of the memory implies the ID of the write transaction. So that the capacity of the memory can accommodate the number of all the concurrently possible write transactions in the bus. For example, if the number of all the concurrently write transactions is the cumulative sum of the maximum capability of the concurrent (Outstanding) transactions per available ID, e.g., there are 16 available IDs and the Outstanding capability per ID is 4, then the memory can hold the relevant data for 64 transactions. It will be appreciated that the outlding capability need not be the same for each ID.
Optionally, information such as the address, data format, etc. of the write transaction is also recorded in the memory. After an exception, the bus monitor MW generates a false substitute signal for each outstanding write transaction to complete the transmission of the write transaction on the AXI bus.
The monitor signal generating means of the bus monitor MW takes over the data transmission of the write address channel, the write data channel and the write response channel in response to the error signal generating means providing the master exception signal. At this time, the master device or the corresponding slave device may be hung up and cannot complete data transmission according to the AXI protocol. In order to avoid subsequent failures of the bus or other bus devices due to propagation of the failure, the monitor signal generation means generates signals conforming to the AXI protocol so that the write transaction being processed is completed. In particular, on the write address channel, the monitor signal generation means indicates to the master that the slave is not ready (by, for example, an invalid AWReady signal) to prevent the master from sending a new write transaction. On the write data channel, the monitor signal generation means ensures for each write transaction being transferred that the complete data it is to write is sent to the slave completion. For example, the monitor signal generating means identifies the amount of complete data to be written by the write transaction and the amount of data sent, and if the amount of complete data to be written by the write transaction is greater than the amount of data sent, the monitor signal generating means generates a dummy substitute signal for sending the data, the dummy substitute signal sending the amount of data for making up the difference between the amount of complete data to be written by the write transaction and the amount of data sent. On the write response channel, the monitor signal generation means generates a false substitute signal to provide a response to the write transaction to the master and a master ready signal (e.g., via a break signal) to the slave.
Optionally, the monitor signal generating means generates a false substitute signal, which is also captured by the error signal generating means. The error signal generating means handles the false substitute signal as part of the write transaction as well, and also overrides the generated master exception signal if it is identified that the exception was generated (e.g. after capturing the complete data to be written for the write transaction, the corresponding response is captured).
The output channel gating means of the bus monitor MW determines whether to provide the write address channel, the write data channel and the write response channel, which are input to the bus monitor MW, to the output of the bus monitor MW, or to provide the dummy substitute signal generated by the monitor signal generating means to the output of the bus monitor MW, depending on whether the error signal generating means provides the master exception signal or not. It will be appreciated that the output of the bus monitor MW is coupled to a bus or master.
The configuration means of the bus monitor MW are optional for providing enable, reset or bypass control signals for the various modules of the bus monitor MW. In response to the presence of the enable signal, the bus monitor MW operates according to the manner described above. If the enable signal is not present, the bus monitor MW couples the incoming write address, write data and write response channel signals directly to the output. In response to the reset signal, the modules of the bus monitor MW start to operate from the initial state, and the generated master exception signal is deasserted. In response to the bypass control signal, the output gating means directly couples the input write address channel, write data channel, and write response channel signals to the output. Optionally, the configuration means also receives an exception signal from the other device indication and in response indicates that the error signal generating means generates a master exception signal.
FIG. 6 illustrates a block diagram of a bus monitor for a slave write transaction according to an embodiment of the present application.
A bus monitor for slave write transactions (referred to simply as a bus monitor SW) couples the slave with the AXI bus through the write address channel, write data channel and write response channel of the AXI bus. Logically, a slave device is coupled to the AXI bus. Physically, the bus monitor SW is located between the slave and the bus.
The bus monitor SW monitors signals of a write address channel, a write data channel, and a write response channel between the slave device and the bus to monitor write transactions transmitted on the bus. When a write transaction is normally transmitted on the bus, the bus monitor SW applies the intercepted signal to the bus as it is without affecting the transmission of the write transaction. When an exception occurs on the bus for a write transaction, the bus monitor SW reports the occurrence of the exception and generates a false substitute signal to make the write transaction transmitted on the bus meet the requirements of the AXI protocol to avoid bus fault propagation.
The bus monitor SW is similar in structure and principle to the bus monitor MW shown in fig. 5, and the same or parts understood by those skilled in the art will not be described again.
The input signals intercepted by the bus monitor SW include signals from a write address channel, a write data channel, and a write response channel. The bus monitor SW also provides the intercepted signals or spurious substitute signals generated by them to the channels.
The bus monitor SW comprises error signal generating means, monitor signal generating means, output gating means and optional configuration means. In contrast to the bus monitor MW, the bus monitor SW may not comprise a memory, since the bus monitor SW according to an embodiment of the present application does not need to generate a signal for complementing the difference of the amount of complete data to be written by a write transaction and the amount of data sent.
The error signal generating means of the bus monitor SW is used to generate a slave abnormality signal. If the situation that the abnormality is generated is recognized to be eliminated, the generated abnormality signal of the slave device is also cancelled.
According to the embodiment of the application, in response to receiving the slave exception signal, the monitoring signal generation means of the bus monitor SW generates no false substitute signal or only the slave ready signal to the write address channel
(AWReady); for the write data channel, the monitor signal generating means generates only a slave ready signal (WReady) at the write data channel; for a write response channel, the monitor signal generation means generates a false substitute signal to provide a response to the write transaction to the master device, optionally with an indication that an error has occurred in the response (e.g., setting the value of the response to Slverr).
Fig. 7A and 7B are block diagrams illustrating an error signal generating apparatus of a bus monitor for write transactions according to an embodiment of the present application.
In the example of fig. 7A, the error signal generating means of the bus monitor includes a write transaction counter, a write data counter, a write response counter, and a timer.
The write transaction counter is coupled to the write address channel to capture write transactions. In response to each capture of a write transaction, a write transaction counter counts. For example, referring also to Table 3, a write transaction is identified as being trapped based on a write address valid signal (AWValid) on the write address channel. As another example, a write transaction is captured based on a write address valid signal (AWValid) and a slave ready signal (AWReady) on a write address channel.
The write data counter is coupled to the write data channel to capture data to be written by the write transaction. In response to each capture of write data, the write data counter counts. The capture of the write data is recognized, for example, from the write data valid signal (WValid) and/or the last write data signal (WLast) on the write data channel. As another example, the capture of write data is identified based on a write data valid signal (WValid), a last write data signal (WLast), and a slave ready signal (WReady) on a write data channel. Optionally, the write data counter counts a number of Burst data transfers (bursts) of write data of the write transaction.
A write response counter is coupled to the write response channel to capture write responses. In response to each capture of a write response, the write response counter counts. For example, the capture of the write response is identified based on a write response valid signal (BValid) on the write response channel. As another example, a write transaction is captured as identified by a write response valid signal (BValid) and a master ready signal (BREAdy) on a write response channel.
The timer couples the write transaction counter, the write data counter, and the write response counter. And in response to the count values of the write transaction counter and the write data counter being not equal, or the count values of the write transaction counter and the write data counter being equal and the count values of the write transaction counter and the write response counter being not equal, the timer counts. The error signal generation means generates a master/slave abnormality signal in response to the count of the timer exceeding a specified threshold value.
The timer is also provided with a reset signal based on signals captured from the write address channel, the write data channel, and/or the write response channel. In response to the reset signal, the timer is cleared or reset.
For the error signal generating means of the bus monitor MW, a reset signal is provided to the timer in response to capturing the write data valid (WValid) from the write data channel and/or capturing the slave ready signal (break) from the write response channel. Optionally, a reset signal is provided to the timer in response to the write transaction counter and the write response counter having the same count value.
For the error signal generating means of the bus monitor SW, a reset signal is provided to the timer in response to capturing a slave ready signal (WReady) from the write data channel and/or capturing a write response valid signal (BValid) from the write response channel. Optionally, a reset signal is provided to the timer in response to the write transaction counter and the write response counter having the same count value.
In one example, there are multiple concurrent (Outstanding) write transactions of the same ID on the bus. These write transactions will be processed sequentially. According to an embodiment of the application, for multiple concurrent write transactions of the same ID, each time a write transaction (with that ID) is captured on the write address channel, the write transaction counter counts; each time the last write data (indicated by WLast) of a burst data transfer corresponding to a write transaction (with that ID) is captured on a write data channel, the write data counter counts; the write response counter counts each time a write response corresponding to a write transaction (with that ID) is captured on the write response channel. And, the write transaction counter, write data counter, write response counter and timer are reset in the manner provided above. Thus, for multiple concurrent (Outstanding) write transactions of the same ID, for multiple Outstanding (Outstanding) write transactions that have been issued, an exception is identified if the complete write data for all of the write transactions is not received for the write transactions within a specified time, or if a write response for all of the write transactions is not received for the write transactions within a specified time.
In the example of fig. 7B, the error signal generating means of the bus monitor provides a write transaction counter, a write data counter, a write response counter and a timer for each available ID of a plurality of write transactions concurrently. The error signal generating means generates a master/slave device abnormality signal in response to any one of the timers corresponding to each ID being timed out. It will be appreciated that for each available ID, it may correspond to one or more concurrent (Outstanding) write transactions.
FIG. 8 shows a block diagram of a monitor signal generation apparatus of a bus monitor for master write transactions according to an embodiment of the present application.
The monitor signal generating means of the bus monitor MW includes write address channel substitution signal generating means, write response channel substitution signal generating means, write data channel substitution signal generating means, and write data length counter. Optionally, the monitor signal generating means further comprises a state machine for controlling the generation of a substitute signal (also referred to as a dummy substitute signal) for each of the plurality of concurrent transactions.
The monitor signal generating means is coupled to the write transaction counter, the write data counter and the write response counter of the error signal generating means. Optionally, the monitoring signal generating device further includes a write transaction counter, a write data counter, and a write response counter, and the write transaction counter, the write data counter, and the write response counter of the monitoring signal generating device operate in the same manner as the corresponding counters of the error signal generating device.
A monitor signal generation apparatus couples the write address channel, the write data channel, and the write response channel and provides a dummy replacement signal to one or more of these channels.
The write data length counter counts the amount of data that has been sent for the write transaction on the write data channel. In one embodiment, even if multiple concurrent write transactions (e.g., multiple concurrent (Outstanding) transactions of the same ID) are to be monitored, the monitor signal generating means includes only one write data length counter since the data transfer process of each write transaction is not inserted into the data transfer process of other write transactions. In another embodiment, the monitor signal generating means comprises a plurality of write data length counters, each write data length counter serving a transaction having an ID corresponding thereto. The write valid signal (WValid) and the slave ready signal (WReady) that occur through the write data channel recognize that the write transaction sent data and accumulate the amount of data sent.
The memory records the amount of complete data to be written by the write transaction. For multiple transactions that are concurrent, the memory records the complete amount of data to be written for each concurrent write transaction.
In response to receiving the master exception signal, the write address channel override signal generation apparatus indicates to the master that the slave is not ready (via, for example, the AWReady signal) on the write address channel to prevent the master from sending a new write transaction. The write data channel replace signal generating means ensures for the write transaction being transferred that the complete data it is to write is sent to the slave completion. For example, if the master exception signal occurs and the complete data to be written for a write transaction has been provided to the slave, then the write data channel substitution signal generating means need not generate a substitution signal for the transaction at the write data channel. Whether the complete data to be written by the write transaction has been provided to the slave device is identified by the value of the write data length counter and the length of the complete data to be written by the write transaction as provided by the memory. For another example, if the master exception signal occurs and the complete data to be written by a write transaction is not completely provided to the slave, the write data channel substitution signal generation device generates a substitution signal in the write data channel to write dummy data into the slave, and the dummy data quantity is used for complementing the difference between the complete data quantity to be written by the write transaction and the sent data quantity. For example, the write data channel substitute signal generating means writes dummy data to the slave by setting a write data signal (WData), a write valve signal (WSTRB), a write valid signal (WValid), a slave ready signal (WReady) signal, and/or a last write data signal (WLast). The write response channel substitute signal generating means generates a false substitute signal on the write response channel to provide a response to the write transaction to the master (e.g., via the BValid signal and the BResp signal) and a master ready signal to the slave (e.g., via the break signal). Optionally, the write response channel replace signal generating means sets the value of the write response signal (Bresp) to indicate a slave device error (Slverr).
If there are a plurality of concurrent write transactions, the write address channel substitution signal generation means, the write response channel substitution signal generation means, and the write data channel substitution signal generation means also generate IDs corresponding to the transactions on the respective channels. In response to the master exception signal, the state machine recognizes that a burst data transfer is currently in progress and the burst data transfer has not been completed, and the write data channel substitution signal generation means generates a substitution signal at the write data channel to write dummy data to the slave device, the dummy data being in an amount to complete the current burst data transfer; next, the state machine control identifies the current concurrent write transaction, and for each of the other concurrent write transactions, identifies again whether the complete data it is to write is provided to the slave device, and if necessary, writes dummy data to the slave device, the amount of dummy data corresponding to the amount of complete data to be written by that write transaction.
In response to the master exception signal, it is identified that there are currently no burst data transfers that have not yet been completed, then the state machine control identifies the current concurrent write transactions, identifies, for each write transaction that is currently concurrent, whether the complete data it is to write is provided to the slave, and if necessary, writes dummy data to the slave, the amount of dummy data corresponding to the amount of complete data to be written by that write transaction.
If for each write transaction that is concurrent, the complete data to be written has already been provided to the slave (including by generating a false substitute signal) and a corresponding response is provided to the master. The monitor signal generating means completes processing of the current master anomaly signal. Optionally, the monitor signal generating means identifies that processing of the current master exception signal is complete in response to the write transaction counter and the write response counter being equal in value.
FIG. 9 shows a block diagram of a monitor signal generation apparatus of a bus monitor for a slave write transaction according to an embodiment of the present application.
The monitor signal generating means of the bus monitor SW includes write address channel substitution signal generating means, write response channel substitution signal generating means, and write data channel substitution signal generating means. Optionally, the monitor signal generating means further comprises a state machine for controlling generation of the substitute signal for each of the plurality of concurrent transactions.
The monitoring signal generating means of the bus monitor SW is similar in structure and principle to the monitoring signal generating means of the bus monitor MW shown in fig. 8, and the same or parts understood by those skilled in the art will not be described again.
In contrast to the bus monitor MW, the monitoring signal generation means of the bus monitor SW may not comprise a write data length counter nor a coupled memory. Since the monitor signal generation means of the bus monitor SW according to the embodiment of the present application generates a false substitute signal to simulate the behavior of a slave device on the AXI bus, only the data to be written by a write transaction is received without generating a signal for complementing the difference between the amount of complete data to be written by the write transaction and the amount of data that has been transmitted.
According to the embodiment of the application, in response to receiving the slave device exception signal, the write address channel replacement signal generation device of the monitoring signal generation device generates a write address channel without generating a false replacement signal or only generates a slave device ready signal (AWReady) to prevent the master device from issuing a new write transaction; the write data channel substitution signal generating means generates only a slave ready signal (WReady) on the write data channel; for the write response channel, the write response channel substitute signal generating means generates a false substitute signal (e.g., BValid signal and BResp signal) to provide the master with a response to the write transaction, optionally with an indication that the slave has made an error (e.g., the value of the response is set to Slverr) in the response. The write response channel replacement signal generating means generates a dummy replacement signal to provide one or more responses to the write transaction to the master device in response to the write transaction counter and the write response counter having the same count value and the write transaction counter and the write response counter having different values until the write transaction counter and the write response counter have the same value.
If there are multiple concurrent write transactions, the monitor signal generating means of the bus monitor SW need not generate a false substitute signal for the ongoing burst transfer to complete the burst transfer. In response to the slave exception signal, the state machine identifies a current concurrent write transaction, and for each concurrent write transaction, if its write transaction counter is different from the value of the write data counter, the write data channel replace signal generating means generates only the slave ready signal (WReady) on the write data channel until the write transaction counter is the same as the value of the write data counter. If the count values of the write transaction counter and the write data counter are the same and the values of the write transaction counter and the write response counter are different, the write response channel substitution signal generation device generates a false substitution signal to provide one or more responses to the write transaction to the master device until the values of the write transaction counter and the write response counter are the same.
While the preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. Therefore, it is intended that the appended claims be interpreted as including the preferred embodiment and all changes and modifications that fall within the scope of the present application. It will be apparent to those skilled in the art that various changes and modifications may be made in the present application without departing from the spirit and scope of the application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations as well.

Claims (10)

1. A bus monitor for coupling a slave device of a bus to the bus, the bus comprising a write address channel, a write data channel, and a write response channel;
the bus monitor comprises an error signal generating device;
the error signal generating means couples the write address channel and the write data channel, the error signal generating means outputting a slave device exception signal in response to no data being captured from the write data channel for a first write transaction within a specified time after the first write transaction is captured from the write address channel;
the error signal generating means is further coupled to a write response channel, and in response to a failure to capture a response to the first write transaction from the write response channel within a specified time after capturing data of the first write transaction from the write data channel, the error signal generating means outputs a slave device exception signal.
2. The bus monitor of claim 1, further comprising a monitor signal generating means;
the monitoring signal generating device is coupled with a write address channel, a write-read data channel and a write response channel, responds to the slave device abnormal signal acquired from the error signal generating device, and indicates the slave device to receive write data to the write data channel if the data of the first write transaction is not captured from the write data channel within a specified time after the first write transaction is captured from the write address channel; if no response is captured from the write response channel to the first write transaction within a specified time after the data of the first write transaction is captured from the write data channel, the monitor signal generation means indicates a response to the first write transaction to the write response channel;
and in response to obtaining the slave exception signal from the error signal generating means, the monitor signal generating means further indicates to the write address channel that a second write transaction is not ready to be received from the write address channel.
3. The bus monitor according to claim 1 or 2,
in response to a number of the plurality of write transactions having the first ID captured from the write address channel not being equal to a number of last data transfers (WLast) of write transactions having the first ID captured from the write data channel, the error signal generation means clocking;
in response to a number of the plurality of write transactions with the first ID captured from the write address channel being equal to a number of last data transfers of the write transactions with the first ID captured from the write address channel and a number of the plurality of write transactions with the first ID captured from the write address channel not being equal to a number of responses to the write transactions with the first ID captured from the write response channel, the error signal generation means is clocked;
a timing reset of the error signal generation means in response to a number of the plurality of write transactions with the first ID captured from the write address channel being equal to a number of responses to the write transactions with the first ID captured from the write response channel, or in response to a response to one of the plurality of write transactions with the first ID captured from the write response channel, or in response to a data transfer to one of the plurality of write transactions with the first ID captured from the write data channel;
in response to timing timeout, the error signal generation means outputs the slave device abnormality signal.
4. The bus monitor of any of claims 1-3, further comprising a configuration device;
the configuration means is for providing an error enable signal to the error signal generating means, a reset signal to the error signal generating means and the monitor signal generating means, and a bypass signal to the output gating means.
5. The bus monitor of any of claims 1-3,
error signal generation means for outputting a slave exception signal in response to no captured response from the write data channel to any of the plurality of write transactions having the first ID within a specified time after capturing the plurality of write transactions having the first ID from the write address channel.
6. A bus monitor for coupling a master device of a bus to the bus;
the bus monitor comprises an error signal generating device;
the error signal generating means couples a write address channel and a write data channel, and in response to no capture of data for a first write transaction from the write data channel within a specified time after capture of the first write transaction from the write address channel, the error signal generating means outputs a master exception signal; and
the error signal generating means is further coupled to a write response channel, and in response to no response being captured from the write response channel to the first write transaction within a specified time after the last data of the first write transaction was captured from the write data channel, the error signal generating means outputs a master exception signal.
7. The bus monitor of claim 6, further comprising a monitor signal generating means;
the monitoring signal generating device is coupled with a writing address channel;
the monitoring signal generating means comprises a memory;
the monitoring signal generation device captures the data length to be written by the first write transaction from the write address channel and stores the data length to be written by the first write transaction in the memory;
the monitor signal generating means captures a length of data written by the first write transaction from the write data channel;
in response to acquiring the master device exception signal from the error signal generation device, if the complete data to be written by the first write transaction is not captured from the write data channel within a specified time after the first write transaction is captured from the write address channel, the monitoring signal generation device acquires the data length to be written by the first write transaction from the memory, and transmits data of the first difference amount through the write data channel according to a first difference between the data length to be written by the first write transaction and the data length written by the first write transaction.
8. The bus monitor of claim 7,
in response to obtaining the master exception signal from the error signal generation means, the monitor signal generation means indicates to the master that it is not ready to receive a second write transaction from the write address channel.
9. The bus monitor of claim 7 or 8, further comprising output gating means;
the output gating device is coupled with a write address channel, a write data channel and a write response channel, and responds to the master device abnormal signal acquired from the error signal generating device, and the output gating device provides data transmitted to a slave device by the monitoring signal generating device through the write data channel to the write data channel of the bus.
10. An electronic system comprising a master device, a slave device, a bus, a master bus monitor, and a slave bus monitor;
the bus provides a write data channel, a write address channel and a write response channel;
the master bus monitor is to couple the master with the bus;
the slave bus monitor is to couple the slave with the bus;
the slave bus monitor is the bus monitor according to any of claims 1-5;
the master bus monitor is a bus monitor according to any of claims 6-9.
CN202110089932.8A 2020-12-01 2021-01-22 AXI bus monitor for write transactions Pending CN114579392A (en)

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Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116932333A (en) * 2023-09-14 2023-10-24 武汉凌久微电子有限公司 AXI bus real-time performance monitoring method for post-silicon verification
CN117435518A (en) * 2023-12-21 2024-01-23 沐曦集成电路(上海)有限公司 Protection method for master-slave read-write data

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN116932333A (en) * 2023-09-14 2023-10-24 武汉凌久微电子有限公司 AXI bus real-time performance monitoring method for post-silicon verification
CN116932333B (en) * 2023-09-14 2023-12-26 武汉凌久微电子有限公司 AXI bus real-time performance monitoring method for post-silicon verification
CN117435518A (en) * 2023-12-21 2024-01-23 沐曦集成电路(上海)有限公司 Protection method for master-slave read-write data
CN117435518B (en) * 2023-12-21 2024-03-22 沐曦集成电路(上海)有限公司 Protection method for master-slave read-write data

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