CN110502377A - It is a kind of that test method is restarted based on CPLD - Google Patents
It is a kind of that test method is restarted based on CPLD Download PDFInfo
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- CN110502377A CN110502377A CN201910729218.3A CN201910729218A CN110502377A CN 110502377 A CN110502377 A CN 110502377A CN 201910729218 A CN201910729218 A CN 201910729218A CN 110502377 A CN110502377 A CN 110502377A
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- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F11/00—Error detection; Error correction; Monitoring
- G06F11/22—Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing
- G06F11/2273—Test methods
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Abstract
The present invention provides a kind of Server Restart test method based on CPLD, comprising the following steps: the switching on and shutting down push button signalling received and the virtual signal Xiang Yuhou generated in response to test instruction are output to PCH by CPLD；The signal that PCH is exported according to CPLD correspondingly sets height or sets low sleep state signals and is switched on or shut down with trigger the server, and the successful signal that will be switched on or shut down transfers back to CPLD；CPLD outputs signals to PCH again and is shut down or be switched on trigger the server in response to receiving the booting or the successful signal of shutdown that PCH is passed back after the period that is delayed.The present invention controls tester table using CPLD, and that realizes single tester table restarts test.
Description
Technical field
The present invention relates to computer fields, and restart test method based on CPLD more particularly, to a kind of.
Background technique
It is exactly constantly to do reboot operation, testing service device to server in the case where AC is not powered off that DC, which restarts test,
Reliability.
In the prior art, mainly using another server as control board, the switching on and shutting down of tester table is controlled, are such as schemed
Shown in 1, real-time monitoring is carried out by off signal of the control board to tester table, when judging power supply status to close, is sent
Power on power-on instruction.Test result is determined, is jumped out after meeting cycle-index.But the operating process is cumbersome, causes resource
Waste；Meanwhile control board can interfere tester table.
Summary of the invention
In consideration of it, the purpose of the embodiment of the present invention is to propose a kind of side for realizing single tester table DC and restarting test
Method, the interference to avoid control board to tester table.
Based on above-mentioned purpose, the one side of the embodiment of the present invention provides a kind of Server Restart test side based on CPLD
Method, comprising the following steps:
Virtual signal phase of the CPLD by the switching on and shutting down push button signalling received to be generated in response to test instruction internal
PCH is output to after；
The signal that the PCH is exported according to the CPLD correspondingly sets height or sets low sleep state signals to trigger the clothes
The booting of business device or shutdown, and the successful signal that will be switched on or shut down transfers back to CPLD；
The CPLD is output signals to after the period that is delayed again in response to receiving booting or the successful signal of shutdown
The PCH is to trigger the server shutdown or booting.
In some embodiments, corresponding switching on and shutting down push button signalling includes the letter from front panel switch machine key
Number, the switching on and shutting down push button signalling from debugging interface and the switching on and shutting down push button signalling from BMC, the switching on and shutting down push button signalling
Low level is effective.
In some embodiments, the virtual signal generated inside the CPLD is configured in the feelings for meeting switching on and shutting down condition
A low level is generated under condition to trigger the server switching on and shutting down.
In some embodiments, the CPLD is delayed the time in response to receiving booting or the successful signal of shutdown
The PCH is output signals to again after section to trigger the server shutdown or be switched on and include:
The CPLD receives the expression that the PCH is passed back and is switched on after successful POST signal, after the first time period that is delayed
The PCH shutdown is triggered according to the switching on and shutting down push button signalling or virtual signal；
After the CPLD detects 12V POWERGOOD power down, again according to the switching on and shutting down after the second time period that is delayed
Push button signalling or virtual signal trigger the PCH booting.
In some embodiments, the method also includes: execute server restart test before preset circulation
Execute the cycle-index of the method.
In some embodiments, the method also includes:
Before each circulation starts, Initialize installation and clock setting are carried out.
In some embodiments, the Initialize installation includes that state machine initializes, signal initializes, register is initial
Change；The clock setting includes that clock generates, Clock Tree generates, signal clock delay.
In some embodiments, the CPLD is by the switching on and shutting down push button signalling received and in response in test instruction
The virtual signal Xiang Yuhou that portion generates is output to PCH and includes:
The CPLD exists corresponding switching on and shutting down push button signalling and the virtual signal generated in response to test instruction internal
After debounce again mutually be then output to PCH.
In some embodiments, the method also includes: the CPLD passes through I for information is tested2C interface is sent to
BMC, to record switch machine information.
In some embodiments, the method can be used for that DC restarts test or AC restarts test.
The present invention has following advantageous effects: provided in an embodiment of the present invention a kind of to restart test side based on CPLD
Method controls tester table using CPLD, realizes single tester table DC and restarts test, avoids control board to survey
Interference and cumbersome operating process caused by commissioning stage DC is restarted in test process, avoid the wasting of resources；It is carried out by CPLD
Power-on and power-off timing control, it is simple to operation.
Detailed description of the invention
In order to more clearly explain the embodiment of the invention or the technical proposal in the existing technology, to embodiment or will show below
There is attached drawing needed in technical description to be briefly described, it should be apparent that, the accompanying drawings in the following description is only this
Some embodiments of invention for those of ordinary skill in the art without creative efforts, can be with
Other embodiments are obtained according to these attached drawings.
Fig. 1 is the flow chart for restart to tester table test by controlling board in the prior art；
Fig. 2 is a kind of flow chart for restarting test method based on CPLD according to the present invention；
Fig. 3 is the schematic diagram according to the present invention for restart based on CPLD test；
Fig. 4 is the flow chart according to an embodiment of the invention for restart based on CPLD test.
Specific embodiment
The following describe the embodiment of the present invention.It should be appreciated, however, that the disclosed embodiments are only example, and
Other embodiments can take various alternative forms.The drawings are not necessarily drawn to scale；Certain functions may be exaggerated or minimum
Change the details to show particular elements.Therefore, specific structure and function details disclosed herein are not necessarily to be construed as restrictive,
And it is merely possible to for instructing those skilled in the art to use representative basis of the invention in various ways.As this field is general
It is logical the skilled person will understand that, the various features with reference to shown or described by any one attached drawing can with it is one or more other
Feature shown in the drawings is combined to produce the embodiment for not being explicitly illustrated or describing.The group of shown feature is combined into typical case
Provide representative embodiment.However, the various combinations and modification of the feature consistent with the teachings of the present invention are for certain spies
Fixed application or embodiment may be desired.
To make the objectives, technical solutions, and advantages of the present invention clearer, below in conjunction with specific embodiment, and reference
The embodiment of the present invention is further described in attached drawing.
Based on above-mentioned purpose, on the one hand the embodiment of the present invention proposes a kind of Server Restart test side based on CPLD
Method, as shown in Figure 2, comprising the following steps:
Step S101: the CPLD by the switching on and shutting down push button signalling received and in response to test instruction internal generation
Virtual signal Xiang Yuhou is output to PCH；
Step S102: the signal that the PCH is exported according to the CPLD correspondingly set height or set low sleep state signals with
The server booting or shutdown are triggered, and the successful signal that will be switched on or shut down transfers back to CPLD；
Step S103: the CPLD, in response to receiving booting or the successful signal of shutdown, is delayed after a period again
The PCH is output signals to trigger the server shutdown or booting.
In some embodiments, corresponding switching on and shutting down push button signalling includes the letter from front panel switch machine key
Number, the switching on and shutting down push button signalling from debugging interface and the switching on and shutting down push button signalling from BMC, opened for the server
Low level is effective when machine.As shown in figure 3, FP_PWRBTN_N is the switching on and shutting down key from Front IO, XDP_PWRBTN_N is
Switching on and shutting down key from XDP, BMC_PWRBTN_N are the switching on and shutting down push button signallings (can be used for remote on-off) from BMC.
In some embodiments, the function of the virtual signal generated inside the CPLD is equal to corresponding switching on and shutting down
Push button signalling, when meeting switching on and shutting down condition, the virtual signal generates a low level to trigger the server booting.Such as
Shown in Fig. 3, Virtual_PWRBTN_N is a virtual key, the same to FP_PWRBTN_N, XDP_PWRBTN_N of function,
BMC_PWRBTN_N signal, it is defined in the variable (not being input to CPLD by other devices) inside CPLD, class
It is similar to a flag.FP_PWRBTN_N, XDP_PWRBTN_N, BMC_PWRBTN_N and Virtual_PWRBTN_N are through CPLD phase
After "AND", PCH_PWRBTN_N signal can be exported to PCH, trigger startup and shutdown.
In some embodiments, the CPLD is delayed a period in response to receiving booting or the successful signal of shutdown
Outputting signals to the PCH again afterwards to trigger the server shutdown or be switched on includes: that the CPLD passes through state machine realization
The control of power-on and power-off timing, wherein the CPLD receives the successful POST signal (BIOS_ of expression booting that the PCH is passed back
POST_CMPLT_N signal) afterwards be delayed first time period after according to the switching on and shutting down push button signalling or virtual signal triggering described in
PCH shutdown, the CPLD detect after the second time period that is delayed after 12V POWERGOOD power down again according to the switching on and shutting down by
Key signals or virtual signal trigger the PCH booting.
In some embodiments, the method also includes: before execute server restarts test preset circulation and hold
The cycle-index of row the method.Every booting, shutdown are once one cycle, and execution restarts test up to the cycle-index.
In some embodiments, before each circulation starts, Initialize installation and clock setting are carried out, it carries out initial
Change setting and clock setting.For example, at the beginning of the Initialize installation may include state machine initialization, signal initialization, register
Beginningization；The clock setting may include that clock generates, Clock Tree generates, signal clock delay.For example, Initialize installation is main
Initialization, the initialization of state machine etc. of initialization, Powergood signal including various enabled Enable signals, are to generation
The constraint of code starting dotted state；Clock setting mainly includes the generation (by way of counting) of clock, the generation of Clock Tree (master
It will be in order to guarantee the homologous of clock, in such a way that control is enabled).
In some embodiments, the method also includes executing to restart test up to the cycle-index.In server first
The virtual signal generated inside corresponding switching on and shutting down push button signalling or the CPLD is directly triggered when secondary booting by the PCH
Trigger the server booting.As shown in figure 4, according to different cycle-indexes, selection triggering compressor start up condition, such as with Virtual_
It for the triggering booting of PWRBTN_N signal, is switched on if it is first time, directly triggering Virtual_PWRBTN_N booting；If no
It is to be switched on for the first time, after monitoring 12V POWERGOOD power down, delay a period of time (such as 30S) triggers Virtual_ afterwards
PWRBTN_N booting.
In some embodiments, the CPLD is by the switching on and shutting down push button signalling received and in response to testing instruction internal
The virtual signal Xiang Yuhou of generation be output to PCH include: the CPLD by the switching on and shutting down push button signalling received and in response to
Test instruction internal generate virtual signal after debounce again mutually be then output to PCH.That is, being realized inside CPLD
Debounce and and Men Gongneng.The mode of adoption status machine time delay realizes signal debounce inside CPLD, is then for example compiled using Verilog
Cheng Shixian phase and assign PCH_PWRBTN_N=FP_PWRBTN_N&XDP_PWRBTN_N&BMC_PWRBTN_N&
Virtual_PWRBTN_N represents 4 signal phases and exports PCH_PWRBTN_N later.
In some embodiments, the method also includes the CPLD passes through I for information is tested2C interface is sent to BMC,
Machine information is switched with record.
In some embodiments, the method can be used for that DC restarts test or AC restarts test.
According to one embodiment of present invention, DC is executed based on CPLD and restarts test, as shown in figure 4, FP_
PWRBTN_N, XDP_PWRBTN_N, BMC_PWRBTN_N, Virtual_PWRBTN_N enter after CPLD, by debounce and door
PCH_PWRBTN_N to PCH is exported later.FP_PWRBTN_N is the switching on and shutting down key from Front IO, XDP_PWRBTN_N
It is the switching on and shutting down key from XDP, BMC_PWRBTN_N is that the switching on and shutting down push button signalling from BMC (can be used for remote switch
Machine), Virtual_PWRBTN_N is a virtual key, it by generating inside CPLD, function be equal to FP_PWRBTN_N,
XDP_PWRBTN_N, BMC_PWRBTN_N signal, low level are effective.When any one PWRBTN for entering CPLD triggers low level
When (switch is pressed as low level), PCH_PWRBTN_N signal is low level.
For example, when executing switching on and shutting down test using Virtual_PWRBTN_N signal, when meeting compressor start up condition,
Virtual_PWRBTN_N generates a lasting 20ms low level, triggering booting.PCH monitors to send after the completion of system electrification
BIOS_POST_CMPLT_N is to CPLD.CPLD receives the 30 seconds triggering Virtual_ that are delayed after BIOS_POST_CMPLT_N
PWRBTN_N shutdown.CPLD passes through I for information is tested2C interface is sent to BMC, record switch machine information.After the completion of the above process
Cycle-index adds 1, judges whether to reach cycle-index be then switched on next time before, if not up to cycle-index, repeats above-mentioned
Process；If reaching cycle-index, the circulatory system is exited.
Technically in feasible situation, it can be combined with each other above in relation to technical characteristic cited by different embodiments,
Or change, add and omit etc., to form the additional embodiment in the scope of the invention.
From above-described embodiment as can be seen that a kind of test method of restarting based on CPLD provided in an embodiment of the present invention uses
CPLD controls tester table, realizes single tester table DC and restarts test, avoids control board to tester table
Interference and cumbersome operating process caused by DC is restarted in test process, avoid the wasting of resources；Power-on and power-off are carried out by CPLD
Timing control, it is simple to operation.
Finally, it should be noted that those of ordinary skill in the art will appreciate that realizing the whole in above-described embodiment method
Or part process, related hardware can be instructed to complete by computer program, the program can be stored in computer can
It reads in storage medium, the program is when being executed, it may include such as the process of the embodiment of above-mentioned each method.Wherein, described to deposit
Storage media can be magnetic disk, CD, read-only memory (ROM) or random access memory (RAM) etc..
In addition, typically, it can be various electric terminal equipments, example that the embodiment of the present invention, which discloses described device, equipment etc.,
Such as mobile phone, personal digital assistant (PDA), tablet computer (PAD), smart television, are also possible to large-scale terminal device, such as service
Device etc., therefore protection scope disclosed by the embodiments of the present invention should not limit as certain certain types of device, equipment.The present invention is real
Apply example disclose the client can be applied to the combining form of electronic hardware, computer software or both it is above-mentioned any
In a kind of electric terminal equipment.
In addition, disclosed method is also implemented as the computer program executed by CPU according to embodiments of the present invention, it should
Computer program may be stored in a computer readable storage medium.When the computer program is executed by CPU, the present invention is executed
The above-mentioned function of being limited in method disclosed in embodiment.
In addition, above method step and system unit also can use controller and for storing so that controller is real
The computer readable storage medium of the computer program of existing above-mentioned steps or Elementary Function is realized.
In addition, it should be appreciated that computer readable storage medium (for example, memory) as described herein can be it is volatile
Property memory or nonvolatile memory, or may include both volatile memory and nonvolatile memory.As example
And not restrictive, nonvolatile memory may include read-only memory (ROM), programming ROM (PROM), electrically programmable to son
ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory.Volatile memory may include arbitrary access
Memory (RAM), the RAM can serve as external cache.As an example and not restrictive, RAM can be with more
Kind form obtains, such as synchronous random access memory (DRAM), dynamic ram (DRAM), synchronous dram (SDRAM), double data rate SDRAM
(DDR SDRAM), enhancing SDRAM (ESDRAM), synchronization link DRAM (SLDRAM) and directly Rambus RAM (DRRAM).
The storage equipment of disclosed aspect is intended to the memory of including but not limited to these and other suitable type.
Those skilled in the art will also understand is that, various illustrative logical blocks, mould in conjunction with described in disclosure herein
Block, circuit and algorithm steps may be implemented as the combination of electronic hardware, computer software or both.It is hard in order to clearly demonstrate
This interchangeability of part and software, with regard to various exemplary components, square, module, circuit and step function to its into
General description is gone.This function is implemented as software and is also implemented as hardware depending on concrete application and application
To the design constraint of whole system.Those skilled in the art can realize described in various ways for every kind of concrete application
Function, but this realization decision should not be interpreted as causing a departure from range disclosed by the embodiments of the present invention.
Various illustrative logical blocks, module and circuit, which can use, in conjunction with described in disclosure herein is designed to
The following component of function described here is executed to realize or execute: general processor, digital signal processor (DSP), dedicated collection
At circuit (ASIC), field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, divide
Any combination of vertical hardware component or these components.General processor can be microprocessor, but alternatively, processing
Device can be any conventional processors, controller, microcontroller or state machine.Processor also may be implemented as calculating equipment
Combination, for example, the combination of DSP and microprocessor, multi-microprocessor, one or more microprocessors combination DSP and/or any
Other this configurations.
The step of method in conjunction with described in disclosure herein or algorithm, can be directly contained in hardware, be held by processor
In capable software module or in combination of the two.Software module may reside within RAM memory, flash memory, ROM storage
Device, eprom memory, eeprom memory, register, hard disk, removable disk, CD-ROM or known in the art it is any its
In the storage medium of its form.Illustrative storage medium is coupled to processor, enables a processor to from the storage medium
Information is written to the storage medium in middle reading information.In an alternative, the storage medium can be with processor collection
At together.Pocessor and storage media may reside in ASIC.ASIC may reside in user terminal.It is replaced at one
In scheme, it is resident in the user terminal that pocessor and storage media can be used as discrete assembly.
In one or more exemplary designs, the function can be real in hardware, software, firmware or any combination thereof
It is existing.If realized in software, can be stored in using the function as one or more instruction or code computer-readable
It is transmitted on medium or by computer-readable medium.Computer-readable medium includes computer storage media and communication media,
The communication media includes any medium for helping for computer program to be transmitted to another position from a position.Storage medium
It can be any usable medium that can be accessed by a general purpose or special purpose computer.As an example and not restrictive, the computer
Readable medium may include RAM, ROM, EEPROM, CD-ROM or other optical disc memory apparatus, disk storage equipment or other magnetic
Property storage equipment, or can be used for carry or storage form be instruct or data structure required program code and can
Any other medium accessed by general or specialized computer or general or specialized processor.In addition, any connection is ok
It is properly termed as computer-readable medium.For example, if using coaxial cable, optical fiber cable, twisted pair, digital subscriber line
(DSL) or such as wireless technology of infrared ray, radio and microwave to send software from website, server or other remote sources,
Then above-mentioned coaxial cable, optical fiber cable, twisted pair, DSL or such as wireless technology of infrared ray, radio and microwave are included in
The definition of medium.As used herein, disk and CD include compact disk (CD), laser disk, CD, digital versatile disc
(DVD), floppy disk, Blu-ray disc, wherein disk usually magnetically reproduce data, and CD using laser optics reproduce data.On
The combination for stating content should also be as being included in the range of computer-readable medium.
It should be understood that it is used in the present context, unless the context clearly supports exceptions, singular " one
It is a " it is intended to also include plural form.It is to be further understood that "and/or" used herein refers to including one or one
Any and all possible combinations of a above project listed in association.
It is for illustration only that the embodiments of the present invention disclose embodiment sequence number, does not represent the advantages or disadvantages of the embodiments.
Those of ordinary skill in the art will appreciate that realizing that all or part of the steps of above-described embodiment can pass through hardware
It completes, relevant hardware can also be instructed to complete by program, the program can store in a kind of computer-readable
In storage medium, storage medium mentioned above can be read-only memory, disk or CD etc..
Above-described embodiment is the possibility example of embodiment, and is mentioned just to be clearly understood that the principle of the present invention
Out.It should be understood by those ordinary skilled in the art that: the discussion of any of the above embodiment is exemplary only, it is not intended that dark
Show that range disclosed by the embodiments of the present invention (including claim) is limited to these examples；Under the thinking of the embodiment of the present invention,
It can also be combined, and exist present invention as described above between technical characteristic in above embodiments or different embodiments
Many other variations of the different aspect of embodiment, for simplicity, they are not provided in details.Therefore, all of the invention real
It applies within the spirit and principle of example, any omission, modification, equivalent replacement, improvement for being made etc. should be included in implementation of the present invention
Within the protection scope of example.
Claims (10)
1. a kind of Server Restart test method based on CPLD, which comprises the following steps:
The CPLD by the switching on and shutting down push button signalling received and in response to test instruction internal generate virtual signal phase with
After be output to PCH；
The signal that the PCH is exported according to the CPLD correspondingly sets height or sets low sleep state signals to trigger the server
Booting or shutdown, and the successful signal that will be switched on or shut down transfers back to CPLD；
The CPLD is output signals to after the period that is delayed again in response to receiving the booting or the successful signal that shuts down
The PCH is to trigger the server shutdown or booting.
2. the method according to claim 1, wherein corresponding switching on and shutting down push button signalling includes coming from front
The signal of switching plate machine key, the switching on and shutting down push button signalling from debugging interface and the switching on and shutting down push button signalling from BMC, institute
It is effective to state switching on and shutting down push button signalling low level.
3. according to the method described in claim 2, it is characterized in that, the virtual signal generated inside the CPLD is configured to full
A low level is generated in the case where sufficient switching on and shutting down condition to trigger the server switching on and shutting down.
4. according to the method described in claim 3, it is characterized in that, the CPLD in response to receive it is described booting or shutdown at
The signal of function outputs signals to the PCH after the period that is delayed to trigger the server shutdown or be switched on and include: again
The CPLD receives the expression that the PCH is passed back and is switched on after successful POST signal, basis after the first time period that is delayed
The switching on and shutting down push button signalling or virtual signal trigger the PCH shutdown；
After the CPLD detects 12V POWERGOOD power down, again according to the switching on and shutting down key after the second time period that is delayed
Signal or virtual signal trigger the PCH booting.
5. the method according to claim 1, wherein the method also includes: restart test in execute server
The cycle-index that circulation executes the method is preset before.
6. according to the method described in claim 5, it is characterized in that, the method also includes:
Before each circulation starts, Initialize installation and clock setting are carried out.
7. according to the method described in claim 6, it is characterized in that, the Initialize installation includes state machine initialization, signal
Initialization, initialization of register；The clock setting includes that clock generates, Clock Tree generates, signal clock delay.
8. the method according to claim 1, wherein the CPLD by the switching on and shutting down push button signalling received and
Being output to PCH in response to the virtual signal Xiang Yuhou that test instruction internal generates includes:
The CPLD is passing through corresponding switching on and shutting down push button signalling and the virtual signal generated in response to test instruction internal
After debounce again mutually be then output to PCH.
9. leading to the method according to claim 1, wherein the method also includes: the CPLD by information is tested
Cross I2C interface is sent to BMC, to record switch machine information.
10. the method according to claim 1, wherein the method can be used for, DC restarts test or AC restarts survey
Examination.
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| CN201910729218.3A CN110502377B (en) | 2019-08-08 | 2019-08-08 | Restarting test method based on CPLD |
| PCT/CN2019/121108 WO2021022721A1 (en) | 2019-08-08 | 2019-11-27 | Cpld-based restart test method |
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| CN201910729218.3A CN110502377B (en) | 2019-08-08 | 2019-08-08 | Restarting test method based on CPLD |
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| CN111767174A (en) * | 2020-06-30 | 2020-10-13 | 西安易朴通讯技术有限公司 | BIOS (basic input output System) refreshing control method, server and storage medium |
| WO2021022721A1 (en) * | 2019-08-08 | 2021-02-11 | 苏州浪潮智能科技有限公司 | Cpld-based restart test method |
| CN112506726A (en) * | 2020-12-11 | 2021-03-16 | 浪潮电子信息产业股份有限公司 | System AC test method, device and system based on Feiteng processor |
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| CN113626270A (en) * | 2021-08-17 | 2021-11-09 | 浪潮商用机器有限公司 | Server switch testing method, system and device, storage medium and starting device |
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