JPH0666764B2 - Digital transmission terminal equipment - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Outline] A monitored circuit inserted between transmission lines, a reference circuit for inversely converting output data converted by the monitored circuit, data to the monitored circuit, and a reference circuit The present invention relates to a digital transmission terminal device provided with a bit collating circuit for bit collating with output data, and an object thereof is to enable bit collation by discriminating between a transmission line fault and a device fault at the time of receiving an AIS signal. , A bit collating circuit performs a phase synchronization pull-in part, a bit error detection part detecting a bit error pulse from both outputs of the phase synchronization part, and a pull-in control of the phase synchronization part by the bit error pulse And a control unit that performs bit error measurement for a certain period of time and generates a switching output to the standby system when there is a bit error. After completion of the phase synchronization pull-in, even if both input signals to the phase synchronization unit are relatively shifted by at least 1 bit, when the phase synchronization pull-in is completed again, it is determined that the AIS signal is in the state and the bit error measurement is not performed. To configure.

[Industrial application field]

The present invention relates to a digital transmission terminal device, and more particularly to a monitored circuit inserted between transmission lines, a reference circuit for inversely converting output data converted by this monitored circuit, data to the monitored circuit and a reference circuit. The present invention relates to a digital transmission terminal station device provided with a bit collating circuit for bit collating with the output data of.

The bit collating circuit used in such a digital transmission terminal station device is a circuit for detecting a bit error of a transmission signal generated due to a failure of the digital transmission terminal device,
When the bit error is detected, the active system and the standby system are switched.

Therefore, since the line is momentarily disconnected due to switching the circuit system, it is necessary to accurately detect the bit error.

[Conventional technology]

FIG. 5 shows a conventionally used digital transmission terminal device, in which 1 is a monitored object such as a multiplexing (MUX) circuit or a separation (DMUX) circuit inserted between transmission lines I and II. Reference numeral 2 denotes a reference circuit for inversely converting the output data converted by the monitored circuit 1 (if the monitored circuit is a multiplexing circuit, it is a separation circuit, and if the monitored circuit is a separation circuit, it is a multiplexing circuit). , And 3 are bit collating circuits for bit collating the data to the monitored circuit 1 with the output data of the reference circuit 2. The bit collating circuit 3 includes a phase synchronization unit 31 that inputs both data and performs phase synchronization pull-in, a bit error detection circuit 32 that detects a bit error of both data output from the phase synchronization unit 31, and this bit. The control unit 33 receives the error bit detected by the error detection unit 32, generates a control signal for controlling the phase synchronization unit 31, and generates a working-preliminary switching signal according to the bit collation result. There is.

The operation of the digital transmission terminal station device shown in FIG. 5 will be described below.

The signal A sent from the transmission line I is converted into the signal B by the monitored circuit 1 and sent to the transmission line II. The signal B is converted into the signal C by the reference circuit 2 in the opposite conversion to that of the monitored circuit 1.

Here, if the two circuits 1 and 2 are operating normally, the signals A and C should have exactly the same waveform, but the signal C passes through the two circuits 1 and 2 more than the signal A. Therefore, the phase is behind that of the signal A.

Therefore, in order to synchronize the phase with the signal C, the signal A may be intentionally delayed. This phase synchronization is called "pull-in".

This pull-in operation is performed by the phase synchronization unit 31, the bit error detection unit 32, and the control unit 33, which form the bit collation circuit 3.
In the phase synchronization unit 31, the signal A is delayed and output, and the signal C is output without delay. Then, these output signals are compared by the bit error detection unit 32, and if they do not match, an error pulse D is generated and the control unit 3
Send to 3.

A specific circuit configuration of the phase synchronization unit 31 and the bit error detection unit 32 is shown in FIG. 6A, and signals A and C are flip-flops (hereinafter abbreviated as FF) 311 and 312, respectively. The signal C is taken in via the elastic memory (ERST MEM) 313 and is read by the transmission path clock of the signal A. The signal A is delayed by the fixed delay circuit 314 and sent to the variable delay circuit 315.

Here, the breakdown of the delay amount of the signal C with respect to the signal A is the absolute fixed "fixed delay" due to the delay of the gate in the circuit and the FF, and the floating due to the monitored circuit 1, the reference circuit 2, the elastic memory 313, and the like. "Variable delay".

Therefore, the phase synchronization unit 31 adds a fixed delay and a variable delay corresponding to this delay amount to the signal A, and the variable delay circuit 315, as shown in FIG. And a selector for the outputs of all of these n stages, and the delay amount is selected by a select signal.
The select signal is given from the control unit 33 as described later.

The delayed signal A output from the variable delay circuit 315 and the elastic memory 313 and non-delayed (FF
(Except for memory and memory delay) Signal C is bit error detector 3
Sent to 2. As shown in FIG. 6 (a), this bit error detection unit 32 has an exclusive OR gate (ExOR) 321.
The exclusive OR gate 321 has a signal obtained by delaying the signal A by the fixed delay circuit 314 and the variable delay circuit 315, and a signal from the memory 313 in which the signal C is temporarily stored. And are input and compared, and as a mismatch signal, FF322
Is input to, and is beaten by the transmission line clock and becomes a signal via the AND gate 323. The pulse waveform of the bit error detector 32 is shown in FIGS. 7 (a) to 7 (c).

FIG. 8 shows a flow chart of the program stored in the control unit 33. The operation of the bit collating circuit in the conventional digital transmission terminal equipment will be described with reference to this flow chart. First, the control unit 33 performs phase synchronization pull-in. Perform (step S1 in FIG. 8).

This phase synchronization pull-in routine is shown in FIG. 9. When this routine is started, first "n = 0" (step S11 in FIG. 9) and the variable delay circuit 3 in FIG. 6 is set.
The select signal for the selector SL of 15 outputs 0-bit delay, that is, phase synchronization data that is not delayed.

Next, the counting of the bit error pulse D, that is, the error bits of the signals of FIGS. 6 and 7 is started (at the same step S
12) The count is continued for a fixed count time, that is, the phase synchronization pull-in time (step S13). Then, after the pull-in time has elapsed, the counting is ended (at step S14) and it is checked whether or not there is a bit error (at step S15). If there is an error n =
As n + 1 (at step S16), a select signal is given to the selector SL to select the 1-bit delayed output by one FF and output it as phase synchronization data. Then, the above steps S2 to S5 are repeatedly executed. this is,
The process is repeated until the bit error pulse D disappears, and the phase lock pull-in is completed when the bit error pulse D becomes zero (step S17).

The state of this phase synchronization pull-in is shown in the waveform of FIG. 7. In FIG. 7 (a), when the phase difference (change) between the signal A and the signal C is 2 bits, FIG. 7 (b) shows When the phase difference is corrected to 1 bit, FIG. 7 (c) shows the case where the pull-in is completely completed.

In this way, the phase synchronization pull-in routine ends, but normally the pull-in is rarely completed as shown in FIG. 7C, and whether the pull-in was possible at the bit rate (BER) within the pull-in time described above. Determine whether or not. Therefore, the bit error rate is measured (step S2 in FIG. 8), and it is checked whether or not it can be determined that the bit error rate can be pulled in (step S3), and the measured bit error rate is the bit error rate threshold BER.
_When it exceeds _P , a signal for switching the active system to the standby system is generated because it is impossible to pull in and there is a device failure (step S7).

When the measured bit error rate is less than or equal to the threshold value BER _P , it is determined that the pull-in is successful, and this time, the time longer than the pull-in time is set and the bit error rate is measured again (step S4). Also in this case, if it exceeds the other bit error rate threshold BER _M , a switching signal is generated (step S7), and if it is less than the threshold BER _M , it is determined that there is no device failure and the next system or Channel bit matching is performed (step S6).

Here, BER _M <BER _P , and pull-in determination time <error measurement time. This is because if the pull-in determination time is increased, the pull-in determination is delayed, so that the pull-in determination is once made, the determination is once made in a short pull-in time, and then the error measurement is performed in a longer time to detect a reliable device failure.

[Problems to be solved by the invention]

In the digital transmission terminal device as described above, the transmission signal A is an AIS (Alarm Indication Signal) signal (for example, a signal of all "1" indicating that the device connected to the transmission line I is in an unused state). In the case of (), there was a problem that it was mistakenly determined to be a device failure.

That is, when the signal from the transmission line I is an AIS signal and a bit error occurs due to an abnormality in the transmission line I as shown in FIG. 10, when the phase is adjusted by the pull-in operation, the signal A And C are the same "1" and the pull-in determination time is relatively short, so the bit error pulse D
Is rarely generated, so the bit error rate is the threshold BER.
It is judged to be _P or less and the phase is synchronized,
In the error measurement (step S4 in FIG. 8), since the error pulse D is counted for a time longer than the pull-in determination time, the error pulse D is detected during this period, and if the bit error rate exceeds the threshold value BER _M , the bit error is detected. If there is a transmission line fault, it will be judged as a device fault and the circuit will be switched. This is the same when the signal A is all "0" signals.

Therefore, the present invention provides a monitored circuit inserted between transmission lines, a reference circuit for inversely converting output data converted by the monitored circuit, data to the monitored circuit, and output data of the reference circuit. An object of the present invention is to make it possible to perform bit collation by discriminating between a transmission line fault and a device fault at the time of receiving an AIS signal in a digital transmission terminal device provided with a bit collating circuit for bit collating.

[Means for solving problems]

The configuration of the digital transmission terminal station apparatus according to the present invention for achieving the above object can use the configuration of FIG. 5 as it is, and in particular, in the present invention, the control unit 33 controls the phase synchronization unit 31 After the phase synchronization pull-in control of the input signals A and C to the phase synchronization unit 31 is completed based on the bit error pulse detected by the bit error detection unit 32 from one output, at least the input signal of the phase synchronization unit 31 is relatively When the phase lock pull-in is completed even if it is shifted by 1 bit, the input signal of this digital transmission terminal station device is judged to be the AIS signal and the bit error measurement is not performed.

[Action]

FIG. 1 is a flow chart conceptually showing the control algorithm of the control unit 33 of the bit matching circuit in the digital transmission terminal station apparatus according to the present invention shown in FIG. 5, and this control algorithm is shown in FIG. 2 (when an AIS signal is received). Waveform diagram) and FIG. 3 (waveform diagram during normal data reception).

First, when an AIS signal is received, when there is no transmission path trouble and there is no bit error in the received signal, the waveform becomes as shown in FIG. 2 (a).

Even if a sudden bit error occurs due to a transmission path failure at the time of receiving an AIS signal as shown in FIG. 2 (b), since the pull-in determination time in the phase lock pull-in control is short, the bit error rate is below the threshold value. Next, the pull-in control is completed (step T1 in FIG. 1).

As a result, this is the same as the case of FIG. 2 (a), but if the bit error measurement is continued as it is, the bit error rate exceeds the threshold value even if it is a sudden bit error because the detection period is long. There is a risk that it may be judged as a device failure. Therefore, in the present invention, the control signal from the control unit 33 to the phase synchronization unit 31 shifts by at least 1 bit and the phase synchronization pull-in is performed again (step T2).
And the waveform diagram of FIG. 2 (c)).

And, even if at least one bit is shifted in this way, the second
When the pull-in operation is completed as shown in FIG.
The input signal of this digital transmission terminal device is judged to be the AIS signal, and bit error measurement is not performed (step T3 in FIG. 1), and the bit collating operation is ended.

〔Example〕

Embodiments of the digital transmission terminal station device according to the present invention will be described below.

The digital transmission terminal station device of the present invention can also use the configuration shown in FIG. Therefore, the description of the configuration of the device itself is omitted.

FIG. 3 is a flow chart showing an embodiment of a program stored and executed in the control unit 33 of the bit collating circuit 3 used in the digital transmission terminal station device of the present invention. Hereinafter, the digital transmission terminal station device of the present invention will be described. The embodiment will be described with reference to FIGS. 3 and 5. In the flowchart of FIG. 2, the same steps as those in the flowchart of FIG. 8 are designated by the same reference numerals and the description thereof will be omitted.

First, the phase synchronization pull-in of the input data signals A and C and the measurement of the bit error rate are performed (step S in FIG. 3).
1, S2), it is further determined whether or not the pull-in is possible (step S3), and when it is determined that the pull-in cannot be performed, a signal for switching to the standby system is generated as shown in FIG. 4 (a). (Step S7).

As shown in FIG. 4 (b), when the bit error rate at the time of phase synchronization pull-in is equal to or less than the threshold value and it is determined that the phase synchronization pull-in is completed, the control unit used in the present invention surrounded by a dotted line in FIG. The step 33 is executed, and in this embodiment, the input signal A of the phase synchronizer 31 is shifted by one bit to perform the phase lock pull-in (step T11).
This bit shifting may be delayed or advanced.

After shifting by 1 bit, the bit error rate at the time of pulling in is determined (at step T12). As a result, when it is determined that the bit error rate is smaller than the threshold value BER _P as shown in FIG. 2 and the pull-in is possible (no pull-in error), the input signal A is regarded as the AIS signal and the following bit error occurs. The measurement is not performed and the bit matching operation is ended, and the bit matching operation of the next system or channel is started.

On the other hand, as a result of the pull-in determination, as shown in FIG. 4 (c), when the bit error rate exceeds the threshold value BER _P , it is determined that the input signal A is normal data and shown in FIG. 4 (d). As described above, the control signal for returning the one-bit data signal A to the original is given as a select signal from the control unit 33 to the variable delay circuit 315 of the phase synchronization unit 31 (at the same step T).
13).

After this, the same steps as in FIG. 8 are executed, but if there is no bit error (the bit error rate is less than or equal to the threshold value BER _M ) as shown in FIG. 4 (d) as a result of returning 1 bit as described above. Although it is determined that there is no device failure in steps S4 to S6, if it is determined that there is still a bit error even after returning, it is determined that there is a device failure and a signal for switching to the backup system is generated (step S7).

In the above embodiment, the possibility of phase synchronization is determined again by shifting by 1 bit, but it is needless to say that the same can be done by shifting by a plurality of bits unless the phases are matched as a result of the shifting.

〔The invention's effect〕

As described above, according to the digital transmission terminal station device of the present invention, after the phase lock pull-in, the relative bit shift of the input signal is performed before the bit error measurement, the phase lock pull-in determination is performed again, and the pull-in is performed. When it is determined that the input signal is the AIS signal, the bit error detection is performed so that the bit error detection is not performed. Therefore, the bit error due to the transmission line failure in the AIS signal state is determined as the device error. Therefore, it is possible to prevent the malfunction of switching to the standby system and avoid the instantaneous interruption of the transmission signal.

[Brief description of drawings]

FIG. 1 is a flowchart conceptually showing a bit matching algorithm of a digital transmission terminal station apparatus according to the present invention, and FIG. 2 is an AIS of a digital transmission terminal station apparatus according to the present invention.
FIG. 3 is a waveform diagram for explaining a bit collation algorithm at the time of signal, FIG. 3 is a flow chart diagram of a program as one embodiment executed by a control unit in a bit collation circuit of a digital transmission terminal device according to the present invention, FIG. 4 is a waveform diagram for explaining the operation of the bit collating circuit used in the present invention when the input signal is normal data, and FIG. 5 is the hardware of the digital transmission terminal device applied to the present invention and the conventional example. FIG. 6 is a hardware configuration diagram of the phase synchronization unit and the bit error detection unit in the bit collating circuit of the digital transmission terminal device applied to the present invention and the conventional example, and FIG. 7 is a diagram of FIG. FIG. 8 is a waveform diagram for explaining the circuit operation, FIG. 8 is a flow chart diagram of a program executed by the control unit in the bit matching circuit of the conventional digital transmission terminal device, and FIG. FIG. 10 is a flow chart showing a phase synchronization pull-in routine used in a conventional example, and FIG. 10 is a waveform diagram for explaining a bit error due to a transmission path failure at the time of an AIS input signal. In the figure, 1 ... Monitored circuit, 2 ... Reference circuit, 3 ... Bit matching circuit, 31 ... Phase synchronization unit, 32 ... Bit error detection unit, 33 ... Control unit. In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (2)

[Claims] 1. A monitored circuit (1) inserted between transmission lines,
A reference circuit (2) for inversely converting the output data converted by the monitored circuit (1), and a bit for bit-matching the data to the monitored circuit (1) with the output data of the reference circuit (2). Matching circuit
(3), the bit collating circuit (3), the phase synchronization unit for performing phase synchronization pulling (31), and a bit error detection unit for detecting a bit error pulse from both outputs of the phase synchronization unit (31)
(32) and the phase synchronization unit (31) by the bit error pulse
In the digital transmission terminal station device including a control unit (33) that performs the pull-in control of the device, performs bit error measurement for a certain period of time, and generates a switching output to the standby system when there is a bit error. 33), when the phase synchronization pull-in is completed again even if both input signals to the phase synchronization unit (31) are relatively shifted by at least 1 bit after completion of the phase synchronization pull-in,
A digital transmission terminal station device characterized in that it is judged to be in a signal state and the bit error measurement is not performed. 2. The control unit (33), when the phase shift pull-in cannot be performed when the bit shift is performed, restore the bit number to the original and perform the bit error measurement. The digital transmission terminal station device according to claim 1.