JPH08330924A - Detection circuit for pulse period abnormality - Google Patents

Abstract

PURPOSE: To provide a circuit which detects the period abnormality of an input signal. CONSTITUTION: When the period of a frame synchronized signal SYNC is reduced shorter than the time width of the output signal S12 of a multivibrator 12, the output signal S14 of a multivibrator 14 is kept at 'L' for a prescribed time from the changing point of the signal SYNC and inputted to the 1st input terminal of an AND circuit 15. At the same time, a signal of 'H' is inputted to the 2nd input terminal of the circuit 15 from a multivibrator 11. Therefore, the logical level of the output terminal of the circuit 15 is set at 'L'. When the period of the signal SYNC exceeds the time width of the output signal S11 of a multivibrator 11, the signal S14 is set at 'H'. Then the signal S11 is kept at 'L' until the input of the next changing point of the SYNC. Thus the logical level of the output terminal of the circuit 15 is set at 'L'.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a pulse cycle abnormality detection circuit in an apparatus which operates by receiving a pulse such as a frame synchronization signal for system operation from a synchronization signal generator.

[0002]

2. Description of the Related Art FIG. 2 is a circuit diagram showing a configuration example of a conventional pulse period abnormality detection circuit. This pulse cycle abnormality detection circuit has an input terminal IN for inputting a frame synchronization signal SYNC supplied from a synchronization signal generator (not shown), and the input terminal IN is connected to the trigger input terminal TG of the mono-multivibrator 1. The output side of the mono multivibrator 1 is connected to the output terminal OUT. Further, the terminal t1 of the monomultivibrator 1 is connected to the terminal t2 via the capacitor C1, and the terminal t2 is connected to the power supply potential Vcc via the resistor R1. The mono-multivibrator 1 has a time T2 that is determined by the time constant of the capacitor C1 and the resistor R1 which is slightly longer than the cycle T1 of the frame synchronization signal SYNC from the change point (that is, the rising edge) of the input frame synchronization signal SYNC. High level only (below,
This circuit outputs the output signal S1 of "H").
However, when a new change point (rising edge) is input to the trigger input terminal TG during the time T2 during which "H" is output, the mono-multivibrator 11 operates during the time T2 from that point. It is a retriggerable mono-multivibrator that outputs "H". FIG. 3 is a time chart showing the operation of FIG. 2, in which the vertical axis represents the logic level and the horizontal axis represents time. The operation of FIG. 1 will be described with reference to this figure. The mono-multivibrator 1 has the trigger input terminal T before the time T2 for outputting "H" ends.
Since the change point (rising edge) of the frame synchronization signal SYNC is newly input to G, the output signal S1 of "H" is always output.

[0003]

However, the pulse period abnormality detection circuit of FIG. 2 has the following problems. That is, since the mono multivibrator 1 detects the presence or absence of a change point of the frame synchronization signal SYNC, the period T1 of the frame synchronization signal SYNC may be the monomultivibrator 1 for some reason, such as a malfunction of the synchronization signal generator. When the pulse generation time T2 is longer than the pulse generation time T2, the output signal S1 becomes low level (hereinafter, referred to as "L"), which is detected as "disconnection" of the frame synchronization signal SYNC. However, when the cycle T1 of the frame synchronization signal SYNC becomes short for some reason, for example, when noise is superimposed on the frame synchronization signal SYNC, the output signal S1 is always "H", and It was not detected as an abnormality. That is, in FIG. 2, when T1> T2, the abnormality of the frame synchronization signal SYNC is detected, and when 2T1 <T2, the abnormality of the frame synchronization signal SYNC is not detected.

[0004]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a pulse cycle abnormality detection circuit, comprising:
From the second logic level of the input signal of a constant period in which the second logic level time is longer than the second logic level time.
Detecting a first transition which is a transition to the logic level and generating an output signal having a time width which is equal to or more than the cycle of the input signal and is less than or equal to twice the cycle of the input signal at each time of the first transition. The first pulse generating means is provided. Further, the pulse period abnormality detection circuit further includes a second transition that is a transition from the first logic level of the input signal to the second logic level.
Of the input signals and generates an output signal shorter than the time of the second logic level of the input signal at each time of the second transition,
Second pulse generating means that does not detect the second transition of the input signal even if the input signal is input while outputting the output signal; the logic level of the input signal and the second pulse generation A first logic gate for comparing a logic level of an output signal of the means to detect a signal other than the input signal;
Of the output signal of the first pulse generating means, the third pulse generating means generating an output signal having a time width equal to or less than the cycle of the input signal from the time when the logic gate detects a signal other than the input signal. A second logic gate is provided for detecting an abnormal period of the cycle of the input signal by comparing the level with the logic level of the output signal of the third pulse generating means.

[0005]

According to the present invention, since the pulse period abnormality detection circuit is constructed as described above, the first transition of the input signal is detected by the first pulse generating means, and the first transition of the input signal is detected. At each time point, the first pulse generating means generates an output signal having a time width which is equal to or longer than the cycle of the input signal and is equal to or smaller than twice the cycle of the input signal. Therefore, when the cycle of the input signal becomes longer than the time width of the output signal of the first pulse generating means, the first pulse generating means detects this as an abnormality of the cycle of the input signal. On the other hand, for the input signal, the second pulse generating means detects the second transition of the input signal,
Every second transition point, the second pulse generating means generates an output signal shorter than the time of the second logic level of the input signal, and the second pulse generating means outputs the output signal. Even if an input signal is input in the meantime, the second transition of the input signal is not detected. Next, the logic level of the input signal and the logic level of the output signal of the second pulse generating means are compared by the first logic gate to detect signals other than the input signal. Then, from the time when the first logic gate detects a signal other than the input signal, the third pulse generating means generates an output signal having a time width equal to or shorter than the cycle of the input signal. for that reason,
When the cycle of the input signal becomes shorter than the time width of the output signal of the second pulse generating means, the second and third pulse generating means and the first logic gate indicate that the cycle of the input signal is abnormal. To detect as. As a result of the above detection, when the cycle of the input signal is longer than the time width of the output signal of the first pulse generating means, or when the cycle of the input signal is longer than the time width of the output signal of the second pulse generating means. If it gets shorter,
A signal for detecting an abnormal period of the cycle of the input signal is output from the second logic gate. Therefore, the above problem can be solved.

[0006]

1 is a circuit diagram of a pulse cycle abnormality detection circuit showing an embodiment of the present invention. This pulse cycle abnormality detection circuit includes an input terminal IN for inputting a frame synchronization signal SYNC, and the input terminal IN is a trigger input terminal TG of the mono-multivibrator 11 which is the first pulse generating means, and a second input terminal IN.
Is connected to the trigger input terminal TG of the mono-multivibrator 12 which is the pulse generation means of the above, and the first input terminal of the two-input AND circuit 13 which is the first logic gate.
Further, the terminal t1 of the monomultivibrator 11 is connected to the terminal t2 via the capacitor C11, and the terminal t2
Is connected to the power supply potential Vcc via the resistor R11. The terminal t1 of the monomultivibrator 12 is connected to the terminal t2 via the capacitor C12, and the terminal t2 is connected to the power supply potential Vcc via the resistor R12.
The mono-multivibrator 11 is similar to the conventional mono-multivibrator 1 in FIG. 2, and the changing point (rising edge) of the frame synchronization signal SYNC input to the trigger input terminal TG.
Is a circuit that outputs "H" during a time T2 determined by the time constant of the capacitor C11 and the resistor R11, which is slightly longer than the cycle T1 of the frame synchronization signal SYNC, and the time T2 during which "H" is output. During the period, a new change point (rise)
Is input, during that time T2,
It is a retriggerable mono-multivibrator that outputs "H".

Here, the time T2 is a frame synchronization signal.
If it is shorter than the cycle T1 of SYNC, the frame synchronization signal SYNC
Even if is not turned off, the mono multivibrator 11
Is detected as "disconnection". On the other hand, time T2 is cycle T1
If it is longer than twice, the frame sync signal SYNC becomes "disconnected".
However, the mono-multivibrator 11 does not detect this "break". Therefore, the time T2 needs to be a time width that is equal to or greater than the cycle T1 of the frame synchronization signal SYNC and is equal to or less than twice the cycle T1. Mono multivibrator 1
2 is the frame sync signal from the change point (falling edge) of the frame sync signal SYNC input to the trigger input terminal TG.
Capacitor C12, which is slightly shorter than SYNC “L” period T3
During a time T4 determined by the time constant of the resistor R12 and
This circuit outputs "H". However, this mono-multivibrator 12 has a new change point (falling edge) at the trigger input terminal TG during the time T4 during which "H" is output.
It is a non-retriggerable mono multivibrator that does not detect the change point even if is input.

The positive phase output terminal Q of the monomultivibrator 12 is connected to the second input terminal of the AND circuit 13. The output terminal of the AND circuit 13 is connected to the trigger input terminal TG of the monomultivibrator 14 which is the third pulse generating means. Mono multivibrator 14
Is connected to a terminal t2 via a capacitor C14, and the terminal t2 is connected to a power supply potential Vc via a resistor R14.
connected to c. The mono multivibrator 14 is
It is a circuit that outputs "L" for a time T1 determined by the time constant of the capacitor C14 and the resistor R14, which is the same as the cycle T1 of the frame synchronization signal SYNC, from the change point (rise) of the signal input to the trigger input terminal TG. . However, when a new change point (rising edge) is input to the trigger input terminal TG during the time T1 during which "L" is output, this mono-multivibrator circuit starts the cycle of the frame synchronization signal from that point. It is a retriggerable mono-multivibrator that outputs "L" for the same time T1 as T1. However, the time when the mono multivibrator 14 outputs "L" does not have to be the same as the cycle T1 of the frame synchronization signal SYNC, and may be the cycle T1 or less. The inverting output terminal Q / of the mono multivibrator 14 is connected to the first input terminal of the 2-input AND circuit 15 which is the second logic gate, and the positive phase output terminal Q of the mono multivibrator 11 is A.
It is connected to the second input terminal of the ND circuit 15. AN
The output terminal of the D circuit 15 is connected to the output terminal OUT.

FIG. 4 is a time chart showing the operation at the time of normal operation of FIG. 1, in which the ordinate represents the logic level and the abscissa represents the time. The operation of FIG. 1 will be described with reference to this figure. The frame synchronization signal SYNC is input to the input terminal IN. Here, the frame synchronization signal SYNC is a signal in which the "L" section is longer than the "H" section of the signal. The output signal S11 of the multivibrator 11 becomes "H" during the time T2 from the change point of the rising edge of the frame synchronization signal SYNC. Since the time T2 is set to be larger than the cycle T1 of the frame synchronization signal SYNC, in the normal state, the rising change point of the frame synchronization signal SYNC comes in before the time T2 ends. Therefore, the multi-vibrator 1
The output signal S11 of 1 is always "H". The output signal S12 of the multivibrator 12 is a frame synchronization signal.
It becomes “H” for a time T4 from the change point of the falling edge of SYNC. Since the time T4 is set smaller than the time T3 of "L" of the frame synchronization signal SYNC, the output signal S13 of the AND circuit 13 is always "L". That is, since the change point is not input to the trigger input terminal TG of the multivibrator 14, the output signal S14 thereof is always "H".
Therefore, since the logical levels of the two input terminals of the AND circuit 15 are both "H", the logical level of the output terminal of the AND circuit 15 is "H" and the logical level of the output terminal OUT is "H". . FIG. 5 shows the frame synchronization signal of FIG.
6 is a time chart showing the operation when the SYNC cycle is short, in which the vertical axis represents the logic level and the horizontal axis represents time.

The operation of FIG. 1 will be described with reference to this figure. The output signal S11 of the multivibrator 11 is shown in FIG.
As in the normal operation of, the signal becomes “H” during the time T2 from the change point of the rising edge of the frame synchronization signal SYNC. Time T2
Is set to be larger than the cycle T1 of the frame sync signal SYNC, so that the frame sync signal before the time T2 ends.
There is a change point at the rising edge of SYNC or a change point such as noise. Therefore, the output signal S1 of the multivibrator 11 is
1 is always "H". The output signal S12 of the multivibrator 12 becomes "H" during the time T4 from the change point of the falling edge of the frame synchronization signal SYNC. The time T4 is set to be smaller than the time T3 of "L" of the frame synchronization signal. Here, when the change points n1 to n4 of noise or the like are input to the first input terminal of the AND circuit 13 while the output signal S12 is “H”, the change points n1 to n4 are input to the multivibrator 14. Is entered. Therefore, the output signal S14 of the multivibrator 14 has the respective change points n1 to n1.
It becomes "L" from n4 during the time T1. That is, in the output signal S14, the fourth noise n4 is input to the multivibrator 14 from the time when the first noise n1 on the output signal S13 in FIG. 5 is input to the trigger input terminal TG of the multivibrator 14. It becomes "L" only for the time T5 from the point of time when the time T1 elapses. Since “L” is input to the first input terminal of the AND circuit 15 from the multivibrator 14, the logical level of the output terminal of the AND circuit 15 becomes “L”. Therefore, the output terminal OUT
Outputs "L" during the time T1 during which the multivibrator 14 outputs "L".

FIG. 6 is a time chart showing the operation when the cycle of the frame synchronization signal SYNC of FIG. 1 is long, in which the vertical axis represents the logic level and the horizontal axis represents the time. The operation of FIG. 1 will be described with reference to this figure. Since the time T6 of “L” of the frame synchronization signal SYNC is longer than the time T2 of the output signal S11 of the multivibrator 11 being “H”, even if the time T2 ends, the trigger input terminal TG of the multivibrator 11 is The output signal S1 of the multi-vibrator 11 is output during the time T7 until the next change point is input without inputting the change point of the rising edge of the frame synchronization signal SYNC.
1 becomes "L". Further, in the multivibrator circuit 12, even if the time T4 of "H" of the output signal S12 ends,
Since the change point of the falling edge of the frame synchronization signal SYNC is not input to the trigger input terminal TG of the multivibrator 12, the output signal S12 is "L" during the time T8 until the next change point is input. Therefore, AND circuit 1
The logic level of the output terminal of No. 3 is "L", and the trigger input terminal TG of the multivibrator 14 is always "L".

As a result, "H" is input from the multivibrator 14 to the first input terminal of the AND circuit 15,
Further, since the output signal S11 of the multivibrator 11 is input to the second input terminal of the AND circuit 15, AND
The output signal S15 of the circuit 15 outputs "L" during the time T7 during which the multivibrator circuit 11 outputs "L". Therefore, "L" is output from the output terminal OUT during the time T7 during which the multivibrator 11 outputs "L". As described above, in the present embodiment, when the frame synchronization signal SYNC enters the pulse cycle abnormality detection circuit in a cycle shorter than the specified cycle T1 of the frame synchronization signal SYNC,
Alternatively, when the cycle of the rising change point of the frame synchronization signal SYNC becomes longer than the cycle T1, the pulse cycle abnormality detection circuit detects this and outputs "L" to the output terminal OUT.

The present invention is not limited to the above embodiment, but various modifications can be made. The following are examples of such modifications. (A) In the embodiment, it is assumed that the “H” time of the frame synchronization signal SYNC is shorter than the “L” time, but the present invention is also applied to the opposite case. However, the frame sync signal
When noise or the like is superimposed on SYNC, the probability of detecting it is lower than that in the present embodiment. (B) The pulse cycle abnormality detection circuit of the present invention is not limited to the pulse cycle abnormality detection circuit of FIG. For example, in the pulse cycle abnormality detection circuit of FIG. 1, the inverting output terminal Q / of the mono multivibrator 11 and the mono multivibrator 14 are used.
The positive-phase output terminal Q may be connected to a 2-input OR circuit.

[0014]

As described above in detail, according to the present invention, the period of the input signal is made longer than the time width of the output signal of the first pulse generating means by using the first pulse generating means. A case is detected, and the period of the input signal becomes shorter than the time width of the output signal of the second pulse generating means by using the second and third pulse generating means and the first logic gate. Since the time width of the output signal of the first pulse generating means and the time width of the output signal of the second pulse generating means are set to values corresponding to the specified cycle of the input signal, If the cycle of the input signal becomes shorter than the specified cycle for some reason, or if the cycle of the input signal becomes longer than the specified cycle, the pulse cycle abnormality detection circuit detects this and detects an abnormality. Can be output.

[Brief description of drawings]

FIG. 1 is a circuit diagram of a pulse cycle abnormality detection circuit showing an embodiment of the present invention.

FIG. 2 is a circuit diagram of a conventional pulse period abnormality detection circuit.

FIG. 3 is a time chart of FIG.

FIG. 4 is a time chart showing an operation during normal operation in FIG.

5 is a time chart when the cycle of the frame synchronization signal of FIG. 1 is short.

FIG. 6 is a time chart when the cycle of the frame synchronization signal of FIG. 1 is long.

[Explanation of symbols]

11 mono-multivibrator (first pulse generation means) 12 mono-multivibrator (second pulse generation means) 13 AND gate (first logic gate) 14 mono-multivibrator (third pulse generation means) 15 AND gate ( Second logic gate)

Claims (1)

[Claims] 1. A first transition, which is a transition from the second logic level to the first logic level, of an input signal having a constant period in which the second logic level time is longer than the first logic level time. First pulse generating means for detecting a transition and generating an output signal having a time width that is equal to or more than the period of the input signal and is equal to or less than twice the period of the input signal at each time of the first transition; A second transition, which is a transition of the signal from the first logic level to the second logic level, is detected, and at a time point of the second transition, a second transition time of the second logic level of the input signal is detected. Second pulse generating means for generating a short output signal and not detecting the second transition of the input signal even if the input signal is input while outputting the output signal; and a logical level of the input signal. Is compared with the logic level of the output signal of the second pulse generating means, and the input signal is compared. A first logic gate for detecting a signal other than the input signal, and a third pulse for generating an output signal having a time width equal to or less than the cycle of the input signal from the time when the first logic gate detects a signal other than the input signal A second means for comparing the logic level of the output signal of the first pulse generation means with the logic level of the output signal of the third pulse generation means to detect an abnormal period of the cycle of the input signal. A pulse cycle abnormality detection circuit comprising a logic gate.