JP3506546B2 - Data valid period signal generation circuit in serial data communication - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention processes a serial data signal to extract only a valid data signal from a serial data signal transmitted in frame units together with a clock signal. And a circuit for generating a data valid period signal indicating a period during which the data signal is valid. [0002] In recent years, the field of exchanges for handling serial data has been rapidly developing. In serial data communication in an exchange, a large number of contents are folded into one data line for communication. Therefore, it is necessary to reliably extract each content from one data line. FIG. 4 is a diagram showing a serial data signal targeted by the present invention. As shown in FIG. 4, in the serial data signal targeted by the present invention, a predetermined period is defined as one frame, and in each frame, transmission of valid data starts after a first period a has elapsed from the start of the frame. Then, transmission of valid data ends after a lapse of the second period b from the start of the frame. Therefore, the period during which valid data is transmitted is ab. At the beginning of the frame, a frame top signal indicating the start of the frame is provided. A serial data signal as shown in FIG. 4 includes a frame top signal and an invalid signal as described above, and the data content cannot be extracted as it is. Therefore, a data valid period signal indicating a valid data period is generated from the serial data signal as shown in FIG. 4, and valid data is extracted according to the data valid period signal. FIG. 5 is a diagram showing a conventional circuit configuration for generating a data valid period signal from a serial data signal and separating valid data from the serial data signal. In FIG. 5, reference numerals 11, 13, 5
1, 52 are D-type flip-flops (D-FF), 12 and 53 are AND gates, 50 is a data valid period signal generation circuit, 54 is a counter, 55 is a decoder group, and 56 is an OR gate. Clock signal CK is transmitted in parallel with the serial data signal. An input data signal is input to a data input terminal D of the D-FF 11, and a clock signal CK is input.
Becomes a synchronous data signal synchronized with the rising edge of. This signal is input to the AND gate 12 and also to the data valid period signal generation circuit 50. The data valid period signal generation circuit 50 generates a signal indicating a period during which data is valid according to the synchronous data signal and the clock signal. The AND gate 12 allows the synchronous data signal to pass only while the data is valid, and passes the DF
It is input to the data input terminal of F13. This gives D
The output of the FF 13 is a signal indicating only a valid data signal. In the data valid period signal generation circuit 50, D
-The FFs 51 and 52 and the AND gate 53 generate a pulse having one logical state (here, "high (H)") only during a period corresponding to the first frame top signal of the synchronous data signal. In the circuit shown in the figure, a pulse which is delayed by one clock signal with respect to the frame top signal of the synchronous data signal is generated. With this pulse, the counter 54 is loaded with a predetermined value. The value to be loaded is a value determined from the first period a in FIG. The counter 54 loaded with the value in this way starts counting. The counter 54 is decoded by a decoder group 55, and its output is combined by an OR gate 56, whereby the period a-
A data valid period signal that is in the “H” state during b is generated. Of the decoder group 55, the last one of the data valid period
The output that goes to the “H” state by the clock signal is returned to the D-FF 51 to reset the D-FF 51, and the output that goes to the “H” state by one clock signal after the end of the data valid period is returned to the counter 54 and the counter Clear the count value of 54. Thereby, the data valid period signal generation circuit 50
The data valid period signal can be generated again upon receiving the frame top signal. [0007] In the circuit of FIG. 5, the output of the decoder group 55 is input to the preset terminal of the D-FF 51. The decoder of the decoder group 55 generates a signal which becomes “H” for the last one clock signal of the data valid period by taking the logical product of the output signal of the counter 54, which is partially inverted. Are different in response when rising and falling when the counter value changes, so that a beard-like noise is likely to occur in the output of the decoder to which they are input. If such noise exists, the D-FF
51 is temporarily preset, the next input data signal is detected as a frame top signal, and control is performed as if a new frame was started.
There is a problem that a correct data valid period signal cannot be generated. In order to solve such a problem, as shown in FIG. 6, a signal which is in the "H" state for the last one clock signal of the data valid period outputted from the decoder is supplied to the circuit of FIG. In this case, a circuit further provided with a D-FF to be input to the DUT is used. However, such a circuit has a problem that the circuit becomes large because a D-FF having a large circuit scale is added. Although a JK flip-flop 59 has been used instead of a D-FF as shown in FIG. 7, the J input of the JK flip-flop 59 and the K
When both inputs become "H", the output is inverted, so that the same problem as in the circuit of FIG. 5 occurs. The present invention has been made in view of the above problems, and has as its object to realize a data valid period signal generation circuit that does not cause a malfunction with a simple configuration. A circuit for generating a data valid period signal in serial data communication according to the present invention includes a clock signal synchronized with a change in a data signal and a predetermined period period as one frame. A data signal is transmitted, in each frame, a frame top signal indicating the start of the frame at the beginning of the frame, and data valid for a period from the beginning of the frame to a first predetermined time and a second predetermined time later. Is a circuit that generates a data valid period signal in serial data communication to be transmitted, detects a frame top signal and changes to one logical state,
A frame top signal detection circuit that maintains a logic state until the end of the second predetermined time; and a second predetermined time after the frame top signal detection circuit changes to one of the logic states, the second
And a counter that counts a time corresponding to the difference between the first time and the first time by counting the clock signal, and decodes the output of the counter to obtain a predetermined time between the first predetermined time and the second predetermined time. A validity period signal generating circuit for generating a validity period signal that becomes a logical state of a circuit for generating a data validity period signal in serial data communication,
In order to achieve the above object, there is provided a data valid period end pulse generating circuit for decoding an output of a counter and generating a data valid period end pulse indicating only a period of one cycle of the last clock signal of the valid period signal, The top signal detection circuit has a data input terminal and a clock signal input terminal to which a clock signal is input, and outputs data corresponding to data input to the data input terminal when the clock signal is input. A gate circuit for synthesizing the D-type flip-flop, a frame top signal, a data valid period end pulse, and an output of the D-type flip-flop; an output of the gate circuit is input to a data input terminal of the D-type flip-flop It is characterized by having such a configuration. In the data valid period signal generating circuit of the present invention, the data valid period end pulse is not inputted to the preset terminal of the D-type flip-flop constituting the frame top signal detecting circuit, but the frame top signal and the D signal are inputted by the gate circuit. After being combined with the output of the type flip-flop itself, it is input to the data input terminal of the D-type flip-flop. Accordingly, if the signal input to the data input terminal is determined at the time when the clock signal is input to the D-type flip-flop, a malfunction does not occur. Therefore, the output of the counter changes after the clock signal changes. However, the output of the counter is fixed at the next time the clock signal changes, and the data valid period end pulse is also a stable signal. Will not occur. FIG. 1 is a diagram showing the configuration of a data separation circuit according to a first embodiment of the present invention, and FIG. 2 is a time chart showing the operation of the circuit of the first embodiment. . here,
It is shown that valid data starts from the fifth clock signal from the start of the frame and is output up to the 21st clock signal. As is apparent from a comparison between FIG. 1 and FIG.
The difference from the conventional example is that the synchronous data signal is input to the OR gate 21 which takes the logical sum with the output of the D-FF 23, and the output of the OR gate 21 is ANDed with the inverted signal of the data valid period end signal. After that, the data is input to the data input terminal of the D-FF 23. A decoder 3 for generating a data valid period end signal indicating only the period of one cycle of the last clock signal CK of the valid period signal in the decoder group 27
An AND gate 2 takes the logical product of the output signal of the counter 26 whose part is inverted. When a data signal as shown in FIG. 2 is input,
The output A of the D-FF 11 becomes a synchronous data signal delayed by one clock signal. The synchronization data signal is input to the OR gate 21. The frame of the synchronization data signal starts,
When the “H” frame top signal is input, D
Since the output of the FF 23 is “L” and the data valid period end signal output from the decoder 32 is “L”, D−
An “H” signal is input to the data input terminal of the FF 23. Then, at the next rising edge of the clock signal CK, D-
The output B of the FF 23 becomes “H”. Since the output B is returned to the OR gate 21, even if the synchronous data signal changes to "L", the output of the OR gate 21 remains "H" and is input to the data input terminal of the D-FF 23. The signal changes because the data valid period end signal is "H".
It is time to change. When output B changes to "H", D-
Since the output of the FF 24 is "L", the AND gate 25
Changes to “H” at the next clock signal CK.
Rises, the output of the D-FF 24 changes to “H”, and the output C becomes a pulse for one clock signal. The output C is input to the load terminal of the counter 26,
At 6, a predetermined value is loaded. Here, it is assumed that zero is loaded. Thus, the counter 26 starts counting the clock signal. The decoder group 27 is provided with 17 AND gates 31, 32, 33 and the like. These operate as decoders. To each AND gate, the output of the counter 26, which is partially inverted so that the output becomes “H” when the count value ranges from 2H (hexadecimal) to 12H, is input. As a result, each AND gate sequentially becomes the "H" state until the count value changes from 2H to 12H. Therefore, when the OR of the outputs of the 17 AND gates is obtained by the OR gate 28, the data valid period signal D is generated. The AND gate 32 of the decoder group 27 outputs a data valid period end signal which becomes "H" when the count value is 11H. Since this signal is inputted to the AND gate 22, the next rising edge of the clock signal is output. D-FF
The output B of 23 changes to "L". The AND gate 33 becomes "H" when the count value is 12H, but this is input to the counter 26 as an enable signal, so that the counter 26 stops counting when the count value becomes 12H. In this manner, a signal F and a data output obtained by removing the frame top signal from the input data as shown are obtained. The AND gate 32 generates a whisker-like noise due to a change in the output of the counter 26. However, since these noises are determined when the clock signal CK rises next time, the D-FF 23 does not malfunction. FIG. 3 is a diagram showing a configuration of a data separation circuit according to a second embodiment of the present invention. In the second embodiment, the data valid period signal is generated as in the first embodiment. The difference is that the parity check of valid data is performed for each frame. D-FF 13 and EXOR gate 17 in FIG.
Constitutes a parity check circuit for serial data, and inputs a data valid period signal generated by the circuit 12 to the AND gate 12 to set a valid data period. The D-FF 30 generates a signal indicating the timing of transmitting the result of the parity check. D-FF1
Reference numerals 5 and 16 denote delay circuits for correcting a phase shift between the circuit 12 and the parity check circuit. As described above, according to the present invention,
A data valid period signal generation circuit that operates reliably with a small number of gates can be realized, and accurate control of serial data can be performed.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a diagram showing a configuration of a data separation circuit according to a first embodiment of the present invention. FIG. 2 is a timing chart showing the operation of the circuit of the first embodiment. FIG. 3 is a diagram showing a configuration of a data separation circuit according to a second embodiment of the present invention. FIG. 4 is a diagram showing a serial data signal targeted by the present invention. FIG. 5 is a diagram showing a configuration of a conventional data separation circuit. FIG. 6 is a diagram showing another configuration of a conventional data separation circuit. FIG. 7 is a diagram showing another configuration of a conventional data separation circuit. [Description of References] 11, 13, 23, 24: D-type flip-flops 12, 22, 25: AND gates 21, 28: OR gate 26: Counter 27: Decoder groups 31, 32, 33: Decoder (AND gate)

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) H04L 7/04 H04L 25/40

Claims (1)

(57) [Claim 1] A data signal is transmitted in frame units with a predetermined cycle period as one frame, together with a clock signal synchronized with a change in the data signal. A frame top signal indicating the start of a frame, and a data valid period signal in serial data communication in which valid data is transmitted during a period from a beginning of the frame after a first predetermined time and after a second predetermined time. A frame top signal detection circuit (21, 22, 23) for detecting the frame top signal, changing to one logic state, and maintaining the logic state until the end of the second predetermined time; After the first predetermined time after the frame top signal detection circuit changes to the one logic state, the difference between the second time and the first time is calculated. An equivalent to time, to count by counting the clock signal counter (24,2
5, 26), and a valid period signal generating circuit (27, 27) for decoding the output of the counter and generating a valid period signal that becomes a predetermined logical state between the first predetermined time and the second predetermined time. 28)
A circuit for generating a data valid period signal in serial data communication, comprising: decoding an output of the counter; and outputting a data valid period end pulse indicating only a period of one cycle of the clock signal at the end of the valid period signal. The frame top signal detection circuit has a data input terminal (D) and a clock signal input terminal to which the clock signal is input; A D-type flip-flop (23) for outputting data corresponding to the data input to the data input terminal (D) at the time when is input, the frame top signal, the data valid period end pulse, And a gate circuit (21, 22) for synthesizing the output of the D-type flip-flop. A data valid period signal generation circuit in serial data communication, wherein the circuit is configured to be inputted to the data input terminal (D) of the D-type flip-flop.