JPH06140940A - Discrimination circuit for parity part of serial data form - Google Patents

Abstract

PURPOSE:To attain high sped processing while the circuit scale is made small with respect to the discrimination circuit for the parity part of serial data form. CONSTITUTION:A parity part comprising serial data 2 in a prescribed bit number is sequentially inputted to each of terminals J, K connected for T flip-flop operation and when a level of the part corresponding to the clock 3 of the input data is logical H, a JK flip-flop 1 inverting its output signal on each occasion is provided and the JK flip-flop is set to the initial state before fetching head data of the parity part to check the state of the parity part based on an output signal level of the JK flip-flop. Furthermore, the discrimination circuit is used for parity check and parity signal generation.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a determination circuit for a parity part of a serial data format, and in particular, each of a J terminal and a K terminal connected to perform a T flip-flop operation is composed of serial data of a predetermined number of bits. The present invention relates to a determination circuit for a parity unit having a JK flip-flop whose output signal is inverted each time the parity unit is sequentially input and the level of the portion of the input data corresponding to the clock is "H".

Generally, in order to cope with the occurrence of a bit error during data transfer, it is widely practiced to set a parity part made up of a predetermined number of bits of serial data in a part of a data string before transferring. The receiving side parity section determination circuit performs a parity check by detecting the level of each data in the parity section and obtaining the number of bits of "H", for example.

At this time, in order to minimize the delay time in the parity determination circuit and to enable high-speed determination processing, it is strongly recommended that the circuit size not be increased as the serial data string of the parity portion becomes longer. The present invention meets these needs and needs. This is similarly required not only in the receiving side parity section determining circuit that performs the parity check, but also in the parity section determining circuit that adds the parity bit.

[0004]

2. Description of the Related Art FIG. 4 is an explanatory diagram showing an outline of a conventional parity part determination circuit. Reference numeral 41 is a serial-parallel conversion circuit composed of shift registers and the like, and 42 and 43 are parity detection circuits composed of adders and the like. Shows each container.

Here, a plurality of serial-parallel conversion circuits 41 are provided according to the length of the serial data string of the parity part. For example, the length of this serial data string is
In the case where one serial-parallel conversion circuit 41 as 32 bits shares conversion for 4 bits, eight serial-parallel conversion circuits are prepared.

Further, each of the parity detectors is in a cascade connection state, and the parity detector 42 in the first stage portion thereof is
Each of the corresponding serial-parallel conversion circuit 41
The output signal of is added. Then, the data of the least significant bit when this output signal is added is input to the parity detector at the next stage in the form of a temporary parity signal.

Next, by using a predetermined number of, for example, four parity detectors 42 as a unit, each of the provisional parity signals is input to the parity detector of the next stage for each unit, and the parity detector of the first stage portion is there. The same signal processing as in 42 is performed to generate a new temporary parity signal, and this temporary parity signal is input to the parity detector at the next stage.

The parity signal is obtained by the parity detector 43 at the final stage by repeating the signal processing in the parity detector as described above the number of times corresponding to the length of the serial data string in the parity section. A similar method is used in the above-mentioned parity part determination circuit on the side of adding a parity bit.

[0009]

As described above, the conventional
In the serial data format parity determination circuit, the serial data is first converted to parallel data by the serial-parallel conversion circuit, and then each of the parallel data is sequentially added. Therefore, the serial data string of the parity is long. There is a problem that the delay time in the determination circuit becomes longer as it becomes larger.

Therefore, in the present invention, serial data in the parity section is sequentially input to the JK flip-flops operating in the form of T flip-flops without being converted into parallel data, and at the time when this input is finished. JK
It is an object of the present invention to provide a decision circuit which is small in circuit scale and has a short delay time and is capable of high-speed processing by performing parity check and parity creation based on the output signal level of a flip-flop.

[0011]

According to the present invention, serial data of a parity portion is input as it is (without being converted into parallel data) to a JK flip-flop in a T flip-flop operation mode, and when the input of this serial data ends. The output signal level is checked to determine whether this value is "H" or "L", and the parity check or the parity creation is performed based on the result of this determination.

FIG. 1 illustrates the principle of the present invention. In the figure, 1 is a JK flip-flop, 2 is serial data of a parity part, 3 is a clock, and 4 is a parity part determination signal. In addition, JK flip-flop 1
Is connected to its J terminal and K terminal to form an operation mode of a T flip-flop.

Here, serial data 2 of the parity part is added to each of the J terminal and the K terminal of the JK flip-flop 1, and when the serial data 2 at the input timing of the clock 3 is "H". , Each time, J
The output signal level of the K flip-flop 1 is inverted between "H" and "L". As the input timing of the clock 3, its rising edge, falling edge, "H" level, etc. are used.

[0014]

As described above, according to the present invention, the output signal level of the JK flip-flop in the T flip-flop operation mode is "H" or "L" in the serial data of the parity section applied to the J terminal and the K terminal, respectively. It utilizes the fact that it corresponds to the number of bits of ".

That is, if the input signal level of the J terminal and the K terminal when the clock is applied is "H", the output signal level of the JK flip-flop is inverted every time, so that the parity part ( In the case of 10-bit serial data), the output of the JK flip-flop, which is initially set to “L”, is inverted at each of the 4th, 6th, 7th, and 10th clock parts, and finally “L”.
become.

Therefore, when the data group including the parity part is sent under the even parity system,
The receiving side parity check circuit for parity check is
It will be determined that there is no bit error during transmission.

In addition, for example, the parity part determination circuit on the side that generates the 10th data of the parity part as a parity bit is the 1st to 9th data input to the flip-flop from the output signal level of the JK flip-flop. The number of "H" bits in the data part of
When it is "4" as shown in the above, the 10th parity bit is set to "L" under the even parity system, and this parity bit is set to "H" under the odd parity system.
Set to.

[0018]

Embodiments of the present invention will be described with reference to FIGS. FIG. 2 is an explanatory diagram showing an example of a parity unit determination circuit,
FIG. 3 is an explanatory diagram showing a time chart of the parity part determination circuit, in which 21 is a D flip-flop and 22 is JK.
Flip-flop, 23 is a counter, 24 is a decoder, 25 is a comparison circuit, and 26 is a flag detector.

Here, the data group in the serial data format including the parity part is added to the D flip-flop 21, and its output signal is the J terminal of the JK flip-flop 22 and K.
Since the data is input to each of the terminals, the parity check is performed based on the signal level appearing at the output terminal of the JK flip-flop when the data input to the parity section is completed.

The data group is transmitted in, for example, a frame unit, and a flag sequence consisting of 8 bits of "01111110" is set at the head portion thereof. When the flag detection unit 26 detects this flag sequence, the counter 23 clocks. The counting operation of is started.

The number of bits (clock number) from the flag sequence to the parity part is set in advance in the comparison circuit 25, and the output signal of the comparison circuit 25 when the count value of the counter 23 reaches this clock number. Then, the reset state of the D flip-flop 21 is released, and then
At the output side of the D flip-flop 21, the parity part data synchronized with the clock is sequentially taken out and input to the J terminal and the K terminal of the JK flip-flop 22, respectively.

The output signal level of the JK flip-flop 22 is inverted every time the input bit is "H" when the clock is applied to the JK flip-flop 22 (for example, at the rising edge).

Therefore, the JK flip-flop 22 when the number of bits of the parity part "10" is counted by the counter 23
By detecting the output signal level of, the number of "H" level bits in the parity part is determined whether it is an even number or an odd number.

That is, when the output signal level is "H", the number of "H" level bits in the parity section is odd, and when the output signal level is "L", the "H" level bit in the parity section is "H". Each of the H "level bits is determined to be an even number, and a parity check is performed based on the determination result.

The number of bits of the parity section "10" is set in advance in the comparison circuit 25, and when the counter 23 counts this value, the comparison circuit 25 outputs a determination signal for the parity section. .

Prior to this parity check, the JK flip-flop 22 is reset by, for example, the output signal of the flag detector 26, and its output side is initialized to "L" level.

The data input to the J terminal and the K terminal of the JK flip-flop 22 is 1 with respect to the data input to the D terminal of the D flip-flop 21.
It will be offset by the clock.

[0028]

According to the present invention, serial data in the parity section is not directly converted into parallel data in this way, but is directly input to each of the J terminal and the K terminal of the JK flip-flop in the T flip-flop operation mode, and the parity is input. When the data input for the department is over, the relevant J
Parity check and parity creation are executed based on the output signal level of the K flip-flop.

Therefore, the circuit scale is smaller than that of a conventional serial-parallel conversion circuit or a parity determination circuit using an adder, and high-speed processing with a small delay time can be realized.

[Brief description of drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is an explanatory diagram showing an example of a parity part determination circuit of the present invention.

FIG. 3 is an explanatory diagram showing a time chart of the circuit of FIG. 2 of the present invention.

FIG. 4 is an explanatory diagram showing an outline of a conventional parity part determination circuit.

[Explanation of symbols]

 In FIG. 1, 1 ... JK flip-flop 2 ... Serial data of parity part 3 ... Clock 4 ... Parity part determination signal

Claims (2)

[Claims] 1. A parity part made up of a predetermined number of bits of serial data is sequentially input to each of a J terminal and a K terminal which are connected so as to perform a T flip-flop operation. When the level is "H", it has a JK flip-flop whose output signal is inverted each time. The JK flip-flop is set to the initial state before fetching the head data of the parity part, and the JK flip-flop concerned. A circuit for determining a parity part in a serial data format, wherein the state of the parity part can be checked based on the output signal level of the parity part. 2. A D flip-flop, which receives each data of the parity section and operates at the clock, is connected to the preceding stage of the J terminal and the K terminal, and the D flip-flop outputs only the data of the parity section. 2. The serial data format parity section determination circuit according to claim 1, wherein the reset state up to that point is released at the timing at which the data can be captured.