JPS58182352A - Digital data reception circuit - Google Patents

Abstract

PURPOSE:To decrease the generation of enoneous decision of data due to the distortion given on the reception data from external noises, by generating a sampling pulse of plural number of times in one bit of the reception data, integrating the result of sampling, and deciding the content of each bit of the reception data with the integration value, in a reception circuit of an interface device. CONSTITUTION:An AND circuit 3 ANDs data sections a1-a8 of a reception signal 8 and a pulse signal (d) and gives the result to a counter 7 as a signal (e). In taking logical product between the reception data of the 1st bit a1 and the signal (d), the 10th- the 12nd pulses of the signal (d) are gated with the AND circuit 3 at the fall-in of the level of a distortion n1 and are not obtained as the signal (e). Thus, the counter 7 counts the number of pulses of the signal (d) while the signal a1 is in a high level, and counts up to 13 in this sampling. A decoder 8 decodes a 4-bit binary code from the counter 7 and when the value reaches >=8, an output (f) is made active. Thus, the bit a1 is discriminated to be ''1'' for the content at the decoder 8 when the number of pulses reaches eight.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a receiving circuit for an interface device that transfers data between devices that operate using digital signals.

Conventionally, this type of receiving circuit samples data by generating a sampling pulse synchronized with the data transfer rate at the center of one bit time T of received data, as shown in FIG. 1, for example.

Therefore, in this method, if distortion n occurs in the waveform of received data due to external noise etc. when sampling pulses are generated,
There was a drawback that incorrect judgments were made. for example,
Figure 2 (a) shows an example in which a signal that should be received as a high level signal rxJ is incorrectly determined to be a low level signal "0" and is received. This is an example of receiving a message.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a digital data receiving circuit that reduces erroneous judgments caused by distortion of received data due to the influence of external noise, etc., and improves the reliability of received data.

According to the present invention, there is provided means for generating clock pulses faster than the data transfer rate of the received signal, and the number of clock pulses is counted only during the period when the received signal has one of the binary values. A digital data receiving circuit is obtained which includes means for determining the count value and means for outputting a determination signal when the counted value exceeds a predetermined value.

Next, the present invention will be described in detail with reference to FIGS. 3 and 4 showing one embodiment of the present invention. This embodiment shows an example in which the present invention is reversely applied to an asynchronous receiving circuit, and one data consists of 8 bits.

In FIG. 3, the clock pulse generation circuit 1 generates a clock pulse b at a speed 16 times the data transfer speed,
Supplied to AND circuit 2. Reception signal a is input from terminal RD and given to AND circuit 3 and start bit detection circuit 4. The start bit detection circuit 4 is a well-known circuit that detects the start bit added to ml of each data. When the start bit is detected, it supplies an enable signal to the 7-lip flop 5 to set it. The positive output Q (signal C) of the flip-flop 5 is applied to the AND circuit 2 to open its gate, and the negative output Q is applied to the start bit detection circuit 4 to stop this detection operation. AND circuit 2 with the gate opened is
The clock pulse b from the pulse generator 1 is applied to the frequency divider 6 (this is referred to as the pulse d), and the AND circuit 3 performs the logical product of the received signal a and the signal d from the AND circuit 2. A counter 7Fi is a circuit that counts the number of pulses of the signal e obtained from the AND circuit 3, and provides the counted value to the decoder 8. 8 decoders, 7 counters! When the numerical value exceeds a pre-added value, a judgment signal f is set in the shift register 9.

6-digit frequency divider, 1/16th division ratio, AND circuit 2
A pulse g is generated every time 16 pulses d are inputted from the cursor 7, and is applied to the cariter 7 as a reset signal and to the shift register 9 as a shift signal. This pulse y is also applied to a frequency divider 10 with a division ratio of 1/8, and when the frequency divider 10 counts eight pulses of the signal 9, it sends a reset signal to the seven lip-flop 5.

Next, the operation of this circuit will be explained by taking as an example the case where the received signal a input from the terminal RD is shown in FIG. This received data a has distortions n, to n, caused by external noise and the like.

When the reception signal a enters the terminal RD, the start bit detection circuit 4 first detects the start bit S, and the detection circuit 4 sends an enable signal to the flip-flop 5 to set it. This results in 7 lipflops of 5
outputs a signal "1" from the terminal Q and a signal "0" from the terminal Q, opens the gate 2, and stops the detection operation of the detection circuit Q. The gated AND circuit 2 supplies a tarok pulse 16 times faster than the data transfer rate from the clock pulse generator 1 as a signal d to the AND circuit 3 and the frequency divider 6, and outputs the received data following the start bit. Start collecting.

The AND circuit 3 takes the logical product of the data portions a, .about.a of the received signal a and the pulse signal d, and provides the result to the counter 7 as a signal e. When we take the logical product of the 1st bit of received data al and the signal d, the 10th to 12th pulses of the signal d are gated by the AND circuit 3 due to the drop in level due to the distortion n, and are obtained as pulses of the signal e. do not have. Therefore, the counter 7 receives the signal d only during the period when the signal al is at high level.
The number of pulses will be counted up to 13 during this sampling.

In this embodiment, the setting value of the decoder 8 is set to 8. That is, the decoder 8 decodes the 4-bit binary code from the counter 7, and when the value becomes 8 or more, makes the output f active. Therefore, the content of bit aI is determined to be 11'' by decoder 8 when the number of pulses of signal e reaches 8.

The output of the decoder 8 is stored in the shift register 9 at the timing of No. 48 g from the frequency divider 6, which outputs an output every time 16 clock pulses d from the AND circuit 2 are counted. Therefore, the judgment result i of the received data is set in the shift register 9 with a delay of approximately one bit. The output g of the frequency divider 6 is also applied to a counter 7 to return its contents to 0, and is also applied to a divider 10 that counts the number of bits of received data, and adds 1 to the counted value.

When data bit a2 is subsequently input to terminal RD, this circuit performs the same operation as before. AND circuit 3 is
Four pulses are sent to the counter due to the distortions n and - on the data bits al, but since the set value "8" of the decoder 8 is not reached, the output f of the decoder remains at a low level. Register 9 sets this at the timing when the sending of 16 pulses of signal d ends, so data a
2 is determined to be "0" without being affected by distortion and n3. At the same time, the frequency dividing circuit 6 resets the counter 7 as described above and adds 1 to the contents of the frequency dividing circuit 10.
-ru.

By continuing to retrieve data 31 to ag as described above and setting data bit a8 in the discrimination result table/register 9, the discrimination result of l received data will be set in register 9. Since the number of pulses from the frequency divider circuit 6 at this time is eight, the frequency divider circuit 10 sends a reset signal to the flip-flop 5. This will result in 7 rip 7
The output Q of the 0-tube 5 is at a low level, which closes the gate 2 and stops sending the output pulse d to the frequency divider circuit 6 of the AND circuit 2. Further, the high level signal of the output Q is applied to the start bit detection circuit 4, and instructs the detection circuit 4 to restart its operation. Shift register 9 obtained in this way
The contents include distortions n1 to n on received data a, ~-,
No adverse effects appear, and it becomes possible to accurately reproduce the received data a, to ag and supply it to the next stage processing device, etc.

In this embodiment, the clock pulse generator 1 generates a clock pulse at a speed 16 times the data transfer rate, and the decoder 8 is set to 1-8'', but this is done under a favorable environment with little external noise. It is obvious that if the system is to be used in the external environment, changes such as reducing the speed of the clock pulse by half or changing the setting value 't rlOJ can be made to make the system suitable for the external environment. Further, although an example in which one data is 8 bits has been described, when handling data composed of a different number of bits, this can be easily handled by changing the frequency division ratio of the frequency divider 100. That is, the number of bits of one data, the speed of the clock pulse, the setting value of the decoder, and the frequency division ratio of the frequency divider used for explaining the present embodiment do not limit the present invention.

As explained above, the present invention generates a sampling pulse multiple times in one bit of received data, integrates the sampling results, and determines the content of each bit of the received data based on the integrated value. etc., to reduce the occurrence of data isthmus judgment due to distortion on received data,
This has the effect of improving the reliability of received data after determination.

[Brief explanation of drawings]

1 and 2 are time charts showing a sampling method using a conventional data receiving circuit, FIG. 3 is a block diagram showing an embodiment of the present invention, and FIG. 4 shows the states of output signals from each part. It is a diagram. 1... Clock pulse generation circuit, 2, 3...
...AND circuit, 4...Start bit detection circuit, 5...Flip-flop, 6,10...
...Frequency divider circuit, 7...Counter, 8...
...Decoder, 9...Shift register Fig. 1 Lower data (cL) (-+!,) Fig. 2

Claims (1)

[Claims] means for generating clock pulses faster than the data transfer rate of a received signal that takes a binary symbol; means for counting the number of clock pulses during which the received signal is one symbol of the binary symbol; and the counted value. 1. A digital data receiving circuit comprising means for detecting that the value exceeds a predetermined value.