JPH08102679A - Crc error detecting circuit - Google Patents

Abstract

PURPOSE: To detect a cyclic redundancy check(CRC) error at the time of '0' continuous data by resetting data by the inversion signal of a frame pulse. CONSTITUTION: A CRC circuit 1 executes CRC for CRC receiving data and obtains its checked result D1. Then the CRC receiving data are inverted by an INV gate 2, the inverted data are inputted to the set terminal S of an R/S flip flop(FF) 4, a frame pulse is inverted by an INV gate 3, and its inverted pulse is inputted to the reset terminal of the FF 4. The output from the FF 4 is recounted by a D type FF 5 at the period of the frame pulse and the Q output from the FF 5 is acquired as a checked result D2. The normality of CRC error detection at the time of '0' continuous data can be recognized from the checked results D1, D2.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a CRC error detection circuit especially for 0 continuous data.

[0002]

2. Description of the Related Art As is well known, CRC (Cyclic Redunda)
cy Check) uses transmission information as a polynomial, divides it by an nth-order polynomial called a generator polynomial without carrying or borrowing, and transmits the remainder together with the original transmission information, which is the same on the receiving side. This is a method of detecting the presence or absence of a transmission error by dividing by the generator polynomial and determining whether it is divisible. The CRC calculation rule is as follows.

First, the input polynomial G (X) is multiplied by X ⁿ . Next, X ⁿ G (X) is divided by the generator polynomial P (X) without carrying or borrowing. Ignore the quotient and the remainder is C
(X). Then, X ⁿ G (X) + C (X) is transmitted. Here, when the quotient ^{Q (X), X n G} (X) = P (X) Q (X) + C (X) X n G (X) + C (X) = X n G (X) -C (X) = P (X) Q (X) However, in the calculation of modulo 2, since addition = subtraction, X ⁿ G (X) + C (X) is divided by P (X) on the receiving side, and the remainder If is 0, there is no CRC error.

However, the conventional CRC as described above is used.
The error detection circuit has the following problems. That is, in the CRC error detection described above, considering the case where the reception signal is disconnected, the reception signal = X ⁿ G (X) +
Since it is when C (X) = 0, CRC calculation of this results in 0 / P (X) = 0, which means that the data is regarded as normal even though there is no input signal.

Here, as the prior art, for example, Japanese Patent Laid-Open No.
In Japanese Patent Publication No. 95426, at the same time that CRC error detection is performed, it is detected that 0 or 1 of input data is continuously input, and when the same data is input for a long time, a CRC detection output is given. "CRC error detection circuit" to mask
Is disclosed.

[0006]

As described above, in the conventional CRC error detection circuit, the data is regarded as normal even though there is no input signal.

The present invention has been made to solve the above problems, and provides a CRC error detection circuit capable of detecting a CRC error at the time of 0 continuous data and recognizing the normality of error detection. The purpose is to do.

Here, the above-mentioned prior art shows a CRC error detection circuit that masks the CRC detection output when the same data is input for a long period of time, and the data subject to the CRC check continues for a certain amount or more. Therefore, there is no specific description that suggests the technical idea of the present invention in which the error detection is performed more strictly and the error detection is performed more strictly, and the technical idea is completely different from the present invention.

[0009]

In order to achieve the above object, a CRC error detection circuit according to the present invention includes a CRC check circuit for performing a CRC check of CRC reception data and outputting a first determination result, and the CRC reception circuit. An R / S flip-flop that is set based on the data and reset based on the frame pulse, and a D that holds the output of the R / S flip-flop at the timing of the frame pulse and outputs it as the second determination result. Type flip-flop.

[0010]

In the CRC error detection circuit having the above structure, C
A CRC check circuit performs a CRC check on the RC received data to obtain a first determination result, sets an R / S flip-flop based on the CRC received data, resets it based on a frame pulse, and outputs its Q output to D. Type flip-flops, re-typed at the cycle of frame pulse,
The Q output is acquired as the second determination result, and the normality of the CRC error detection at the time of continuous 0 can be recognized from the first and second determination results.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows a configuration of an embodiment of a CRC error detection circuit according to the present invention, in which C supplied to a terminal T1 is
The RC reception data is supplied to the CRC check circuit 1 and also to the set terminal S of the R / S flip-flop 4 via the INV gate 2. Further, the frame pulse supplied to the terminal T2 is R / S via the INV gate 3.
The clock signal is supplied to the reset terminal R of the flip-flop 4 and the clock input terminal CLK of the D-type flip-flop 5.
Is supplied to.

The Q terminal output of the R / S flip-flop 4 is supplied to the data input terminal D of the D-type flip-flop 5. The output of the CRC check circuit 1 is output from the terminal T3 as the determination result D1. The output of the Q terminal of the D-type flip-flop 5 is the terminal T4 as the determination result D2.
Output from

In the above structure, the operation will be described below with reference to the phase relationship of input / output data shown in FIG.

First, the CRC check circuit 1 performs a CRC check on the received data, and the determination result D1 is taken out from T3. Further, the reception data is passed through the INV gate 2 and the inverted result is set terminal S of the R / S flip-flop 4.
To enter. As a result, the R / S flip-flop 4 is set when at least one "1" is present in the received data. Further, if there is no "1", the set is not applied.

On the other hand, the frame pulse is passed through the INV gate 3 and the inverted result is input to the reset terminal R of the R / S flip-flop 4. As a result, the R / S flip-flop 4 is reset every frame pulse cycle.

Therefore, the processing result of the R / S flip-flop 4 is corrected by the D-type flip-flop 5 at the cycle of the frame pulse. As a result, the result of whether or not "1" is present in the received data is extracted as the determination result D2.

The result of the above processing is as follows. First, in the case of normal data including at least one "1", the determination result D1 is normal and the determination result D2 is H level. Further, in the case of normal data that does not include “1” at all, the determination result D1 is normal and the determination result D2 is L level. In the case of abnormal data, the determination result D1 is abnormal and the determination result D2 is indefinite.

Therefore, although the conventional CRC error circuit cannot detect the CRC error at the time of 0 continuous data, the CRC error detection circuit having the above-mentioned configuration detects the error by detecting all "0" s. The normality of can be recognized.

It is needless to say that the present invention is not limited to the above-mentioned embodiments, and can be similarly implemented even if various modifications are made without departing from the gist of the present invention.

[0021]

As described above, according to the present invention, it is possible to provide a CRC error detection circuit capable of detecting a CRC error at the time of 0 continuous data and recognizing the normality of error detection. it can.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an error detection circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of the embodiment.

[Explanation of symbols]

 1 CRC check circuit 2 INV gate 3 INV gate 4 S / R flip-flop 5 D-type flip-flop

Claims (2)

[Claims] 1. A CRC check circuit for performing a CRC check of CRC reception data and outputting a first judgment result; and an R / S flip-flop set based on the CRC reception data and reset based on the frame pulse thereof. And a D-type flip-flop that holds the output of the R / S flip-flop at the timing of the frame pulse and outputs the result as a second determination result. 2. The R / S flip-flop comprises the C
The CRC error detection circuit according to claim 1, wherein the CRC error detection circuit is set by an inversion signal of RC reception data and reset by an inversion signal of the frame pulse.