JPH05167647A - Speed converter having fault detection function - Google Patents

Abstract

PURPOSE:To detect an occurrence of a fault in the speed converter converting a speed of an input data signal. CONSTITUTION:The converter is provided with a speed conversion circuit 101 converting a speed of plural strings of input data signals 1 and with an input vertical parity arithmetic operation circuit 102 outputting an input vertical parity signal 5 of the input data signal, and also an output vertical parity arithmetic operation circuit 105 outputting an output vertical parity signal 7 of an output data signal 2 subjected to speed conversion outputted from the speed conversion circuit 101 and with a fault detection circuit 103 comparing an output signal 6 resulting from converting the speed of the input vertical parity signal 5 with the output vertical parity signal 7 to detect a fault.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a slave synchronization system in digital radio communication, and more particularly to a speed converter having a fault detecting function.

[0002]

2. Description of the Related Art In digital wireless communication, signals are compressed,
Alternatively, the transmission rate of the signal is converted such as enlargement. For this purpose, a shift register, a memory, or the like is used as the speed conversion circuit, and speed conversion can be performed by making the synchronization timing of the signal input to this different from the synchronization timing of the signal to be output.

[0003]

In this type of speed conversion device, when there is a deviation in the synchronization timing of input or output, or when there is a failure in the speed conversion circuit, the input signal and the output signal are output. And no longer correspond and so-called speed conversion failure occurs. Conventionally, since a function of detecting this kind of speed conversion failure is not provided, there is a problem that the speed conversion failure cannot be confirmed. An object of the present invention is to provide a speed conversion device having a failure detection function capable of confirming a speed conversion failure.

[0004]

A speed conversion device of the present invention comprises a speed conversion circuit for speed-converting input data signals of a plurality of columns, an input vertical parity arithmetic circuit for outputting an input vertical parity signal of the input data signals, Compare the output vertical parity operation circuit that outputs the output vertical parity signal of the speed-converted output data signal output from the speed conversion circuit with the output vertical parity signal whose speed is converted from the input vertical parity signal. And a failure detection circuit for detecting a failure. Here, the speed conversion circuit performs speed conversion of the input vertical parity signal in synchronization with the output data signal and outputs the output signal. Further, the timing conversion circuit is provided with a timing signal generation circuit for generating a timing signal required for speed conversion in the speed conversion circuit and at the same time inserting predetermined data at a bit insertion position of a frequency difference between the input data signal sequence and the output data signal sequence. ..

By comparing the input vertical parity signal of the input data signal and the output vertical parity signal of the output data signal, the correspondence relationship between the speed-converted input data signal and the output data signal can be compared, and a failure is detected. It becomes possible to do.

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block circuit diagram of an embodiment of the present invention.
In the figure, 101 is a speed conversion circuit composed of an M-bit memory, which reads N columns of input data signal trains 1 in synchronization with a clock signal 3 and outputs N columns of output data signal trains 2 in synchronization with a clock signal 4. Can be read out.
The clock signal 3 is obtained by dividing the clock signal 10 by the M frequency divider 10
It is obtained by dividing M by 6. Further, the clock signal 4 is obtained by dividing the frequency of the clock signal 11 that is phase-synchronized with the clock signal 10 at a constant cycle and has a different speed by the M frequency divider 107.

The input vertical parity calculation circuit 102 performs a vertical parity calculation for each bit of the input data signal sequence 1 and outputs an input vertical parity signal 5. Further, the output vertical parity calculation circuit 105 performs vertical parity calculation for each bit of the output data signal sequence 2 and outputs the output vertical parity signal 7. The input vertical parity signal 5 is read by the speed conversion circuit 101 in synchronization with the clock signal 3 and read out as the output signal 6 in synchronization with the clock signal 4.

The timing signal generating circuit 104 inputs the clock signals 3 and 4 respectively, and outputs both clock signals 3 and 4.
"0" is inserted by the timing signal 9 at the additional bit insertion position corresponding to the frequency difference of. Also, the fault detection circuit 1
Reference numeral 03 is configured to compare the output signal 6 of the input vertical parity signal 5 with the output vertical parity signal 7 and output a failure detection signal 8 if the two signals do not match.

Next, the operation of the speed conversion device having the above configuration will be described with reference to the timing chart of FIG. The input data signal sequence 1 of N columns is temporarily stored in the speed conversion circuit 101 at the synchronization timing of the clock signal 3. Then, the speed conversion circuit 1 is synchronized with the clock signals 4 having different speeds.
The output data signal sequence 2 from 01 to N is read and speed conversion is performed. At this time, "0" is inserted by the timing signal 9 at the additional bit insertion position corresponding to the frequency difference between both clocks (signals). On the other hand, the input parity arithmetic circuit 102 performs vertical parity arithmetic on N columns of data for each bit (every one clock cycle) of the input data signal sequence 1 and outputs an input vertical parity signal 5. The input vertical parity signal 5 is read by the speed conversion circuit 101 by the clock signal 3, read by the clock signal 4 and converted in speed in the same manner as described above, and output as the output signal 6.

Further, the output vertical parity arithmetic circuit 105 is
The speed-converted output data signal sequence 2 is subjected to vertical parity calculation for each bit of N column data (every one clock cycle), and an output vertical parity signal 7 is output. Fault detection circuit 10
In 3, the output signal 6 which is the result of the parity calculation on the input side and the output vertical parity signal 7 are compared to determine whether or not the respective bits match. At this time, with respect to the additional bit insertion position, the comparison of both signals is prohibited by the timing signal 9, and the determination is not performed.

If no faults have occurred, the corresponding bits of both signals match. If the corresponding bits do not match, it means that any of all the devices including the speed conversion circuit 101 has a failure. If a failure has occurred, the failure detection circuit 103 can output a failure detection signal 8 to confirm the failure. The bit content of the additional bit insertion position may not be limited, and the data one bit before the additional bit insertion position may be used as the additional bit. In this case, in the fault detection circuit 103,
The same effect can be obtained by adopting a method in which the comparison is not prohibited by the timing signal 9.

[0012]

As described above, the present invention compares the input vertical parity signal of the input data signal with the output vertical parity signal of the speed-converted output data signal to ensure that the input data signal is correctly speed-converted. It is possible to confirm whether or not the failure has occurred, and it is possible to detect the occurrence of a failure in the speed conversion device. Further, by inserting the additional bit by the timing generating circuit and detecting it, it is possible to confirm whether or not the timing signal is correctly generated.

[Brief description of drawings]

FIG. 1 is a block circuit diagram of an embodiment of a speed conversion device of the present invention.

FIG. 2 is a timing diagram for explaining the operation of the present invention.

[Explanation of symbols]

 101 speed conversion circuit 102 input vertical parity arithmetic circuit 103 failure detection circuit 104 timing signal generation circuit 105 output vertical parity arithmetic circuit 106, 107 frequency divider

Claims (3)

[Claims] 1. A speed conversion circuit for speed-converting a plurality of columns of input data signals, an input vertical parity operation circuit for outputting an input vertical parity signal of the input data signals, and a speed-converted speed output from the speed conversion circuit. An output vertical parity arithmetic circuit for outputting an output vertical parity signal of an output data signal, and a failure detection circuit for detecting a failure by comparing the output vertical parity signal with an output signal obtained by speed conversion of the input vertical parity signal. A speed conversion device having a failure detection function, comprising: 2. The speed conversion device having a failure detection function according to claim 1, wherein the speed conversion circuit performs speed conversion of the input vertical parity signal in synchronization with the output data signal and outputs the output signal. 3. A timing signal generator for generating a timing signal required for speed conversion in a speed conversion circuit, and at the same time inserting predetermined data at a bit insertion position of a frequency difference between an input data signal sequence and an output data signal sequence. A speed conversion device having a failure detection function according to claim 1 or 2, further comprising a circuit.