JP2000188591A - Received data error detection circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a circuit that a circuit scale does not increase even if data length becomes long and can cope with data of a variable length by comparing the data value of received data with the output value of a flip flop when the end of received data is detected by means of an end detection means and detecting the error of received data. SOLUTION: A signal 'start' showing the head of an input data string, the input data string 'data' and a 'clock' are supplied to a toggle flip flop(TFF) 3 and the output of TFF 3 becomes a parity. When the output 'start' signal is given when the head bit string of a head detection means is detected, namely, when TFF 3 is set or reset and is initialized at the head timing of input data and when the input data string is '1' in the second and subsequent bits of the input data string, an output value is inverted and the output value is held when it is '0'. TFF 3 output when all the input data strings loading the parity are already inputted is the value of the parity bit.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a reception data erroneous detection circuit for detecting a data error in received data.

[0002]

2. Description of the Related Art Conventionally, for error detection and data compensation by data transmission, a parity code is generated and added to the original data regardless of whether it is odd parity or even parity. As described in "Conversion device in parallel" by JP-A-63-313919,
Generally, it is constituted by a parallel circuit. This example is shown in FIG. 4, in which a shift register 4 for inputting serial data and a clock and a parallel output of the shift register 4 are XORed.
In addition to the circuit 5, the output is used as a parity signal, and one bit is added to the serial data to obtain a data signal including a parity bit.

However, when the parity is generated by the parallel circuit, as the data length to which the parity bit is added increases, the number of input bits to the parity generation circuit increases and the scale of the parity generation circuit increases.

[0004] In the "parity circuit" disclosed in Japanese Patent Application Laid-Open No. 01-28739, a simple system having a small circuit scale is proposed by using flip-flops instead of parallel calculation of parity. According to this publication, a shift register and a timing signal output unit that outputs a timing signal in synchronization with predetermined code information among output signals of the shift register, a flip-flop circuit whose output signal is inverted by the timing signal, Selecting means for outputting an output signal of the flip-flop circuit in response to the determination of the state of the flip-flop circuit.

[0005]

However, the method disclosed in Japanese Patent Laid-Open No.
According to Japanese Patent Application Laid-Open No. 1-28739, there is a problem that the data length must be a fixed value due to its configuration.
There is also a problem that an error in received data cannot be detected only by parity check.

The present invention provides a reception data error detection circuit capable of coping with variable length data, in addition to the feature that the circuit scale does not increase even if the data length increases.

[0007]

SUMMARY OF THE INVENTION The present invention relates to a reception data error detection circuit used in a serial data transmission reception circuit, comprising: a head detection means for detecting the head of the reception data; and a tail detection means for detecting the tail of the reception data. And a flip-flop, which is initialized by detecting the head of the received data by the head detecting means and inverts an output value based on the received data, and wherein the data of the received data is detected when the tail detecting means detects the end of the received data. An error in the received data is detected by comparing a value with an output value of the flip-flop.

In the above-mentioned received data error detection circuit, a second data is initialized by the first detection of the received data by the first detecting means instead of the flip-flop, and is inverted when the received data value is "1". A flip-flop, and a parity detection function by counting the number of "1" in the received data.

In the above-mentioned reception data error detection circuit, an error of the reception data is detected for the reception data of a variable length.

Further, according to the present invention, since the parity can be generated without depending on the length of the data string by the circuit configuration using the T-FF, even if the data string to which the parity is added becomes long, There is a feature that the circuit scale does not increase. Therefore, the longer the data string to be subjected to parity addition, the greater the effect when the circuit size is reduced compared to the conventional method using an XOR circuit.

[0011]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments according to the present invention will be described.
This will be described in detail with reference to the drawings.

FIG. 1 is a circuit diagram of a reception data error detection circuit according to the present embodiment. In the figure, a head detection means 10 for detecting a head bit of serial reception data by a serial data transmission / reception circuit, a tail detection means 11 for detecting a tail bit of reception data, and an AND 12 for calculating a logical sum of the reception data and a clock. , And the output of AND12 is input to the clock terminal, and is input to the reset terminal and initialized upon detection of the first bit of the received data. As a result, the inverted output terminal is connected to the input terminal based on the received data, and the output value is inverted. D flip-flop 13 which performs an exclusive OR operation on the received data and the output of the flip-flop 13, a flip-flop which inputs the output of the end detection means 11 of the received data to a clock terminal, and receives the output of the NOR 14 as an input 15. Also, 16
Reference numeral 17 denotes a parity check unit including an AND 12 and a flip-flop 13. Reference numeral 17 denotes a delay unit that matches the result of the parity check with the timing of the tail detection unit.

Here, the head detecting means 10 of the received data detects the head bit string inserted on the transmitting side by a pattern matching circuit using a shift register, for example. Similarly, the reception data end detecting means 11 similarly detects the end bit string of the data string inserted on the transmission side by a pattern matching circuit using a shift register, for example. In this case, a serial bit sequence different from the first bit sequence and the last bit sequence is preferable. However, in the case of the same bit sequence, the first bit sequence and the last bit sequence can be detected while being distinguished cyclically.

The exclusive OR circuit 14 compares the received data value with the output value of the parity check unit 16 including the D flip-flop 13, thereby providing an error detection function for the received data.

In FIG. 1, a head bit string of a predetermined pattern is detected from a received data value by a head detection means, and the D flip-flop 13 is reset by the detection signal. Next, the parity check unit 13 checks the data following the head bit string for odd or even parity. The parity check unit 13 calculates the logical product of the clock and the received data, inputs the result to the clock terminal of the D flip-flop 13, supplies the inverted output of the D flip-flop 13 to the input terminal, and The presence or absence of an error in the data section is detected. Next, the output of the parity check unit 16 and the received data are exclusive-ORed by the Exc-OR circuit 14, and the delay unit 17 adjusts the timing for a predetermined time. At the output level of OR circuit 14, flip-flop 15 outputs Q
And With this configuration and operation, the presence or absence of an error in the received data can be detected.

In addition, instead of the flip-flop 13, there is provided a flip-flop which is initialized by detecting the head of the received data and inverts when the received data value is "1", and counts the number of "1" in the received data. By providing a parity detection function by having a parity detection function, detection corresponding to odd parity can be performed, and the reception data detection method can be easily converted together with the case of supporting even parity.

Further, even for variable-length serial received data, error detection of the received data can be performed, and a function as a parity can be provided.

FIG. 2 is a circuit diagram using a toggle flip-flop (T-FF) instead of the parity check unit 16 including the AND 12 and the D flip-flop 13 in FIG. . In FIG. 2, 1
Is an AND circuit for ANDing a start signal corresponding to the output of the head detection means 10 and the received data, 2 is an AND circuit for ANDing the inverted signal of the received data and the start signal, 3 is the set terminal of the output of the AND circuit 1, A toggle flip-flop (T-FF) that outputs an output of the AND circuit 2 to a reset terminal, input of received data, and an inverted clock signal to a clock terminal to output a parity signal.

In FIG. 2, a signal "start" representing the head of an input data string, an input data string "data", and a "clock" are represented by a toggle flip-flop (T).
-FF) 3 and the output of T-FF 3 becomes parity. When an output "start" signal, which is a time when the head bit string of the head detection means 10 is detected, is given, that is, at the head timing of the input data, the T-FF3 is set (1) or reset (0) and initialized. In the second and subsequent bits of the input data string, the input data string performs an operation of 1: output value inversion (change) 0: output value hold (no change) The output of the T-FF3 at the time when all the input data strings to which parity is added is the parity bit value.

[Explanation of Operation of this Embodiment] The operation of this embodiment will be described below.

According to FIG. 1, the flip-flop 10 by the head detecting means of the received data is initialized to "0". Each time "1" is received as the received data value, the output of the flip-flop 10 is inverted. Since the output of the flip-flop 11 by the end detection means of the received data is a parity output, a bit error of the received data can be detected.

Referring to FIG. 2, the operation of setting the initial value will be described first with reference to the timing chart of FIG.
The initial setting of the T-FF 3 is performed at the fall of the clock by the start bit of the input data string and the start bit input at the same timing as the start bit. In the case of the circuit of FIG. 2, when the leading data is 1: 1 (set) When the leading data is 0: 0 (reset). According to FIG. 2A, when the start bit is 1 and the data is 1, the output of the AND circuit 1 becomes 1 and T-
FF3 is set. In addition, in the waveforms at the end of the input data shown in FIG. 2B, after the last bit of the data string is input, 0 and 1 bits are generated as parity. The initial setting changes depending on whether the parity to be generated is an even number or an odd number. Conversely to FIG. 2, when the leading data is 1: 0 (reset) When the leading data is 0: 1 (set). In FIG. 2, it is assumed that the input data and the start signal change at the rising edge of the clock, and the T-FF 3 is described as the falling edge of the clock to avoid the simultaneous change of the input data and the clock. I have. As long as the timing guarantee to avoid the simultaneous change of the input change of the T-FF 3 and the clock change is secured,
The T-FF3 does not need to change at the falling edge of the clock.

The T-FF 3 shown in FIG. 2 operates at the falling edge of the clock when data is 1: output value inversion (change) When data is 0: output value is held (no change) Therefore, according to the number of 1s in the input data sequence,
The output value of T-FF3 is determined, and the output value of T-FF3 can be used as parity.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The operation of the parity check unit will be described below as a specific example with reference to FIG.

When the number of bits in the input signal data sequence is 9,
The parity bit is set to 1, and even parity is used as a condition.
The input data sequence is assumed to be input data: 1, 0, 1, 1, 0, 0, 0, 1, 0. First, since the first bit is 1, T-FF3 is initialized to 1 by this 1 and the start bit. From the second bit on, the output of the T-FF3 changes only when the input data is 1, so that the output of the T-FF3 is
It changes at the 4th and 8th bits. Therefore, the T-FF output value for the above 9 bits of input data is the output of T-FF3: 1, 1, 0, 1, 1, 1, 1, 0, 0, and T-FF after inputting the last bit of the data string. Since the output of -FF3 is 0, the parity is 0.

[0026]

As described above, according to the present invention, it is possible to provide a received data error detection circuit which can cope with variable length data without increasing the circuit scale even if the data length becomes long.

Since the shift register is a group of flip-flops, from the viewpoint of the circuit scale, XO
Although the effect is greater than increasing R,
This shows that the effect of preventing an increase in circuit scale by the method using the FF is remarkable.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of an embodiment according to the present invention.

FIG. 2 is a circuit diagram of an embodiment according to the present invention.

FIG. 3 is a signal timing chart according to the embodiment of the present invention.

FIG. 4 is a circuit configuration block diagram of a conventional system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 AND circuit 2 AND circuit 3 Toggle flip-flop (TFF) 4 Shift register 5 XOR circuit 10 Head detection means (flip-flop) 11 End detection means (flip-flop) 12 AND 13 D flip-flop 14 Exclusive OR 15 Flip-flop Step 16 Parity generation circuit 17 Delay circuit

Claims (3)

[Claims] 1. A reception data error detection circuit used in a serial data transmission reception circuit, wherein: a head detection means for detecting the head of the reception data; an end detection means for detecting the end of the reception data; A flip-flop, which is initialized by detecting the head of data and whose output value is inverted based on the received data,
A reception data error detection circuit for detecting an error in the reception data by comparing a data value of the reception data with an output value of the flip-flop when the tail detection means detects the end of the reception data. 2. The reception data error detection circuit according to claim 1, wherein the reception data is initialized by a head detection of the reception data by the head detection means instead of the flip-flop, and when the reception data value is “1”. A reception data error detection circuit comprising: a second flip-flop for inverting; and a parity detection function by counting the number of "1" in the reception data. 3. The reception data error detection circuit according to claim 1, wherein an error in the reception data is detected with respect to the reception data having a variable length.