JPH1155231A - Serial interface device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the throughput of a micro processor by primarily accumulating received data converted in parallel in a shift register or an UART part by means of a FIFO system and transferring it to the micro processor. SOLUTION: A data buffer part 71 is provided between the shift register 61, the UART part 1 and the incorporated micro processor 2. Received data which is converted in parallel in the shift register 61 or the UART part 1 is primarily stored in the FIFO system and is transferred to the micro processor 2. A status buffer part 71 primarily stores the check result of parity and the like by the FIFO system and it is transferred to the micro processor 2. The detection of communication speed which is decided on a user terminal 200-side in one way, the setting of a clock based on the detection and communication speed, the reception and the analysis of an AT command and the format setting of the UART part based on the analysis can be realized without depending on the software processing of the incorporated micro processor 2.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a serial interface device for interposing communication data between a user terminal device (DTE) such as a personal computer and a modem to perform a process of transferring communication data.

[0002]

2. Description of the Related Art Conventionally, as a serial interface device of this kind, a U which is unitized to perform transmission and reception of asynchronous serial data to a user terminal device and serial / parallel conversion (serial conversion and parallel conversion) of transmitted / received data has been known.
There are provided an ART part and a microprocessor having a built-in microprocessor that receives an AT command from the UART part and executes processing such as modem control and data transfer control.

In this case, the UART unit is interposed between the user terminal device and the microprocessor, and transfers commands and data received from the user terminal device and converted in parallel to the microprocessor as they are. The microprocessor is a UA
The RT unit senses whether or not the command or data has been received by an interrupt process, and as soon as the UART unit receives the command or data, shifts to a processing state for receiving the command or data from the UART unit.

[0004]

In this type of serial interface device, the asynchronous serial data communication speed with respect to the user terminal device is unilaterally determined by the user terminal device, and commands and commands from the user terminal device are transmitted. Data transmission is performed randomly. For this reason,
In the above-described device, the processing load of the microprocessor that executes the processing in response to the command or the data randomly and largely fluctuates. In order to cope with this load fluctuation, a microprocessor having a large processing capacity in accordance with the peak of the load fluctuation is required, but this is a major hindrance to simplification of the apparatus configuration and cost reduction. Was.

The present invention relates to a serial interface device comprising a UART unit and a microprocessor, which reduces the processing capacity required for the microprocessor, thereby simplifying the device configuration and reducing the cost. The purpose is to be able to achieve.

[0006]

SUMMARY OF THE INVENTION In order to solve this problem, the present invention provides a UART unit for transmitting / receiving asynchronous serial data to / from a user terminal device and performing serial / parallel conversion of the transmitted / received data. A serial interface device comprising a microprocessor for executing modem control, data transfer control, and the like based on a received command of the user terminal device, wherein a first character of an AT command transferred asynchronously serially from the user terminal device. Start bit detection means for detecting whether or not the start bit has been received, and a speed for determining the communication speed of the user terminal device by measuring the time width of the start bit in response to the start detection of the detection means. A measuring means and a clock having a speed corresponding to the judgment speed of the measuring means are generated. A clock generating means, a shift register for sampling and detecting the bit data after the start bit using the clock generated by the clock generating means, and performing a parallel conversion on a character-by-character basis; Format setting means for setting an asynchronous serial communication format in the UART section based on the received data. The received data converted in parallel by either the shift register or the UART section is temporarily stored in a FIFO format. And a data buffer unit to be transferred to the microprocessor.

As a result, the processing capability required for the microprocessor can be reduced, so that a serial interface device with a simplified configuration and reduced cost can be obtained.

[0008]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention provides a UART unit for transmitting / receiving asynchronous serial data to / from a user terminal device and performing a serial / parallel conversion of the transmitted / received data, A microprocessor for executing modem control, data transfer control, and the like based on the received command, and a start for detecting whether reception of a start bit of a first character of an AT command transferred asynchronously from the user terminal has started. Bit start detecting means, speed measuring means for determining the communication speed of the user terminal device by measuring the time width of the start bit in response to the start detection of the detecting means, A clock generating means for generating a clock of a speed, and a clock generated by the clock generating means. A shift register that samples and detects the bit data after the start bit using a clock and performs parallel conversion in character units, and sets an asynchronous serial communication format in the UART section based on the character data converted in parallel by this register. And a data buffer unit for temporarily storing received data converted in parallel by either the shift register or the UART unit in a FIFO format and then transferring the received data to the microprocessor. Thus, an effect is obtained that the processing capacity required for the microprocessor is reduced, and the apparatus can be simplified and the cost can be reduced.

According to a second aspect of the present invention, in the first aspect, only two consecutive received characters in the latest order are always obtained, and it is determined whether or not the two characters are the first character string of the AT command. When it is determined that the character string is the first character string of the AT command, the UART unit includes format recognition means for analyzing the type of parity from the parity bit of the character and generating format information. As a result, the communication format setting for the UART unit can be performed without depending on the software processing of the microprocessor.

According to a third aspect of the present invention, in the first or second aspect, only two consecutive received characters in the latest order are always obtained, and the two characters are A
Judge whether it is the first character string of the T command,
When it is determined that the character string is the first character string of the AT command, a format recognizing means for analyzing the type of parity from the parity bit of the character and generating format information is provided, and a parity check at the time of reception is performed based on the format information. In addition, parity is added at the time of transmission, whereby the format of transmission / reception data can be determined without depending on software processing of the microprocessor.

[0011] The invention described in claim 4 is the first to third aspects of the present invention.
In any one of the above, the URAT unit includes a status buffer unit for temporarily storing a check result of parity or the like performed at the time of receiving asynchronous serial data in a FIFO format and transferring the result to a microprocessor. It is possible to further reduce the temporary concentration of the processing load.

[0012] The invention according to claim 5 is the invention according to claims 1 to 4.
In any one of the above, the number of serial shift stages of the shift register that performs the bit detection after the start bit is sampled and converted in parallel on a character basis is extended, and the bit data values in this extended shift stage sequence become "0" all at once. The break signal is detected depending on whether or not the break signal is detected, whereby the break detection can be reliably performed with the addition of a simple configuration.

[0013] The invention according to claim 6 is the invention according to claims 1 to 5.
In any one of the above, as a clock generation unit that generates a clock having a speed corresponding to the determination speed of the speed measurement unit, a clock having a duty width that is an integer multiple of the reference signal is frequency-divided and the integer ratio to the reference signal is different. By intermittently generating and inserting a clock with a duty width and inserting the clock, a clock whose frequency ratio with respect to the reference signal does not have an integer relationship is also generated, thereby enabling a fine setting of the clock speed. It becomes possible.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. FIG. 1 shows a schematic configuration example of a serial interface device according to an embodiment of the present invention.

An apparatus 100 shown in FIG. 1 is provided between a user terminal (DTE) 200 and a modem 9 to execute an AT command and execute a data transfer process in accordance with the AT command. Unit 1, built-in microprocessor 2, clock generation circuit 32, start bit start detection unit 4, communication speed measurement unit 5, shift register 61, break detection circuit 62, FIFO memory 7,
It comprises a format setting section 8 and the like.

The UART unit 1 includes a serial reception unit 11 and a status generation unit 12, and a serial transmission unit 13 and a parity generation unit 14. The UART unit 1 transmits and receives asynchronous serial data to and from the user terminal device 200 and transmits / receives the transmitted / received data directly. Perform parallel conversion.

The built-in microprocessor 2 executes control of the modem 9 and control of data transfer to the modem 9 based on a reception command from the user terminal device 200.

The start bit start detecting section 4 is constituted by using a hardware logic circuit, and receives the first AT command transmitted from the user terminal device 200 in an asynchronous serial manner.
It is detected by hardware whether the start bit of the character has been received. This detection is performed when the high level (“1”) continuously appears on the serial transmission line connected to the user terminal device 200 and the serial transmission line goes to the low level (“0”). This is done by monitoring whether the

The communication speed measuring unit 5 comprises a counter 51 and a decoder 52. The communication speed measuring unit 5 receives the start detection of the start detecting unit 4 and counts and measures the time width of the start bit. Determine the communication speed. The counter 51 counts the low level time width of the start bit in response to the start detection of the start detection unit 4. Decoder 52 converts the count value into speed data.

The clock generation circuit 32 includes a reference oscillator 31
By performing variable frequency division processing on the frequency reference signal φ generated by the above, a clock having a speed corresponding to the determination speed of the speed measuring unit 5 is generated.

The shift register 61 operates using a clock generated by the clock generation circuit 2 in accordance with the communication speed, performs sampling detection of the bit data after the start bit, and performs parallel conversion in character units. The shift register 61 can form a part of the break detection circuit 62 by expanding the number of shift stages, which will be described later in detail.

The format setting section 8 is composed of a 2-byte register 81 and a format recognizing section 82. If two consecutive received characters in the latest order are the first character string of the AT command, the format setting section 8 starts from the parity bit of the character and sets the parity bit. The format information is generated by analyzing the type. The register 81 stores two consecutive
It always acquires and holds only one received character. The format recognition unit 82 determines that the character of the register 81 is A
The first character string of the T command ("AT" or "a
t ") is logically determined by hardware as to whether
The first character string of the T command ("AT" or "a
If t ”) is determined, the type of parity is analyzed from the parity bit of the character to generate format information. The format information generated in this way is the status generation unit 12 of the UART unit 1. And the parity generation unit 14. The UART unit 1 performs a parity check at the time of reception and a parity addition at the time of transmission based on the format setting information.

The FIFO memory 7 forms a data buffer 71 and a status buffer 72 in FIFO format. The data buffer unit 71 is interposed between the shift register 61 and the UART unit 1 and the microprocessor 2, and temporarily stores reception data converted in parallel by either the shift register 61 or the UART unit 1 in a FIFO format. And then deliver it to the microprocessor 2.
The status buffer unit 71 temporarily stores, in the FIFO format, a check result of parity or the like performed when the URAT unit 1 receives asynchronous serial data, and transfers the result to the microprocessor 2.

The modem 9 is connected between the microprocessor 2 and the communication line L, and performs data transmission / reception via the line L under the control of the microprocessor 2.

FIG. 2 shows a specific configuration example of the clock generation circuit. The clock generation circuit 32 shown in the figure includes a data selection circuit 321, a comparison reference data memory 322, a clock counter 323, a data comparison circuit 324, and a decoder 3.
25, a timing adjustment circuit 326 and the like.

The selection circuit 321 uses the speed data Ds generated by the speed measuring section 5 as search data, and searches and selects the comparison reference data Dx corresponding to the search data from the comparison reference data memory 322. .
The selected comparison reference data Dx is stored in the data comparison circuit 324.
Given to.

The comparison reference data memory 322 is configured using a ROM or a non-volatile memory. The memory 322 stores a large number of comparison reference data Dx set in advance corresponding to various speed data Ds in a data table format. Each comparison reference data Dx has four time reference data Dx1, Dx2, Dx3, respectively.
Dx4. Each time reference data Dx
1, Dx2, Dx3, Dx4 are 2 of the generated clock CK.
In the case where the cycle is a unit of repetition, it is set so that each time width from the starting point of the repetition to the half cycle, the first cycle, the 3/2 cycle, and the second cycle is determined.

The clock counter 323 includes the reference oscillator 3
The frequency reference signal φ generated in step 1 is counted. The count content Cx is provided to the data comparison circuit 324.

The comparison circuit 324 stores the comparison reference data D
The data value is compared between x and the count content Cx. This comparison is based on the time reference data (Dx1 to Dx
It is performed every 4). The comparison output (P1 to P4) is also performed for each of the time reference data (Dx1 to Dx4).
The comparison outputs (P1 to P4) are input to the decoder 325.

The decoder 325 outputs the comparison output (P1 to P1).
The clock CK is generated based on P4). In the clock generation in this case, the two periods of the generated clock CK are used as a unit of repetition, and the respective time widths from the starting point of the repetition to the half period, the first period, the 3/2 period, and the second period are compared with each other. The determination is performed by the output (P1 to P4).

The timing adjustment circuit 326 resets and initializes the count content Cx of the clock counter 323 to zero every time the above-mentioned repetition unit makes one cycle.

FIG. 3 illustrates a part of the clock generated by the clock generation circuit 32 described above.

In the figure, clocks CK1 and CK3
The low duty width and the high duty width are unified over the entire cycle of the clock. Such a clock is based on the time reference data (Dx1 to Dx
This is realized by equalizing the differences between the data values in 4). In this case, the frequency (speed) of the generated clock has an integer relationship with the frequency ratio with respect to the reference signal φ, and the frequency ratio can be arbitrarily set according to the magnitude of the difference between the data values.

The clock CK2 differs from the other parts only in the duty width (4) in the 3/2 cycle of the two-cycle repetition unit of the clock. Such a clock is obtained by making the data value difference in the time reference data Dx3 for setting the time width up to the 3/2 turn different from the data value difference in the other time reference data Dx1, Dx2, Dx4. Is achieved. In this case, a clock having a duty ratio having a different integer ratio with respect to the reference signal φ is intermittently inserted. As a result, as a whole, a clock whose frequency ratio with respect to the reference signal φ does not have an integer relationship is also generated. be able to.

As described above, in the above-described clock generation circuit 32, a clock having a duty width that is an integral multiple of the reference signal φ is frequency-divided and generated, and a clock having a duty width having a different integer ratio to the reference signal φ is intermittently generated. By generating the frequency division and inserting it, a clock whose frequency ratio with respect to the reference signal φ does not have an integer relationship can also be generated.

FIG. 4 shows a configuration example of the break detection circuit 62. The break signal is defined as a 13-bit continuous "0" signal. As shown in the figure, the break signal is detected by sampling the bit data after the start bit and performing parallel conversion in character units. The number of serial shift stages of the shift register 62 is extended, and a logic gate (13) for detecting whether or not the bit data values in the extended shift stages (F1 to F13) all become "0" at the same time.
By providing the input NOR) 63, the operation can be performed relatively easily.

FIG. 5 shows the relationship between the AT code pattern and the format. As shown in the figure, the head character string of the AT command is formed by a character code of "AT" or "at". By analyzing a bit data pattern (bit data) expressing this code,
Bit length, parity type (E: even number, O: odd number, M:
Mark, S: space, N: none), and stop bit length. For example, the code pattern “7E1” in (1) represents a bit length of 7, an even parity (E), and a stop bit length of 1.

FIG. 6 shows an example of format analysis using parity bits. As shown in the figure, the format of the data asynchronously transferred from the user terminal device can be determined from the parity bit of the head character string (“AT” or “at”) of the AT command.

The above-described format analysis is performed by hardware logic processing in the format recognition unit 82 (FIG. 1).
The analysis result is transferred to the URAT unit 1 as format setting information, and is held so that the microprocessor 2 can read it at any time.

As described above, one embodiment of the present invention has been described. As described above, in the serial interface device according to the present invention, the detection of the communication speed unilaterally determined on the user terminal device 200 side, Setting of the clock and the communication speed, reception and analysis of the AT command, and format setting of the UART section based on the analysis can be realized without depending on the software processing of the built-in microprocessor 2. In addition, by passing the received data to the microprocessor 2 via the FIFO-type buffer 71, the processing load on the microprocessor is reduced, and the time concentration of the load is corrected. Load fluctuation peaks can be greatly reduced. As a result, even a microprocessor having a relatively small processing capability can be sufficiently used, so that the device configuration can be greatly simplified and the cost can be reduced.

[0041]

As described above, according to the present invention, the UART
In a serial interface device configured by using a unit and a microprocessor, it is possible to reduce the processing capacity required for the microprocessor, thereby achieving simplification of the device configuration and cost reduction. An advantageous effect is obtained.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a schematic configuration example of a serial interface device according to an embodiment of the present invention;

FIG. 2 is a block diagram illustrating a specific configuration example of a clock generation circuit.

FIG. 3 is a waveform chart illustrating a part of a clock generated by a clock generation cycle;

FIG. 4 is a circuit diagram showing a configuration example of a break detection circuit;

FIG. 5 is a table and a waveform chart showing a relationship between an AT code pattern and a format.

FIG. 6 is a table showing an example of format analysis using parity bits.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 serial interface device 200 user terminal device 1 UART unit 11 serial reception unit 12 status generation unit 13 serial transmission unit 14 parity generation unit 2 built-in microprocessor 31 reference oscillator 32 clock generation circuit 4 start bit start detection unit 5 communication speed measurement unit REFERENCE SIGNS LIST 51 counter 1 52 decoder 61 shift register 62 break detection circuit 7 FIFO memory 71 data buffer section 72 status buffer section 8 format setting section 81 2-byte register 82 format recognition section 9 modem

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[Procedure amendment]

[Submission date] November 11, 1998

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] Claims

[Correction method] Change

[Correction contents]

[Claims]

Claims (6)

[Claims] 1. A UART unit for transmitting / receiving asynchronous serial data to / from a user terminal device and performing a serial / parallel conversion of the transmitted / received data, and executes a modem control and a data transfer control based on a reception command from the user terminal device. A start bit detecting means for detecting whether or not the start bit of the first character of the AT command transferred asynchronously from the user terminal device has been started, and receiving the start detection of the detecting means. Speed measurement means for determining the communication speed of the user terminal device by measuring the time width of the start bit, clock generation means for generating a clock having a speed corresponding to the determination speed of the measurement means, Bit after the start bit using the clock generated by the means A shift register that detects sampling of data and performs parallel conversion in character units;
Format setting means for setting the asynchronous serial communication format in the UART section based on the character data converted in parallel by the register; and FIFO converting the received data converted in parallel by either the shift register or the UART section. A data buffer unit for temporarily storing the data in a format and then transferring the data to the microprocessor. 2. A method for constantly acquiring only two consecutive received characters in the latest order, determining whether the two characters are the first character string of the AT command, and determining that the two characters are the first character string of the AT command. In the case where the format is determined, a format recognizing means for generating format information by analyzing the type of parity from the parity bit of the character is provided, and the asynchronous serial communication format setting in the UART section is performed using the format information. The serial interface device according to claim 1, wherein: 3. A method for constantly acquiring only two consecutive received characters in the latest order and determining whether the two characters are the first character string of the AT command, and determining that the two characters are the first character string of the AT command. In the case where the parity check is performed, a format recognizing unit is provided for analyzing the type of parity from the parity bit of the character to generate format information, and performs parity check at the time of reception and parity addition at the time of transmission based on the format information. 3. The serial interface device according to claim 1, wherein: 4. A URAT unit transmits a check result of parity or the like performed at the time of receiving asynchronous serial data to a FIFO.
4. The serial interface device according to claim 1, further comprising a status buffer unit that temporarily stores the data in an O format and transfers the data to a microprocessor. 5. The number of serial shift stages of a shift register that performs sampling detection of bit data after a start bit and performs parallel conversion on a character basis is extended, and the bit data values in the extended shift stages become "0" all at once. The serial interface device according to any one of claims 1 to 4, wherein a break signal is detected depending on whether or not the serial interface is activated. 6. A clock generating means for generating a clock having a speed corresponding to the judgment speed of the speed measuring means, which divides and generates a clock having a duty width that is an integral multiple of the reference signal and has a different integer ratio to the reference signal. 6. A clock according to claim 1, wherein a clock having a duty width is intermittently frequency-divided and inserted to generate a clock whose frequency ratio with respect to said reference signal does not have an integer relation. The serial interface device as described.