JPH07327028A - Multi-frame synchronization system - Google Patents

Abstract

PURPOSE:To reduce maximum detection time by detecting a multi-frame identification code from a bit stream having a already been stored and hold. CONSTITUTION:The system is made up of a cyclic counter 1 incremented for each bit of a bit stream and runs freely by using a bit number of 1 multi-frame for an upper limit, a memory circuit 5 storing the bit stream, a counter 2 counting a bit number of the bit stream, a control circuit 4 writing the bit stream to the memory circuit 5, a counter 3 whose count is incremented by a bit number of one frame, a control circuit 4 reading the content of the memory circuit 5 at a higher speed than a bit rate of the bit stream based on the count of the counter 3, a shift register 6 identifying a multi-frame identification code, an arithmetic circuit 8 calculating the count of the counter 3 based on the output of the shift register 6 and a comparator 9 comparing the output of the arithmetic circuit 8 and the output of the cyclic counter 1.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiframe synchronization system for performing multiframe synchronization in a system which receives a serial bitstream having a multiframe structure.

[0002]

2. Description of the Related Art Generally, a multi-frame used for serial data transmission is composed of a set of a fixed number of consecutive frames, and one multi-frame bit exists at a defined position of a bit string constituting one frame.

To detect multi-frame bits transmitted in the same series as serial data, each frame is extracted one bit at a time in one frame period, and a multi-frame identification code for one multi-frame is detected.

FIG. 7 is a block diagram of a conventional multi-frame synchronization system, and FIG. 8 is an explanatory diagram of a frame configuration showing the maximum detection time in the conventional multi-frame identification code detection.

As shown in the block diagram of FIG. 7, this type of multi-frame identification code detecting means is a counter 107 for counting the number of bits for one multi-frame.
, A shift register 103 for extracting the multi-frame identification code, and a decoder 104 for matching the multi-frame identification code are used.

Here, it is assumed that one frame is composed of a frame bit F of 1 bit at the beginning and serial data of 192 bits continuous thereafter, and one multiframe is composed of 6 frames. To do. The clock signal 102 is a clock signal having a 1-bit width that is synchronized with the bit stream signal 101, and the counter 107
Is 0 to 115 that can count 193 × 6 = 1158
7 counter.

The shift register 103 is a 6-bit parallel output shift register capable of holding a 6-bit multi-frame identification code, and the decoder 104 determines whether the outputs Q0 to Q5 of the shift register 103 match the multi-frame identification code. This is a circuit for determining whether or not.

Next, the operation of the multi-frame synchronization system of FIG. 7 will be described with reference to FIG.

The counter 107 increments by the clock signal 102, the control clock signal 108 output from the counter 107 is output at the timing of 193 × N (N = 0 to 5), and the shift register 103 is output at the timing of the control clock signal 108. He bitstream signal 10
1 is input.

The value of the control clock signal 108 is "965".
When it becomes (193 × 5), 6 is stored in the shift register 103.
The second bit is input, and the outputs Q0 to Q5 at this time are input to the decoder 104, and it is determined whether or not they match the multiframe identification code. If they do not match, the multi-frame sync signal 105 does not become active.

After that, the increment operation of the counter 107 is stopped for one clock period by the control signal 109 output when the counter 107 counts "1157", and thereafter, the multiframe identification code is detected in the same sequence as described above. To do. At this time, the operation is restarted from a position that is delayed by 1 bit relative to the previous sequence,
This operation is continued until the multi-frame identification code is detected.

When the outputs Q0 to Q5 are input to the decoder 104 and match the multiframe identification code, the multiframe synchronizing signal 105 is activated and the counter 1
Even when 07 becomes “1157”, the increment operation is not stopped and the counting operation of the counter 107 is continued in the multi-frame synchronized state.

[0013]

In the above-mentioned conventional example, the multiframe identification code cannot be detected unless the 1-bit F at the head multiframe bit position of the multiframe identification code matches the value "0" of the counter 107. ,
The maximum detection time becomes [1 multi-frame transmission time] x [total number of bits in 1 multi-frame], which requires a long time.

As a method for shortening the maximum detection time, there is a method disclosed in Japanese Patent Laid-Open No. 5-110554.

The maximum detection time according to the technique disclosed in this publication is [1 multiframe transmission time] × [total number of bits in 1 frame], which is shortened to 1 / the number of frames in 1 multiframe as compared with the conventional example. It's done, but it's still not fast.

Therefore, an object of the present invention is to provide a multi-frame synchronization system capable of shortening the detection time of a multi-frame identification code even when it takes a maximum detection time.

[0017]

A multi-frame synchronization system according to a first aspect of the invention is to add one frame by adding a frame identification bit to a fixed length of serial data, and construct one multi-frame by a predetermined number of the frames. A cyclic counter that starts operation upon reception of a bitstream, increments bit by bit of the bitstream, and runs freely with the number of bits of one multiframe as an upper limit; a memory circuit that stores and holds the bitstream; A first counter that counts the number of bits of the bitstream and outputs a control signal when a certain number of bits is reached; and a bitstream of the bitstream to the memory circuit until a control signal is output based on the count of the first counter. It operates by the control circuit for writing and the control signal of the first counter. The Start, incremented by the number of bits of one frame, and resets the count value when the count number is larger than a predetermined number of bits, then,
The content of the memory circuit is changed by a second counter that increments again by a bit number of one frame from a value that is larger than the previous count start value by one, and a counter signal of the second counter and a control signal of the first counter. A first determination circuit that reads out at a higher speed than the bit rate of the bit stream and determines whether the read pattern matches the multi-frame identification code, and the number of counters of the second counter based on the output of the first determination circuit And a second determination circuit that compares the output of the arithmetic circuit with the number of counters of the cyclic counter.

In the multi-frame synchronization method according to a second aspect of the present invention, the value of the constant number of bits of the first counter has a margin more than the minimum number of bits required for performing multi-frame synchronization, and the value of the multi-frame identification code is set. The detection operation is performed multiple times.

[0019]

According to the present invention, the increment is started at the same time as the reception of the bit frame, and the cyclic counter having the total number of bits of one multi-frame as the upper limit value is operated. At the same time, the bitstream is sequentially stored and held in the memory circuit, and when the number of bits reaches a certain number, the storage and holding operation is stopped by the output of the first counter which detects this. Next, the bit stream stored and held in the memory circuit is read out at a higher rate than the storage holding operation by the second counter that increments by one bit for one frame, and the read bit pattern matches the multi-frame identification code. It is determined whether or not there is.

When they do not match, the second counter is further incremented and the match determination is continued. When the count value of the second counter becomes larger than the fixed number of bits, the count value is reset, the value incremented by 1 from the previous count start value is incremented again by the number of bits for one frame, and the match determination is continued.

When they match, the arithmetic circuit calculates the leading bit position of the multi-frame from the counter value of the second counter at the time of matching, and compares the calculated value with the value of the cyclic counter that is operating first. The time when the two values match is the start bit position of the multiframe of the current bitstream. Further, the value of the fixed number of bits is one frame less than two multiframes because one multiframe has to be included in the stored and held bitstream without interruption.
Frame) The minimum number of bits is required.

In the second aspect, in the process of detecting the multi-frame identification code, the same pattern as the multi-frame identification code may be generated due to the arrangement of the data, and it is assumed that this pattern is captured as the multi-frame identification code. This is called multi-frame synchronization, and this is not the original synchronization, which hinders later data transmission, and it is necessary to resynchronize again thereafter. The probability of detecting a pseudo multi-frame is reduced by setting the value of the fixed number of bits to more than 11 frames and performing multi-frame identification code detection a plurality of times.

[0023]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of a multi-frame synchronization system according to an embodiment of the present invention. FIG. 2 is an explanatory diagram of the maximum detection period of the multi-frame identification code in the multi-frame synchronization system according to the embodiment of the present invention.

1 is synchronized with the bit stream signal 12,
It is a cyclic counter that increments by the clock signal 10 having a cycle of 1-bit width of the bit stream signal 12 and continues the counting operation with the count value "1158" as the upper limit. 2 is a clock signal 10
A clock signal which is incremented by, outputs the count value thereof, and outputs the control signal 13 when the count number reaches “3281”, the clock signal 3 which is started by the control signal 13 and is faster than the clock signal 10. 11
The counter 4 which increments the count value and outputs the count value and holds the count output by the control signal 16 receives the count output of the clock signal 10 and the counter 2 and the count output of the clock signal 11 and the counter 3 and inputs the control signal 13 Switch the input of both counters and output,
In addition, the control circuit 5 which activates either the clock signal 10 or the clock signal 11 by the control signal 13 and outputs it as the control clock signals 14 and 15, respectively, has a bit stream signal 12 of 1 bit based on the output of the control circuit 4. A memory circuit for holding or outputting each of them, 6 is a shift register for shifting the output of the memory circuit 5 by 1 bit by the control clock signal 15 and outputting in 12-bit parallel, 7 is a continuous multi-frame output of the shift register 6 A decoder that determines whether or not the two identification codes match, and outputs a control signal 16 if they match.
Reference numeral 8 is an arithmetic circuit for calculating the count output of the counter 3 by the control signal 16 to calculate the multi-frame head bit position, and 9 is a comparison between the output of the cyclic counter 1 and the output of the arithmetic circuit 8. Signal 1
This is a comparator that outputs 7.

Next, the operation of the multi-frame synchronization system of the embodiment shown in FIG. 1 will be described with reference to FIG.

As shown in FIG. 2, one frame bit F is added to the head of 192-bit serial data to obtain 1
A frame, and further, a bit stream that configures 6 frames as 1 multi-frame, a clock signal 10 having a 1-bit width of the bit stream synchronized with this bit stream, and a clock signal 1 synchronized with the clock signal 10.
A clock signal 11 having a bit rate four times 0 is input to the control circuit 4.

When performing multi-frame synchronization,
Considering the case where the maximum detection time is required, it is assumed that bitstream reception is started at a position delayed by 1 bit from the head bit of 1 multiframe. Cyclic counter 1
And the counter 2 increments at the falling edge of the clock signal 10.

The clock signal 10 and the counter output of the counter 2 are input to the control circuit 4. The control circuit 4 selects the count value of either the counter 2 or the counter 3 by the control signal 13 of the counter 2 and outputs it to the memory circuit 5. Further, since the clock signal 10 is used as the write signal to the memory circuit 5 and the clock signal 11 is used as the read signal from the memory circuit 5, either one of the clock signals is activated by the control signal 13 and the memory circuit 5 is activated.
Output to.

A timing chart at the start of bitstream reception will be described with reference to FIG. FIG. 3 is a timing chart at the start of bitstream reception in the multi-frame synchronization system according to the embodiment of the present invention.

The counter value output from the control circuit 4 is used as an address, and the bit stream signal 12 is transferred to the memory circuit 5 by the rising edge of the control clock signal 14 (active clock 10) output from the control circuit 4.
Are sequentially written into. At this point, the control clock signal 15 is not output.

The cyclic counter 1 has a maximum number of bits of one multi-frame (193 × 6 = 1158)
Repeat the count for 1157. Also, the counter 2 has a total number of bits of 17 frames (193 × 17 = 3281).
Is counted up to 0 to 3280.

Next, FIG. 4 shows a timing chart when the reception of the bit stream for 17 frames is completed.

FIG. 4 is a timing chart at the end of reception of a multi-frame synchronization type bit stream according to an embodiment of the present invention.

After the counter 2 has counted "3280", the output of the counter 2 is reset to "0" at the next falling edge of the clock signal 10. At the same time, the control signal 13 is activated to instruct the control circuit 4 to switch the counter output, stop the output of the control clock signal 14, and start the output of the control clock signal 15.

Further, the control signal 13 is input to the counter 3 to start the operation of the counter 3. The counter 3 has a clock signal 11 having a bit rate four times that of the clock signal 10.
Increment by the falling edge of. After the control signal 13 becomes active, the count value of the counter 3 is used as an address, and the bit stream stored in the memory circuit 5 is read at the rising edge of the control clock signal 15 output from the control circuit 4.

At this time, the counter 3 increments the count value by the number of bits of one frame (193), whereby the bit string at 193 bit intervals is extracted from the bit stream and the multi-frame identification code is searched. When the count value of the counter 3 becomes equal to or more than the total number of bits (3281) of 17 frames, the count value is set to a position advanced by 1 bit from the previous count start position, and the increment is restarted by 193 bits.

In FIG. 4, the count value changes from 0 → 193 → 386 → 579 → ... →→ 2895 → 3088 → 1 → 194 → .... The bits read from the memory circuit 5 are sequentially input to the shift register 6 at the falling edge of the control clock signal 15.

Now, the multi-frame identification code is "100.
110 ″.

If this pattern is output from the memory circuit 5, it can be considered that the F bit position has been tentatively captured, but this is not certain. Because, as a result of performing bit extraction from the data part other than F bits at 193 bit intervals,
This is because the bit string may be "100110".

Further, it is predicted that the "100110" pattern of the data is detected by chance and the F bit position is fixed at this point. Incidentally, this is called pseudo multi-frame synchronization.

When the present invention is implemented, pseudo multi-frame synchronization must be avoided because the original multi-frame synchronization is performed.

In the present embodiment, in order to increase the probability of capturing the original F bit position, after detecting "100110", the multiframe identification code detection operation is performed again for the bitstream for one multiframe. , The "100110" pattern is detected twice in succession, the F bit position is first determined.

As a result, the probability of performing the pseudo multi-frame synchronization acquisition is reduced to 1/64 as compared with the case where the multi-frame identification code is detected only once.

Specifically, the output of the shift register is set to 12
The bits "100110100110" are detected.

When the decoder 7 detects this pattern, it activates the control signal 16 to stop the operation of the counter 3, and holds and outputs the count value indicating the last bit position of this pattern. In FIG. 5, “10011010011
The timing chart at the time of detecting the pattern of "0" is shown.

FIG. 5 is a timing chart when the pattern "100110100110" of the multi-frame synchronization system according to the embodiment of the present invention is detected.

When the decoder 7 detects this pattern, the control signal 16 is activated, the operation of the counter 3 is stopped, the count value indicating the last bit position of this pattern is held, and the arithmetic signal 8 is generated by the control signal 16. Is operated to calculate the leading bit position of the multi-frame identification code from the count value of count 3.

In this embodiment, since the reception of the bit stream signal 12 is started from the position delayed by 1 bit from the head bit of the multi-frame, "10011010011"
The counter value of the counter 3 at the time when the "0" pattern is detected is "3280".

Here, the operation of the arithmetic circuit 8 will be described with reference to FIG.

FIG. 6 is an operation explanatory diagram of the arithmetic circuit 8 of the multi-frame synchronization system according to the embodiment of the present invention.

In FIG. 6, since "3280" is the last bit position of the second multiframe identification code, the first bit position of the first multiframe identification code is 3280-((193 * 5) +1158) = It becomes 1157. The calculation circuit 8 performs this calculation and outputs the result.

This is compared with the output of the cyclic counter 1 by using the comparator 9, and the point of coincidence is the multi-frame head bit position in the bit stream.

The operation time at this time, that is, the maximum detection time requires only 4 multiframes as shown in FIG. 2, and when the conventional example is used in the same multiframe configuration as this embodiment, a maximum of 1158 frames is obtained. It can be remarkably shortened as compared with the case of requiring.

Further, Japanese Patent Laid-Open No. 5-110, which is an improvement of the conventional example.
1158/6 = 19 when using the technique of Japanese Patent No. 554
It can be shortened compared to 3 frames.

By the way, the shift register 6 of this embodiment
Reads the contents of the memory circuit 5 at a speed higher than the bit rate of the bit stream by the counter number of the counter 3 and the control signal of the control circuit 4, and determines whether the read pattern matches the multi-frame identification code. However, it is possible to use a comparison circuit, and as a result, a determination circuit for comparing and determining the counter number of the counter 3 and the control signal of the control circuit 4 may be used. By the way, this is the first
Use as a judgment circuit.

Further, the comparator 9 of this embodiment compares the output of the shift register 6 with the arithmetic circuit 8 for calculating the counter number of the counter 3, and the output of the arithmetic circuit 8 with the counter number of the cyclic counter 1. Therefore,
A comparison circuit can be used, and as a result, a determination circuit that determines the output of the arithmetic circuit 8 and the counter number of the cyclic counter 1 for comparison can be used. Incidentally, this is referred to as a second determination circuit.

As described above, in the multi-frame synchronization method of this embodiment, a frame identification bit is added to a fixed length of serial data to form one frame, and a predetermined number of the frames make up one multi-frame. A cyclic counter 1 that starts operation upon reception of a bitstream, increments bit by bit of the bitstream, and performs free-running with the number of bits of one multiframe as an upper limit in a receiving circuit for receiving
And a memory circuit 5 for storing and holding the bit stream.
And a counter 2 which counts the number of bits of the bit stream and outputs a control signal when a certain number of bits is reached.
And a control circuit 4 for writing the bit stream to the memory circuit 5 until a control signal is output based on the count number of the first counter.
The operation is started by the control signal of the control circuit 4, the number of bits of one frame is incremented by one, the count value is reset when the count number exceeds a certain number of bits, and then the count value is incremented by 1 from the previous count start value. A second counter composed of a counter 3 for incrementing the number of bits of one frame again from a large value; and the counter 3
Whether the content of the memory circuit 5 is read at a speed higher than the bit rate of the bit stream by the counter number of the second counter and the control signal of the control circuit 4, and the read pattern matches the multi-frame identification code. First composed of shift register 6 for judging whether
An arithmetic circuit 8 for calculating the number of counters of the second counter composed of the counter 3 by the output of the first judgment circuit composed of the judgment circuit and the shift register 6, the output of the arithmetic circuit 8 and the counter of the cyclic counter 1. The second determination circuit is composed of a comparator 9 for comparing the number with the second determination circuit, which can be the embodiment of claim 1.

The multi-frame synchronization system of this embodiment operates as follows.

At the same time when the bit frame is received, the increment is started, and the cyclic counter 1 having the total number of bits of one multi-frame as the upper limit value is operated. At the same time, the bit stream is sequentially stored and held in the memory circuit 5, and when the number of bits reaches a certain number of bits, the storage and holding operation is stopped by the output of the first counter which is the counter 2 which detects this. Next, the bit stream stored and held in the memory circuit 5 is read out at a higher speed than the storage and holding operation by the second counter composed of the counter 3 which increments the number of bits for one frame, and the read bit pattern identifies the multi-frame. Determine if it matches the code.

When the bit pattern read from the memory circuit 5 does not match the multi-frame identification code,
Further, the second counter, which is the counter 3, is incremented, and the match determination is continued. Second consisting of counter 3
When the count value of the counter becomes larger than the fixed number of bits, the count value is reset, the value incremented by 1 from the previous count start value is incremented again by the number of bits for one frame, and the match determination is continued.

When the bit pattern read from the memory circuit 5 coincides with the multi-frame identification code, the arithmetic circuit 8 calculates the leading bit position of the multi-frame from the counter value of the second counter composed of the counter 3 at the time of coincidence. , The value of the cyclic counter 1 operating first is compared with the calculated value. The time when the two values match is the start bit position of the multiframe of the current bitstream. In addition, the value of the fixed number of bits must be one frame less than two multiframes (11 frames) because one multiframe must be included in the stored bitstream without interruption. The minimum number of bits is required.

Therefore, in the method of detecting the multi-frame identification code from the bit stream having the multi-frame structure of the present embodiment, the multi-frame is already stored and held by the circuit for storing and holding the bit stream. By performing the detection operation of the identification code, the maximum detection time can be shortened.

Therefore, in the method of detecting a multiframe identification code from a bitstream having a multiframe structure, the memory circuit 5 for storing and holding the bitstream is used to detect the multiframe identification code for the bitstream already stored and held. Since the detection operation of
If the multi-frame identification code is not detected by scanning the number of bits for one multi-frame as in the conventional example, the maximum number of bits can be increased as compared with the method for shifting the number of bits for the next one multi-frame by shifting 1 bit. When the detection time is required, the multiframe identification code can be detected in a short time.

In the multi-frame synchronization method of the present embodiment, the value of the constant number of bits of the first counter, which is the counter 2, is set to have a margin larger than the minimum number of bits required for multi-frame synchronization, so that the multi-frame synchronization is performed. The detection operation of the identification code is performed a plurality of times, and this can be the embodiment of claim 2.

In this embodiment, in the process of detecting the multi-frame identification code, the same pattern as the multi-frame identification code may be generated due to the arrangement of the data, and it is assumed that this pattern is captured as the multi-frame identification code. This is called multi-frame synchronization, and this is not the original synchronization, which hinders later data transmission, and it is necessary to resynchronize again thereafter. The probability of detecting a pseudo multi-frame is reduced by setting the value of the fixed number of bits to more than 11 frames and performing multi-frame identification code detection a plurality of times.

Therefore, the multi-frame identification code is detected twice consecutively even for the pseudo multi-frame synchronization acquisition which is generated by detecting the same pattern as the multi-frame identification code which is accidentally generated in the data string. As a result, the capture probability can be reduced.

[0068]

As described above, according to the multi-frame synchronization method of claim 1, in the method of detecting a multi-frame identification code from a bit stream having a multi-frame structure, a frame identification bit is added to a fixed length of serial data. In the receiving circuit that receives a bitstream that constitutes one multiframe by a predetermined number of the frames, the memory circuit that stores and holds the bitstream is used for the bitstream that is already stored and held. To detect the multi-frame identification code. Therefore, as in the conventional example, if the multi-frame identification code is not detected by scanning the number of bits for one multi-frame once, the number of bits is shifted by one bit, and then the number of bits for the next one multi-frame is scanned. Compared with the above, there is an effect that the multi-frame identification code can be detected in a short time when the maximum detection time is required.

According to the multi-frame synchronization method of the second aspect, the multi-frame identification code is detected even for the pseudo multi-frame synchronization acquisition which is caused by detecting the same pattern as the multi-frame identification code which is accidentally generated by the data string. By performing the above twice consecutively, there is an effect of reducing the capture probability.

[Brief description of drawings]

FIG. 1 is a block diagram of a multi-frame synchronization system according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram of a maximum detection period of a multi-frame identification code in the multi-frame synchronization system according to the embodiment of the present invention.

FIG. 3 is a timing chart at the start of bitstream reception in a multi-frame synchronization system according to an embodiment of the present invention.

FIG. 4 is a timing chart at the end of reception of a multi-frame synchronization type bit stream according to an embodiment of the present invention.

FIG. 5 is a timing chart when the pattern of “100110100110” of the multi-frame synchronization system of one embodiment of the present invention is detected.

FIG. 6 is an operation explanatory diagram of an arithmetic circuit of a multi-frame synchronization system according to an embodiment of the present invention.

FIG. 7 is a block diagram of a conventional multi-frame synchronization system.

FIG. 8 is an explanatory diagram of a frame structure showing the maximum detection time in the conventional multi-frame identification code detection.

[Explanation of symbols]

 1 cyclic counter 2,3 counter 4 control circuit 5 memory circuit 6 shift register 7 decoder 8 arithmetic circuit 9 12 bit 2 input comparator 10,11 clock signal 12 bit stream signal 13,16 control signal 14,15 control clock signal 17 multi Frame sync signal

Claims (2)

[Claims] 1. A receiving circuit for receiving a bitstream, which comprises one frame by adding a frame identification bit to a fixed length of serial data to form one frame, and receiving the bitstream. A cyclic counter that starts operation by incrementing by 1 bit for each bit of the bit stream and free-runs with the number of bits of 1 multiframe as an upper limit; a memory circuit that stores and holds the bit stream; and a number of bits of the bit stream. And a control circuit for writing the bit stream to the memory circuit until a control signal is output based on the count number of the first counter And the operation is started by the control signal of the first counter. Then, the number of bits in one frame is incremented, the count value is reset when the number of counts exceeds a certain number of bits, and then the number of bits in one frame is incremented again from a value one greater than the previous count start value. A second counter for performing the above, and the number of counters of the second counter and a control signal of the first counter, the contents of the memory circuit are read at a higher speed than the bit rate of the bit stream, and the read pattern is a multi-frame identification code. A first determination circuit for determining whether or not the output of the first determination circuit calculates the number of counters of the second counter, an output of the arithmetic circuit and a counter of the cyclic counter And a second determination circuit for comparing the number with a multi-frame. -Time synchronization method. 2. The constant bit number value of the first counter has a margin larger than the minimum bit number required for multiframe synchronization, and the multiframe identification code detection operation is performed a plurality of times. The multi-frame synchronization method according to claim 1.