JPH08149118A - Synchronizing signal detector - Google Patents

Abstract

PURPOSE: To detect a synchronizing signal correctly without mistaking a similar synchronizing signal as a synchronizing signal from a bit series including the synchronizing signal and a signal having the same bit pattern as the synchronizing signal and whose appearance time interval is the same as that of the synchronizing signal (hereinafter called similar synchronizing signal) at least. CONSTITUTION: Taking notice that the number of bits from a synchronizing signal to a similar synchronizing signal and the number of bits from the similar synchronizing signal to the synchronizing signal differ from each other, the number of bits between the synchronizing signal and the similar synchronizing signal is counted to identify the synchronizing signal and when a signal series is given to a synchronizing signal candidate pattern detector 1, in which the pattern of the synchronizing signal is detected from the received signal and the period when the signal appears is calculated and the signal of the same bit pattern as that of the synchronizing signal in the data is excluded and the synchronizing signal or the similar synchronizing signal or the both signals are outputted. The outputted signal is used as a reset signal and the counter 2 is operated and counts up by using the clock signal synchronously with the bit of the input signal and the count is fed to a discrimination device 3, which discriminates the synchronizing signal based on numeral data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a sync signal detecting device.

[0002]

2. Description of the Related Art A conventionally proposed sync signal detecting apparatus takes advantage of the fact that the time interval at which the sync signal appears is constant, so that a signal of the same bit sequence as the sync signal is taken out and its cycle is the same as that of the sync signal. It was identified whether there was, and if they were the same, it was detected as a synchronization signal.

[0003]

However, if the signal has the same bit pattern as the sync signal and the time interval at which the signal appears is the same as the sync signal (hereinafter, sync similar signal), for example, the MPEG transmission standard. In the program identification signal (PID), if a sync-similar signal is detected, the sync-similar signal is always detected, and since the sync signal is not detected, there is a problem that the digital signal cannot be processed correctly. It was

Therefore, the present invention has been made to solve the above-mentioned problems, and is capable of detecting a sync signal and performing correct digital signal processing even for a signal sequence having both a sync signal and a sync-similar signal. An object of the present invention is to provide a detection device.

[0005]

In order to achieve the above object, a video signal reproducing apparatus of the present invention has a number of bits from a sync signal to a sync-similar signal sync signal and a number of bits from a sync-similar signal to a sync signal. Focusing on the difference, the number of bits between the sync signal and the sync-like signal is counted to identify the sync signal, that is, the sync signal and the sync signal may have the same cycle as the sync signal. A signal sequence including at least a signal and a signal having the same bit sequence (hereinafter, referred to as a synchronization similar signal) as an input signal, and a synchronization signal candidate for detecting and outputting the synchronization signal and the synchronization similar signal from the input signal. The difference between the output value of the pattern detection means and the counting means for counting and outputting the number of bits between the outputs sequentially output from the synchronization signal candidate pattern detection means and the output value of the counting means Ri, distinguishes between synchronous signals and the synchronizing similar signals among the signals output from the synchronizing signal and the synchronizing similar signals, a configuration of the sync signal detection apparatus comprising a judging means for outputting a synchronization signal.

[0006]

With the above-described structure, the present invention can correctly detect a sync signal even for a signal series having both a sync signal and a sync-similar signal.

[0007]

【Example】

(Embodiment 1) An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing a video signal reproducing apparatus of the present invention. FIG. 2 shows an MPEG bit sequence.

In FIG. 1, 1 is a sync signal candidate pattern detector, 2 is a counter, and 3 is a discriminator. In order to easily understand this embodiment, the input signal is MP
The bit sequence of EG.

FIG. 2 shows an MPEG bit sequence. In this bit sequence, it is the program identification signal that can be the synchronization-like signal. When the signal sequence is input to the sync signal candidate pattern detector 1, the sync signal candidate pattern detector 1 has 00001111 which is the bit pattern of the sync signal.
From the input signal, calculate the period in which the signal appears, eliminate the signal of the same bit pattern as the synchronization signal in the payload data such as video data, and synchronize or synchronize the similar signal or its Output both signals. The counter 2 operates using the signal output from the synchronization signal candidate pattern detector 1 as a reset signal.
The counter 2 counts up with a clock synchronized with the bits of the input signal and outputs the value to the discriminator 3. The discriminator 3 discriminates the sync signal from the numerical data sent from the counter 2. This state will be described below in more detail in three types.

(1) When there is no synchronous analog signal in the input signal. Since the transport stream packet is 188 bytes, at this time, the counter 2 counts up to 1498 and returns to 0. Therefore, 1498
Will be counted up for a while (eg 3
(Up to 4 times), the detected pattern is determined to be a sync signal, and the discriminator 3 outputs the sync signal.

(2) In the case where there is a sync-similar signal in the input signals and the sync signal is detected first. Of the 13 bits of the PID, the lower 8 bits have the same bit pattern as the synchronization signal, that is, 01000111.

The counter 2 counts up by the sync signal detected by the sync signal candidate pattern detector 1 and counts up to 9. On the other hand, the counter 2 counts up by the sync-similar signal detected by the sync-signal candidate pattern detector 1, and counts up to 1483.

The larger output value of the counter 2 is 1483.
Is. The output signal of the sync signal candidate pattern detector 1 immediately after counting up to 1483 is used as the sync signal.
That is, the one that counts up to 9 becomes the synchronization signal. This is the correct sync signal.

(3) In the case where there is a sync-like signal in the input signals and the sync-like signal is detected first. Similar to the case of (2), the discriminator 3 makes the following discrimination.

The larger output value of the counter 2 is 1483.
Is. The output signal of the sync signal candidate pattern detector 1 immediately after counting up 1483 is used as the sync signal. That is, the one that counts up to 9 becomes the synchronization signal. This is the correct sync signal.

In this embodiment, the MPEG transmission bit stream is assumed, but it goes without saying that it is applicable to a signal sequence including the same bit pattern as the synchronization signal. At this time, the sync signal can be discriminated by utilizing the bit difference between the sync signal and the sync-similar signal and the bit difference between the sync-similar signal and the sync signal in the embodiment. (Embodiment 2) FIG. 3 shows the configuration of Embodiment 2. Also, FIG.
Shows the window waveform.

A second embodiment will be described with reference to FIGS. 3 and 4. The second embodiment differs from the first embodiment in that a window waveform is generated from the output from the sync signal candidate pattern detector and the input signal of the sync signal candidate pattern detector is AND masked by the window waveform. The sync signal can be detected earlier than in the first embodiment without detecting the same bit pattern as the sync signal in the data.

FIG. 3 shows the above circuit, 1 is a sync signal candidate pattern detector, 2 is a counter, and 3 is a discriminator, which are the same as those in the first embodiment. Reference numeral 11 is an AND mask, and 12 is a window generation circuit, which are different from the first embodiment.

In FIG. 4, (a) is an input signal M
A PEG bit stream, (b) is an output of the sync signal candidate pattern detector 1, and (c) is a window waveform.
As in the first embodiment, the input signal is an MPEG bit sequence.

The signal input to the AND mask 11 is AND masked by the output from the window generation circuit 12, but the output from the window generation circuit 12 is the "H" signal for the first input signal. , That is,
All are "1" signals. Therefore, the same signal as the signal input to the AND mask 11 is input to the synchronization signal candidate pattern detector 1. The operation of the sync signal candidate pattern detector 1 is the same as that of the first embodiment, and therefore its explanation is omitted here. The output signal from the sync signal candidate pattern detector 1 is sent to the window generation circuit 12 and the counter 2. Since the operations of the counter 2 and the discriminator 3 are the same as those in the first embodiment, the description thereof will be omitted here. The window generation circuit 12 outputs the waveform of (c) of FIG. 4 from the output signal from the synchronization signal candidate pattern detector 1. That is, from 16 bits before the leading edge to 16 bits after the trailing edge of the output signal from the sync signal candidate pattern detector 1,
The H ”signal is output. The waveform output from the window generation circuit 12 is sent to the AND mask circuit 11, the input signal is AND masked, and the AND signal is sent to the sync signal candidate pattern detector 1. When the input signal does not reach 1504 bits or more, the window generation circuit 12 outputs a "H" signal, that is, a signal of all "1" for 1504 bits.

By introducing the window generation circuit 12 that performs the above operation, the same bit pattern as the sync signal in the data is not detected, and the sync signal can be detected faster than in the first embodiment. You can do it.

[0022]

As is apparent from the above description of the embodiments, according to the present invention, the number of bits from the sync signal to the sync-similar signal sync signal is different from the number of bits from the sync-similar signal to the sync signal. Focusing attention, by counting the number of bits between the sync signal and the sync-similar signal, the sync signal is detected even for a signal series having both the sync signal and the sync-similar signal, and correct digital signal processing is performed. The present invention provides a synchronization signal detecting device that can perform the above.

[Brief description of drawings]

FIG. 1 is a block diagram showing a sync signal detection device according to an embodiment of the present invention.

Fig. 2 Schematic diagram of MPEG bitstream

FIG. 3 is a block diagram showing a synchronization signal detecting device according to another embodiment of the present invention.

FIG. 4 is a diagram showing a window waveform.

[Explanation of symbols]

 1 sync signal candidate pattern detector 2 counter 3 discriminator 11 AND mask circuit 12 window generation circuit

Continuation of front page (51) Int.Cl. ⁶ Identification number Internal reference number FI Technical location H04N 7/24 (72) Inventor Kenji Morimoto 1006 Kadoma, Kadoma, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Inventor Akihiro Takeuchi 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd.

Claims (5)

[Claims] 1. A signal sequence including at least both a synchronization signal and a signal having the same bit sequence as that of the synchronization signal, which may have the same period as the synchronization signal (hereinafter referred to as a synchronization similar signal), is used as an input signal. A synchronizing signal candidate pattern detecting means for detecting and outputting the synchronizing signal and the synchronizing similar signal from an input signal, and a counting means for counting and outputting the number of bits between outputs sequentially output from the synchronizing signal candidate pattern detecting means. And a discriminating means for discriminating between the sync signal and the sync-similar signal among the signals output from the sync signal and the sync-similar signal based on the difference between the output values of the counting means, and outputting the sync signal. A synchronization signal detection device characterized by the above. 2. The synchronizing signal detecting device according to claim 1, wherein the discriminating means discriminates an output from the synchronizing signal candidate pattern detecting means immediately after the output value of the counting means becomes the largest as a synchronizing signal. . 3. A synchronizing signal candidate pattern detecting means for generating a signal for a certain period of time from an output from the synchronizing signal candidate pattern detecting means, and a window generating means for outputting the signal and masking the input with the output from the window generating means. 2. The synchronization signal detecting device according to claim 1, further comprising a masking unit for outputting a signal to the. 4. The synchronizing signal detecting apparatus according to claim 3, wherein the window generating means is a window generating means for generating a "high" signal for a certain period of time, and the masking means is an AND mask. 5. Selecting 1504 bits as the cycle according to claim 1, and selecting a period from 16 bits before the trailing edge to 16 bits after the leading edge of the output from the sync signal candidate pattern detecting means as the certain period. 4. The method according to claim 3,
The synchronization signal detection device described.